JP5190225B2 - 半導体装置及びその作製方法 - Google Patents
半導体装置及びその作製方法 Download PDFInfo
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- JP5190225B2 JP5190225B2 JP2007187883A JP2007187883A JP5190225B2 JP 5190225 B2 JP5190225 B2 JP 5190225B2 JP 2007187883 A JP2007187883 A JP 2007187883A JP 2007187883 A JP2007187883 A JP 2007187883A JP 5190225 B2 JP5190225 B2 JP 5190225B2
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- insulating film
- semiconductor film
- film
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- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 1
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Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
- H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
- H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/764—Air gaps
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Thin Film Transistor (AREA)
Description
本発明の半導体装置において、半導体素子が有する半導体膜と、該半導体膜と重なるように配置された空洞の構成について、図1を用いて説明する。図1(A)は、本発明で用いられる半導体素子が有する半導体膜100と、空洞101の断面図である。
μ=τq/m*
δ=αPa4/(Et3)
本発明の半導体装置において、半導体素子が有する半導体膜と、該半導体膜と重なるように配置された空洞の構成について、図2を用いて説明する。図2(A)は、本発明で用いられる半導体素子が有する半導体膜200と、空洞201の断面図である。
本実施の形態では、本発明の半導体装置が有するトランジスタの、より具体的な構成について説明する。図3(A)は、本実施の形態のトランジスタの上面図である。また図3(B)は、図3(A)に示す上面図の破線A−A’における断面図であり、図3(C)は、図3(A)に示す上面図の破線B−B’における断面図である。
本実施の形態では、本発明の半導体装置が有するトランジスタの、より具体的な構成について説明する。図4(A)は、本実施の形態のトランジスタの上面図である。また図4(B)は、図4(A)に示す上面図の破線A−A’における断面図であり、図4(C)は、図4(A)に示す上面図の破線B−B’における断面図である。
本実施の形態では、本発明の半導体装置が有するトランジスタの、より具体的な構成について説明する。図5(A)は、本実施の形態のトランジスタの上面図である。また図5(B)は、図5(A)に示す上面図の破線A−A’における断面図であり、図5(C)は、図5(A)に示す上面図の破線B−B’における断面図である。
本実施の形態では、半導体基板(ボンド基板)を用いて、支持基板(ベース基板)上に、凹部を有する半導体膜を形成する、本発明の半導体装置の作製方法について説明する。
本実施の形態では、半導体基板(ボンド基板)を用いて、開口部を有する絶縁膜が形成された支持基板(ベース基板)に半導体膜を形成する、本発明の半導体装置の作製方法について説明する。
本実施の形態では、本発明の半導体装置におけるトランジスタの具体的な作製方法の一例について説明する。なお、本実施の形態では実施の形態7に示す作製方法により形成された半導体膜を用いる場合について説明するが、実施の形態6に示す作製方法により形成された半導体膜を用いていても良い。
101 空洞
102 ベース基板
103 絶縁膜
104 絶縁膜
105 破線
106 領域
107 領域
108 チャネル形成領域
109 不純物領域
110 ゲート絶縁膜
111 電極
200 半導体膜
201 空洞
202 ベース基板
203 絶縁膜
205 破線
206 領域
207 領域
208 チャネル形成領域
209 不純物領域
210 ゲート絶縁膜
211 電極
300 半導体膜
301 電極
302 ゲート絶縁膜
303 不純物領域
305 チャネル形成領域
306 ベース基板
307 空洞
308 LDD領域
310 サイドウォール
400 半導体膜
401 電極
402 ゲート絶縁膜
403 不純物領域
405 チャネル形成領域
406 ベース基板
407 空洞
408 LDD領域
410 サイドウォール
411 絶縁膜
420 半導体膜
421 電極
422 ゲート絶縁膜
423 不純物領域
425 チャネル形成領域
426 ベース基板
427 空洞
428 LDD領域
430 サイドウォール
431 絶縁膜
432 絶縁膜
501 ベース基板
502 絶縁膜
503 半導体膜
504 半導体膜
505 空洞
506 ゲート絶縁膜
507 電極
508 不純物領域
509 不純物領域
510 サイドウォール
511 高濃度不純物領域
512 低濃度不純物領域
513 チャネル形成領域
514 高濃度不純物領域
515 低濃度不純物領域
516 チャネル形成領域
517 トランジスタ
518 トランジスタ
519 絶縁膜
520 絶縁膜
521 導電膜
522 導電膜
600 ボンド基板
601 絶縁膜
602 欠陥層
604 凹部
605 絶縁膜
606 ベース基板
607 絶縁膜
608 半導体膜
609 空洞
610 半導体膜
611 トランジスタ
700 ボンド基板
701 絶縁膜
702 欠陥層
703 絶縁膜
704 ベース基板
705 開口部
706 絶縁膜
707 半導体膜
708 空洞
709 半導体膜
710 トランジスタ
800 基板
801 演算回路
802 演算回路用制御部
803 命令解析部
804 制御部
805 タイミング制御部
806 レジスタ
807 レジスタ制御部
808 バスインターフェース
809 メモリ
820 メモリ用インターフェース
900 RFタグ
901 アンテナ
902 集積回路
903 電源回路
904 復調回路
905 変調回路
906 レギュレータ
907 制御回路
909 メモリ
1801 開口部
1802 絶縁膜
1803 ベース基板
1804 ボンド基板
1805 半導体膜
1806 半導体装置
2001 トランジスタ
2002 トランジスタ
2003 配線
2004 配線
2005 配線
2006 配線
2007 配線
2008 半導体膜
2009 空洞
2010 半導体膜
2101 本体
2102 表示部
2103 音声入力部
2104 音声出力部
2105 操作キー
2401 筐体
2402 表示部
2403 スピーカー部
2601 本体
2602 表示部
2603 筐体
2604 外部接続ポート
2605 リモコン受信部
2606 受像部
2607 バッテリー
2608 音声入力部
2609 操作キー
2610 接眼部
3001 トランジスタ
3002 トランジスタ
3003 トランジスタ
3004 トランジスタ
3005 半導体膜
3006 半導体膜
3007 配線
3008 配線
3009 配線
3010 配線
3011 配線
3012 配線
3013 空洞
Claims (3)
- ベース基板と、
前記ベース基板側に凹部が設けられた半導体膜と、を有し、
前記ベース基板と前記凹部の間には空洞が設けられており、前記半導体膜のうち前記空洞と重なる領域は前記ベース基板側に向かって歪んでおり、
前記半導体膜はゲルマニウムを有し、
前記半導体膜は(100)面においてキャリアの移動する方向が[011]であることを特徴とする半導体装置。 - ベース基板と、
半導体膜と、
前記ベース基板と前記半導体膜の間において開口部を有する絶縁膜と、を有し、
前記開口部により前記半導体膜と前記ベース基板との間には空洞が設けられており、前記半導体膜のうち前記空洞と重なる領域は前記ベース基板側に向かって歪んでおり、
前記半導体膜はゲルマニウムを有し、
前記半導体膜は(100)面においてキャリアの移動する方向が[011]であることを特徴とする半導体装置。 - 開口部または凹部を有する絶縁膜をベース基板上に形成し、
前記絶縁膜を間に挟んで、前記ベース基板上にボンド基板を減圧雰囲気下で貼り合わせ、
前記ボンド基板を劈開させることで、前記絶縁膜上に、前記開口部または前記凹部を覆うように半導体膜を形成し、
前記減圧雰囲気下での貼り合わせにより、前記絶縁膜の前記開口部または前記凹部が前記ベース基板と前記ボンド基板との間に挟まれることで空洞が形成され、
大気雰囲気下にさらすことにより、前記半導体膜のうち前記空洞と重なる領域は、前記ベース基板側に向かって歪むことを特徴とする半導体装置の作製方法。
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