JP2008311636A - 半導体装置の作製方法、表示装置の作製方法、半導体装置、表示装置及び電子機器 - Google Patents
半導体装置の作製方法、表示装置の作製方法、半導体装置、表示装置及び電子機器 Download PDFInfo
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- JP2008311636A JP2008311636A JP2008126115A JP2008126115A JP2008311636A JP 2008311636 A JP2008311636 A JP 2008311636A JP 2008126115 A JP2008126115 A JP 2008126115A JP 2008126115 A JP2008126115 A JP 2008126115A JP 2008311636 A JP2008311636 A JP 2008311636A
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Images
Classifications
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
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- H01L29/66409—Unipolar field-effect transistors
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Abstract
【解決手段】単結晶半導体基板の表面から所定の深さにイオンドーピング層を形成し、単結晶半導体基板上に第1の絶縁層を形成し、絶縁性基板上の一部に第2の絶縁層を形成し、第2の絶縁層上に非単結晶半導体層を形成し、第1の絶縁層を介して、単結晶半導体基板を絶縁性基板の第2の絶縁層が形成されていない領域に接合させ、単結晶半導体基板を、イオンドーピング層において分離させることにより、絶縁性基板上に単結晶半導体層を形成する。
【選択図】図1
Description
本実施の形態では、本発明に用いる半導体基板の作製方法を、図1乃至図7を用いて以下に説明する。なお、本実施の形態に係る半導体基板は、その一部を、単結晶半導体基板から、異種基板(以下、「ベース基板」という)に転写して形成するものである。
本実施の形態では、実施の形態1にて作製した半導体基板を用いて液晶表示装置を製造する方法について、図8乃至11を用いて以下に説明する。
実施の形態2では、液晶表示装置を用いる表示装置を作製する例を示したが、本実施の形態においてはその他の表示装置について図12を用いて説明する。
本発明の表示装置を用いた電子機器について、図13を参照して説明する。
110 ベース基板
120 絶縁層
122 接合層
124 窒素含有絶縁層
126 酸化シリコン層
130 単結晶半導体層
140 絶縁層
150 非単結晶半導体層
160 絶縁層
162 バリア層
164 接合層
400 ベース基板
402 絶縁層
404 半導体層
408 レーザー光
410 結晶性半導体層
500 単結晶半導体基板
502 イオン
504 イオンドーピング層
506 絶縁層
508 接合層
510 単結晶半導体基板
512 単結晶半導体層
800 基板
802 絶縁層
804 接合層
806 絶縁層
808 絶縁層
809 絶縁層
810 非単結晶半導体層
811 単結晶半導体層
812 ゲート絶縁層
814 ゲート電極
816 絶縁層
818 サイドウォール絶縁層
819 導電層
820 表示部
821 非単結晶半導体層
822 画素回路部
823 不純物領域
824 低濃度不純物領域
825 チャネル形成領域
826 高濃度不純物領域
830 駆動回路部
831 単結晶半導体層
832 周辺回路部
833 不純物領域
834 低濃度不純物領域
835 チャネル形成領域
836 高濃度不純物領域
841 単結晶半導体層
843 不純物領域
844 低濃度不純物領域
845 チャネル形成領域
846 高濃度不純物領域
850 駆動回路部
860 画素電極
870 端子領域
874 端子電極
876 異方性導電層
878 外部入力端子
880 シール材
882 配向膜
884 液晶層
886 スペーサ
887 配向膜
888 対向電極
889 カラーフィルター
890 基板
891 偏光板
892 偏光板
1210 発光素子
1212 画素電極
1214 有機化合物層
1216 対向電極
1218 隔壁層
1220 空間
1230 マイクロカプセル
1232 画素電極
1234 対向電極
1236 バインダ
1240 電気泳動層
1400 基板
1401 画素部
1402 画素
1403 走査線側入力端子
1404 信号線側入力端子
1450 FPC(Flexible Printed Circuit)
1451 IC
1460 駆動回路
2001 筺体
2002 支持台
2003 表示部
2004 スピーカー部
2005 ビデオ入力端子
2101 本体
2102 表示部
2103 受像部
2104 操作キー
2105 外部接続ポート
2106 シャッターボタン
2201 本体
2202 筐体
2203 表示部
2204 キーボード
2205 外部接続ポート
2206 ポインティングデバイス
2301 本体
2302 表示部
2303 スイッチ
2304 操作キー
2305 赤外線ポート
2401 本体
2402 筐体
2403 表示部A
2404 表示部B
2405 記録媒体読み込み部
2406 操作キー
2407 スピーカー部
2501 本体
2502 表示部
2503 操作キー
2601 本体
2602 表示部
2603 筐体
2604 外部接続ポート
2605 リモコン受信部
2606 受像部
2607 バッテリー
2608 音声入力部
2609 操作キー
2610 接眼部
2701 本体
2702 筐体
2703 表示部
2704 音声入力部
2705 音声出力部
2706 操作キー
2707 外部接続ポート
2708 アンテナ
Claims (33)
- 単結晶半導体基板の表面から所定の深さにイオンドーピング層を形成し、前記単結晶半導体基板上に第1の絶縁層を形成し、
絶縁性基板上の一部に第2の絶縁層を形成し、前記第2の絶縁層上に非単結晶半導体層を形成し、
前記第1の絶縁層を介して、前記単結晶半導体基板を前記絶縁性基板の前記第2の絶縁層が形成されていない領域に接合させ、
前記単結晶半導体基板を、前記イオンドーピング層において分離させることにより、前記絶縁性基板上に単結晶半導体層を形成することを特徴とする半導体装置の作製方法。 - 単結晶半導体基板の表面から所定の深さにイオンドーピング層を形成し、前記単結晶半導体基板上に第1の絶縁層を形成し、
絶縁性基板上の一部に第2の絶縁層を形成し、前記第2の絶縁層上に非単結晶半導体層を形成し、
前記第1の絶縁層を介して、前記単結晶半導体基板を前記絶縁性基板の前記第2の絶縁層が形成されていない領域に接合させ、
前記単結晶半導体基板を、前記イオンドーピング層において分離させることにより、前記絶縁性基板上に単結晶半導体層を形成し、
前記絶縁性基板上の前記単結晶半導体層を用いて高速動作が要求される回路を形成し、
前記絶縁性基板上の前記非単結晶半導体層を用いて高速動作が要求されない回路を形成することを特徴とする半導体装置の作製方法。 - 請求項1又は2において、
前記第1の絶縁層又は前記第2の絶縁層は、積層構造で形成することを特徴とする半導体装置の作製方法。 - 請求項3において、
前記第1の絶縁層の前記単結晶半導体層と接する部分と、前記第2の絶縁層の前記非単結晶半導体層と接する部分とは、同じ材料を用いて形成することを特徴とする半導体装置の作製方法。 - 請求項3又は4において、
前記第1の絶縁層の前記単結晶半導体層と接する部分、及び前記第2の絶縁層の前記非単結晶半導体層と接する部分として、酸化窒化シリコン層を形成し、
前記酸化窒化シリコン層に接するように窒化酸化シリコン層を形成することを特徴とする半導体装置の作製方法。 - 請求項3乃至5のいずれか一において、
前記第1の絶縁層の前記絶縁性基板と接する部分として、酸化シリコン層を形成することを特徴とする半導体装置の作製方法。 - 請求項1乃至6のいずれか一において、
前記非単結晶半導体層の膜厚より前記単結晶半導体層の膜厚を小さくすることを特徴とする半導体装置の作製方法。 - 請求項1乃至7のいずれか一において、
前記単結晶半導体層の膜厚と前記第1の絶縁層の膜厚との和を、前記非単結晶半導体層の膜厚と前記第2の絶縁層の膜厚との和に等しくすることを特徴とする半導体装置の作製方法。 - 請求項1乃至8のいずれか一において、
前記絶縁性基板上に前記単結晶半導体層を形成した後にレーザー光を照射することで、前記単結晶半導体層及び前記非単結晶半導体層の特性を向上させることを特徴とする半導体装置の作製方法。 - 単結晶半導体基板の表面から所定の深さにイオンドーピング層を形成し、前記単結晶半導体基板上に第1の絶縁層を形成し、
絶縁性基板上の一部に第2の絶縁層を形成し、前記第2の絶縁層上に非単結晶半導体層を形成し、
前記第1の絶縁層を介して、前記単結晶半導体基板を前記絶縁性基板の前記第2の絶縁層が形成されていない領域に接合させ、
前記単結晶半導体基板を、前記イオンドーピング層において分離させることにより、前記絶縁性基板上に単結晶半導体層を形成し、
前記絶縁性基板上の前記単結晶半導体層を用いて駆動回路を形成し、
前記絶縁性基板上の前記非単結晶半導体層を用いて表示部の回路を形成することを特徴とする表示装置の作製方法。 - 請求項10において、
前記第1の絶縁層又は前記第2の絶縁層は、積層構造で形成されることを特徴とする表示装置の作製方法。 - 請求項11において、
前記第1の絶縁層の前記単結晶半導体層と接する部分と、前記第2の絶縁層の前記非単結晶半導体層と接する部分とは、同じ材料を用いて形成されることを特徴とする表示装置の作製方法。 - 請求項11又は12において、
前記第1の絶縁層の前記単結晶半導体層と接する部分、及び前記第2の絶縁層の前記非単結晶半導体層と接する部分として、酸化窒化シリコン層を形成し、
前記酸化窒化シリコン層に接するように窒化酸化シリコン層を形成することを特徴とする表示装置の作製方法。 - 請求項11乃至13のいずれか一において、
前記第1の絶縁層の前記絶縁性基板と接する部分として、酸化シリコン層を形成することを特徴とする表示装置の作製方法。 - 請求項10乃至14のいずれか一において、
前記非単結晶半導体層の膜厚より前記単結晶半導体層の膜厚を小さくすることを特徴とする表示装置の作製方法。 - 請求項10乃至15のいずれか一において、
前記単結晶半導体層の膜厚と前記第1の絶縁層の膜厚との和を、前記非単結晶半導体層の膜厚と前記第2の絶縁層の膜厚との和に等しくすることを特徴とする表示装置の作製方法。 - 請求項10乃至16のいずれか一において、
前記絶縁性基板上に前記単結晶半導体層を形成した後にレーザー光を照射することで、前記単結晶半導体層及び前記非単結晶半導体層の特性を向上させることを特徴とする半導体装置の作製方法。 - 絶縁性基板上の第1の絶縁層及び第2の絶縁層と、
前記第1の絶縁層上の単結晶半導体層と、
前記第2の絶縁層上の非単結晶半導体層と、を有することを特徴とする半導体装置。 - 絶縁性基板上の第1の絶縁層及び第2の絶縁層と、
前記第1の絶縁層上の単結晶半導体層と、
前記第2の絶縁層上の非単結晶半導体層と、を有し、
前記単結晶半導体層は高速動作が要求される回路を形成するために用いられ、
前記非単結晶半導体層は、高速動作が要求されない回路を形成するために用いられたことを特徴とする半導体装置。 - 請求項18又は19において、
前記第1の絶縁層又は前記第2の絶縁層は、積層構造を有することを特徴とする半導体装置。 - 請求項20において、
前記第1の絶縁層の前記単結晶半導体層と接する部分と、前記第2の絶縁層の前記非単結晶半導体層と接する部分とは、同じ材料で形成されたことを特徴とする半導体装置。 - 請求項20又は21において、
前記第1の絶縁層の前記単結晶半導体層と接する部分、及び前記第2の絶縁層の前記非単結晶半導体層と接する部分は、酸化窒化シリコン層であり、
前記酸化窒化シリコン層に接するように窒化酸化シリコン層が設けられたことを特徴とする半導体装置。 - 請求項20乃至22のいずれか一において、
前記第1の絶縁層の前記絶縁性基板と接する部分は、酸化シリコン層であることを特徴とする半導体装置。 - 請求項18乃至23のいずれか一において、
前記非単結晶半導体層の膜厚より前記単結晶半導体層の膜厚が小さいことを特徴とする半導体装置。 - 請求項18乃至24のいずれか一において、
前記単結晶半導体層の膜厚と前記第1の絶縁層の膜厚との和が、前記非単結晶半導体層の膜厚と前記第2の絶縁層の膜厚との和に等しいことを特徴とする半導体装置。 - 絶縁性基板上の第1の絶縁層及び第2の絶縁層と、
前記第1の絶縁層上の単結晶半導体層と、
前記第2の絶縁層上の非単結晶半導体層と、を有し、
前記単結晶半導体層は駆動回路を形成するために用いられ、
前記非単結晶半導体層は、表示部の回路を形成するために用いられたことを特徴とする表示装置。 - 請求項26において、
前記第1の絶縁層又は前記第2の絶縁層は、積層構造を有することを特徴とする表示装置。 - 請求項27において、
前記第1の絶縁層の前記単結晶半導体層と接する部分と、前記第2の絶縁層の前記非単結晶半導体層と接する部分とは、同じ材料で形成されたことを特徴とする表示装置。 - 請求項27又は28において、
前記第1の絶縁層の前記単結晶半導体層と接する部分、及び前記第2の絶縁層の前記非単結晶半導体層と接する部分は、酸化窒化シリコン層であり、
前記酸化窒化シリコン層に接するように窒化酸化シリコン層が設けられたことを特徴とする半導体装置。 - 請求項27乃至29のいずれか一において、
前記第1の絶縁層の前記絶縁性基板と接する部分は、酸化シリコン層であることを特徴とする半導体装置。 - 請求項26乃至30のいずれか一において、
前記非単結晶半導体層の膜厚より前記単結晶半導体層の膜厚が小さいことを特徴とする半導体装置。 - 請求項26乃至31のいずれか一において、
前記単結晶半導体層の膜厚と前記第1の絶縁層の膜厚との和が、前記非単結晶半導体層の膜厚と前記第2の絶縁層の膜厚との和に等しいことを特徴とする半導体装置。 - 請求項26乃至32のいずれか一に記載の表示装置を用いた電子機器。
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