JP5160238B2 - n−FET用途のためのHfSiN金属を形成する方法 - Google Patents
n−FET用途のためのHfSiN金属を形成する方法 Download PDFInfo
- Publication number
- JP5160238B2 JP5160238B2 JP2007551254A JP2007551254A JP5160238B2 JP 5160238 B2 JP5160238 B2 JP 5160238B2 JP 2007551254 A JP2007551254 A JP 2007551254A JP 2007551254 A JP2007551254 A JP 2007551254A JP 5160238 B2 JP5160238 B2 JP 5160238B2
- Authority
- JP
- Japan
- Prior art keywords
- hfsin
- stack
- dielectric
- gate
- metal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/60—Electrodes characterised by their materials
- H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
- H10D64/667—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/01—Manufacture or treatment
- H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
- H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
- H10D64/01304—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H10D64/01318—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/0212—Manufacture or treatment of FETs having insulated gates [IGFET] using self-aligned silicidation
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
- H10D30/0227—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/60—Electrodes characterised by their materials
- H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
- H10D64/667—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers
- H10D64/669—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers the conductor further comprising additional layers of alloy material, compound material or organic material, e.g. TaN/TiAlN
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/60—Electrodes characterised by their materials
- H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
- H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
- H10D64/681—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having a compositional variation, e.g. multilayered
- H10D64/685—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having a compositional variation, e.g. multilayered being perpendicular to the channel plane
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/60—Electrodes characterised by their materials
- H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
- H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
- H10D64/691—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator comprising metallic compounds, e.g. metal oxides or metal silicates
Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Formation Of Insulating Films (AREA)
- Electrodes Of Semiconductors (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US11/035,369 | 2005-01-13 | ||
| US11/035,369 US20060151846A1 (en) | 2005-01-13 | 2005-01-13 | Method of forming HfSiN metal for n-FET applications |
| PCT/US2005/043555 WO2006076087A2 (en) | 2005-01-13 | 2005-12-02 | METHOD OF FORMING HfSiN METAL FOR n-FET APPLICATIONS |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2008530770A JP2008530770A (ja) | 2008-08-07 |
| JP2008530770A5 JP2008530770A5 (https=) | 2008-11-06 |
| JP5160238B2 true JP5160238B2 (ja) | 2013-03-13 |
Family
ID=36652441
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2007551254A Expired - Fee Related JP5160238B2 (ja) | 2005-01-13 | 2005-12-02 | n−FET用途のためのHfSiN金属を形成する方法 |
Country Status (7)
| Country | Link |
|---|---|
| US (3) | US20060151846A1 (https=) |
| EP (1) | EP1836732B1 (https=) |
| JP (1) | JP5160238B2 (https=) |
| CN (2) | CN101789370B (https=) |
| AT (1) | ATE526684T1 (https=) |
| TW (1) | TW200636870A (https=) |
| WO (1) | WO2006076087A2 (https=) |
Families Citing this family (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060151846A1 (en) * | 2005-01-13 | 2006-07-13 | International Business Machines Corporation | Method of forming HfSiN metal for n-FET applications |
| JP2006245461A (ja) * | 2005-03-07 | 2006-09-14 | Sony Corp | 半導体装置およびその製造方法 |
| US7301219B2 (en) * | 2005-06-06 | 2007-11-27 | Macronix International Co., Ltd. | Electrically erasable programmable read only memory (EEPROM) cell and method for making the same |
| JP4455427B2 (ja) * | 2005-06-29 | 2010-04-21 | 株式会社東芝 | 半導体装置及びその製造方法 |
| US7425497B2 (en) * | 2006-01-20 | 2008-09-16 | International Business Machines Corporation | Introduction of metal impurity to change workfunction of conductive electrodes |
| US7611979B2 (en) * | 2007-02-12 | 2009-11-03 | International Business Machines Corporation | Metal gates with low charge trapping and enhanced dielectric reliability characteristics for high-k gate dielectric stacks |
| US7648868B2 (en) * | 2007-10-31 | 2010-01-19 | International Business Machines Corporation | Metal-gated MOSFET devices having scaled gate stack thickness |
| EP2123789A1 (en) * | 2008-05-15 | 2009-11-25 | Eifeler Werkzeuge GmbH | A method of producing hard coatings |
| US8350341B2 (en) | 2010-04-09 | 2013-01-08 | International Business Machines Corporation | Method and structure for work function engineering in transistors including a high dielectric constant gate insulator and metal gate (HKMG) |
| US8633534B2 (en) * | 2010-12-22 | 2014-01-21 | Intel Corporation | Transistor channel mobility using alternate gate dielectric materials |
| US8916427B2 (en) * | 2013-05-03 | 2014-12-23 | Texas Instruments Incorporated | FET dielectric reliability enhancement |
| KR102392059B1 (ko) * | 2013-07-29 | 2022-04-28 | 삼성전자주식회사 | 반도체 소자 및 그 제조 방법 |
| CN106158601A (zh) * | 2015-03-26 | 2016-11-23 | 比亚迪股份有限公司 | SiC基器件的栅介质层结构及栅介质层的形成方法 |
| CN105448742B (zh) * | 2015-12-30 | 2019-02-26 | 东莞市义仁汽车租赁有限公司 | 一种碳化硅材料上制备栅介质的方法 |
| US10446400B2 (en) * | 2017-10-20 | 2019-10-15 | Samsung Electronics Co., Ltd. | Method of forming multi-threshold voltage devices and devices so formed |
| CN110993603A (zh) * | 2019-12-09 | 2020-04-10 | 中国科学院微电子研究所 | 半导体结构及其形成方法 |
Family Cites Families (28)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6861356B2 (en) * | 1997-11-05 | 2005-03-01 | Tokyo Electron Limited | Method of forming a barrier film and method of forming wiring structure and electrodes of semiconductor device having a barrier film |
| US6313539B1 (en) * | 1997-12-24 | 2001-11-06 | Sharp Kabushiki Kaisha | Semiconductor memory device and production method of the same |
| US6413386B1 (en) * | 2000-07-19 | 2002-07-02 | International Business Machines Corporation | Reactive sputtering method for forming metal-silicon layer |
| JP2003069011A (ja) * | 2001-08-27 | 2003-03-07 | Hitachi Ltd | 半導体装置とその製造方法 |
| US20030111678A1 (en) * | 2001-12-14 | 2003-06-19 | Luigi Colombo | CVD deposition of M-SION gate dielectrics |
| US6797525B2 (en) * | 2002-05-22 | 2004-09-28 | Agere Systems Inc. | Fabrication process for a semiconductor device having a metal oxide dielectric material with a high dielectric constant, annealed with a buffered anneal process |
| WO2004027824A2 (en) * | 2002-09-18 | 2004-04-01 | Infineon Technologies Ag | Nitride and polysilicon interface with titanium layer |
| US6858524B2 (en) * | 2002-12-03 | 2005-02-22 | Asm International, Nv | Method of depositing barrier layer for metal gates |
| CN1263147C (zh) * | 2002-12-09 | 2006-07-05 | 旺宏电子股份有限公司 | 具有高介电常数隧穿介电层只读存储器的结构与制造方法 |
| US6803611B2 (en) * | 2003-01-03 | 2004-10-12 | Texas Instruments Incorporated | Use of indium to define work function of p-type doped polysilicon |
| JP2004221467A (ja) * | 2003-01-17 | 2004-08-05 | Fujitsu Ltd | 半導体装置及びその製造方法 |
| US6852645B2 (en) * | 2003-02-13 | 2005-02-08 | Texas Instruments Incorporated | High temperature interface layer growth for high-k gate dielectric |
| JP4489368B2 (ja) * | 2003-03-24 | 2010-06-23 | 株式会社日立製作所 | 半導体装置およびその製造方法 |
| JP2005005603A (ja) * | 2003-06-13 | 2005-01-06 | Toshiba Corp | 半導体装置及びその製造方法 |
| US7202186B2 (en) * | 2003-07-31 | 2007-04-10 | Tokyo Electron Limited | Method of forming uniform ultra-thin oxynitride layers |
| JP4933256B2 (ja) * | 2003-07-31 | 2012-05-16 | 東京エレクトロン株式会社 | 半導体微細構造物を形成する方法 |
| US6974779B2 (en) * | 2003-09-16 | 2005-12-13 | Tokyo Electron Limited | Interfacial oxidation process for high-k gate dielectric process integration |
| JP3790242B2 (ja) * | 2003-09-26 | 2006-06-28 | 株式会社東芝 | 半導体装置及びその製造方法 |
| US7351626B2 (en) * | 2003-12-18 | 2008-04-01 | Texas Instruments Incorporated | Method for controlling defects in gate dielectrics |
| US7737051B2 (en) * | 2004-03-10 | 2010-06-15 | Tokyo Electron Limited | Silicon germanium surface layer for high-k dielectric integration |
| JP2005317647A (ja) * | 2004-04-27 | 2005-11-10 | Toshiba Corp | 半導体装置及びその製造方法 |
| US7098516B2 (en) * | 2004-05-24 | 2006-08-29 | Texas Instruments Incorporated | Refractory metal-based electrodes for work function setting in semiconductor devices |
| US8399934B2 (en) * | 2004-12-20 | 2013-03-19 | Infineon Technologies Ag | Transistor device |
| US7282773B2 (en) * | 2004-09-14 | 2007-10-16 | Advanced Micro Devices Inc. | Semiconductor device with high-k dielectric layer |
| US7361608B2 (en) * | 2004-09-30 | 2008-04-22 | Tokyo Electron Limited | Method and system for forming a feature in a high-k layer |
| US20060068603A1 (en) * | 2004-09-30 | 2006-03-30 | Tokyo Electron Limited | A method for forming a thin complete high-permittivity dielectric layer |
| JP2006114747A (ja) * | 2004-10-15 | 2006-04-27 | Seiko Epson Corp | 半導体装置の製造方法 |
| US20060151846A1 (en) * | 2005-01-13 | 2006-07-13 | International Business Machines Corporation | Method of forming HfSiN metal for n-FET applications |
-
2005
- 2005-01-13 US US11/035,369 patent/US20060151846A1/en not_active Abandoned
- 2005-12-02 EP EP05826298A patent/EP1836732B1/en not_active Expired - Lifetime
- 2005-12-02 AT AT05826298T patent/ATE526684T1/de not_active IP Right Cessation
- 2005-12-02 JP JP2007551254A patent/JP5160238B2/ja not_active Expired - Fee Related
- 2005-12-02 CN CN2010101366125A patent/CN101789370B/zh not_active Expired - Fee Related
- 2005-12-02 WO PCT/US2005/043555 patent/WO2006076087A2/en not_active Ceased
- 2005-12-02 CN CN2005800465277A patent/CN101401211B/zh not_active Expired - Fee Related
-
2006
- 2006-01-09 TW TW095100785A patent/TW200636870A/zh unknown
-
2007
- 2007-10-19 US US11/875,524 patent/US7521346B2/en not_active Expired - Fee Related
-
2008
- 2008-06-18 US US12/141,476 patent/US20080245658A1/en not_active Abandoned
Also Published As
| Publication number | Publication date |
|---|---|
| EP1836732B1 (en) | 2011-09-28 |
| WO2006076087A2 (en) | 2006-07-20 |
| CN101789370A (zh) | 2010-07-28 |
| CN101401211A (zh) | 2009-04-01 |
| EP1836732A2 (en) | 2007-09-26 |
| CN101401211B (zh) | 2012-03-21 |
| CN101789370B (zh) | 2012-05-30 |
| JP2008530770A (ja) | 2008-08-07 |
| US20080038905A1 (en) | 2008-02-14 |
| TW200636870A (en) | 2006-10-16 |
| EP1836732A4 (en) | 2009-07-01 |
| US20060151846A1 (en) | 2006-07-13 |
| US7521346B2 (en) | 2009-04-21 |
| WO2006076087A3 (en) | 2008-11-13 |
| US20080245658A1 (en) | 2008-10-09 |
| ATE526684T1 (de) | 2011-10-15 |
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