JP5160238B2 - ｎ−ＦＥＴ用途のためのＨｆＳｉＮ金属を形成する方法 - Google Patents

ｎ−ＦＥＴ用途のためのＨｆＳｉＮ金属を形成する方法 Download PDF

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Publication number
JP5160238B2
JP5160238B2 JP2007551254A JP2007551254A JP5160238B2 JP 5160238 B2 JP5160238 B2 JP 5160238B2 JP 2007551254 A JP2007551254 A JP 2007551254A JP 2007551254 A JP2007551254 A JP 2007551254A JP 5160238 B2 JP5160238 B2 JP 5160238B2
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hfsin
stack
dielectric
gate
metal
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Expired - Fee Related
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JP2007551254A
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Japanese (ja)
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JP2008530770A5 (enExample
JP2008530770A (ja
Inventor
コールガリ、アレッサンドロ、シー
フランク、マーティン、エム
ジャミー、ラージャラオ
レーシー、ダイアン、エル
マクフィーリー、フェントン、アール
ザファー、スーフィー
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International Business Machines Corp
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International Business Machines Corp
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/667—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28088—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a composite, e.g. TiN
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0212—Manufacture or treatment of FETs having insulated gates [IGFET] using self-aligned silicidation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H10D30/0227—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/681—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having a compositional variation, e.g. multilayered
    • H10D64/685—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having a compositional variation, e.g. multilayered being perpendicular to the channel plane
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/691—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator comprising metallic compounds, e.g. metal oxides or metal silicates 

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Composite Materials (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Formation Of Insulating Films (AREA)
JP2007551254A 2005-01-13 2005-12-02 ｎ−ＦＥＴ用途のためのＨｆＳｉＮ金属を形成する方法 Expired - Fee Related JP5160238B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/035,369 2005-01-13
US11/035,369 US20060151846A1 (en) 2005-01-13 2005-01-13 Method of forming HfSiN metal for n-FET applications
PCT/US2005/043555 WO2006076087A2 (en) 2005-01-13 2005-12-02 METHOD OF FORMING HfSiN METAL FOR n-FET APPLICATIONS

Publications (3)

Publication Number Publication Date
JP2008530770A JP2008530770A (ja) 2008-08-07
JP2008530770A5 JP2008530770A5 (enExample) 2008-11-06
JP5160238B2 true JP5160238B2 (ja) 2013-03-13

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Family Applications (1)

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JP2007551254A Expired - Fee Related JP5160238B2 (ja) 2005-01-13 2005-12-02 ｎ−ＦＥＴ用途のためのＨｆＳｉＮ金属を形成する方法

Country Status (7)

Country Link
US (3) US20060151846A1 (enExample)
EP (1) EP1836732B1 (enExample)
JP (1) JP5160238B2 (enExample)
CN (2) CN101789370B (enExample)
AT (1) ATE526684T1 (enExample)
TW (1) TW200636870A (enExample)
WO (1) WO2006076087A2 (enExample)

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US20060151846A1 (en) * 2005-01-13 2006-07-13 International Business Machines Corporation Method of forming HfSiN metal for n-FET applications
JP2006245461A (ja) * 2005-03-07 2006-09-14 Sony Corp 半導体装置およびその製造方法
US7301219B2 (en) * 2005-06-06 2007-11-27 Macronix International Co., Ltd. Electrically erasable programmable read only memory (EEPROM) cell and method for making the same
JP4455427B2 (ja) * 2005-06-29 2010-04-21 株式会社東芝 半導体装置及びその製造方法
US7425497B2 (en) * 2006-01-20 2008-09-16 International Business Machines Corporation Introduction of metal impurity to change workfunction of conductive electrodes
US7611979B2 (en) * 2007-02-12 2009-11-03 International Business Machines Corporation Metal gates with low charge trapping and enhanced dielectric reliability characteristics for high-k gate dielectric stacks
US7648868B2 (en) * 2007-10-31 2010-01-19 International Business Machines Corporation Metal-gated MOSFET devices having scaled gate stack thickness
EP2123789A1 (en) * 2008-05-15 2009-11-25 Eifeler Werkzeuge GmbH A method of producing hard coatings
US8350341B2 (en) 2010-04-09 2013-01-08 International Business Machines Corporation Method and structure for work function engineering in transistors including a high dielectric constant gate insulator and metal gate (HKMG)
US8633534B2 (en) * 2010-12-22 2014-01-21 Intel Corporation Transistor channel mobility using alternate gate dielectric materials
US8916427B2 (en) * 2013-05-03 2014-12-23 Texas Instruments Incorporated FET dielectric reliability enhancement
KR102392059B1 (ko) * 2013-07-29 2022-04-28 삼성전자주식회사 반도체 소자 및 그 제조 방법
CN106158601A (zh) * 2015-03-26 2016-11-23 比亚迪股份有限公司 SiC基器件的栅介质层结构及栅介质层的形成方法
CN105448742B (zh) * 2015-12-30 2019-02-26 东莞市义仁汽车租赁有限公司 一种碳化硅材料上制备栅介质的方法
US10446400B2 (en) * 2017-10-20 2019-10-15 Samsung Electronics Co., Ltd. Method of forming multi-threshold voltage devices and devices so formed
CN110993603A (zh) * 2019-12-09 2020-04-10 中国科学院微电子研究所 半导体结构及其形成方法

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US6313539B1 (en) * 1997-12-24 2001-11-06 Sharp Kabushiki Kaisha Semiconductor memory device and production method of the same
US6413386B1 (en) * 2000-07-19 2002-07-02 International Business Machines Corporation Reactive sputtering method for forming metal-silicon layer
JP2003069011A (ja) * 2001-08-27 2003-03-07 Hitachi Ltd 半導体装置とその製造方法
US20030111678A1 (en) * 2001-12-14 2003-06-19 Luigi Colombo CVD deposition of M-SION gate dielectrics
US6797525B2 (en) * 2002-05-22 2004-09-28 Agere Systems Inc. Fabrication process for a semiconductor device having a metal oxide dielectric material with a high dielectric constant, annealed with a buffered anneal process
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Also Published As

Publication number Publication date
ATE526684T1 (de) 2011-10-15
CN101789370A (zh) 2010-07-28
EP1836732A2 (en) 2007-09-26
CN101401211B (zh) 2012-03-21
TW200636870A (en) 2006-10-16
CN101401211A (zh) 2009-04-01
US20080245658A1 (en) 2008-10-09
EP1836732B1 (en) 2011-09-28
US7521346B2 (en) 2009-04-21
JP2008530770A (ja) 2008-08-07
EP1836732A4 (en) 2009-07-01
CN101789370B (zh) 2012-05-30
US20060151846A1 (en) 2006-07-13
US20080038905A1 (en) 2008-02-14
WO2006076087A2 (en) 2006-07-20
WO2006076087A3 (en) 2008-11-13

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