JP5139039B2 - 半導体装置及びその製造方法 - Google Patents

半導体装置及びその製造方法 Download PDF

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Publication number
JP5139039B2
JP5139039B2 JP2007300790A JP2007300790A JP5139039B2 JP 5139039 B2 JP5139039 B2 JP 5139039B2 JP 2007300790 A JP2007300790 A JP 2007300790A JP 2007300790 A JP2007300790 A JP 2007300790A JP 5139039 B2 JP5139039 B2 JP 5139039B2
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JP
Japan
Prior art keywords
insulating layer
semiconductor device
semiconductor
connection terminal
wiring pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2007300790A
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English (en)
Japanese (ja)
Other versions
JP2009129982A (ja
JP2009129982A5 (https=
Inventor
孝治 山野
洋弘 町田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
Original Assignee
Shinko Electric Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Priority to JP2007300790A priority Critical patent/JP5139039B2/ja
Priority to KR1020080114951A priority patent/KR20090052282A/ko
Priority to US12/273,901 priority patent/US7906833B2/en
Priority to TW097144823A priority patent/TW200931595A/zh
Priority to CNA2008101809569A priority patent/CN101441992A/zh
Priority to EP08169571A priority patent/EP2065928A3/en
Publication of JP2009129982A publication Critical patent/JP2009129982A/ja
Publication of JP2009129982A5 publication Critical patent/JP2009129982A5/ja
Application granted granted Critical
Publication of JP5139039B2 publication Critical patent/JP5139039B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P54/00—Cutting or separating of wafers, substrates or parts of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/129—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed forming a chip-scale package [CSP]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/131—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed
    • H10W74/147—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed the encapsulations being multilayered
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/921—Structures or relative sizes of bond pads
    • H10W72/923—Bond pads having multiple stacked layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/951—Materials of bond pads
    • H10W72/952—Materials of bond pads comprising metals or metalloids, e.g. PbSn, Ag or Cu

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Dicing (AREA)
  • Semiconductor Integrated Circuits (AREA)
JP2007300790A 2007-11-20 2007-11-20 半導体装置及びその製造方法 Expired - Fee Related JP5139039B2 (ja)

Priority Applications (6)

Application Number Priority Date Filing Date Title
JP2007300790A JP5139039B2 (ja) 2007-11-20 2007-11-20 半導体装置及びその製造方法
US12/273,901 US7906833B2 (en) 2007-11-20 2008-11-19 Semiconductor device and manufacturing method thereof
KR1020080114951A KR20090052282A (ko) 2007-11-20 2008-11-19 반도체 장치 및 그 제조 방법
CNA2008101809569A CN101441992A (zh) 2007-11-20 2008-11-20 半导体器件及其制造方法
TW097144823A TW200931595A (en) 2007-11-20 2008-11-20 Semiconductor device and manufacturing method thereof
EP08169571A EP2065928A3 (en) 2007-11-20 2008-11-20 Semiconductor device and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2007300790A JP5139039B2 (ja) 2007-11-20 2007-11-20 半導体装置及びその製造方法

Publications (3)

Publication Number Publication Date
JP2009129982A JP2009129982A (ja) 2009-06-11
JP2009129982A5 JP2009129982A5 (https=) 2010-11-11
JP5139039B2 true JP5139039B2 (ja) 2013-02-06

Family

ID=40298658

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007300790A Expired - Fee Related JP5139039B2 (ja) 2007-11-20 2007-11-20 半導体装置及びその製造方法

Country Status (6)

Country Link
US (1) US7906833B2 (https=)
EP (1) EP2065928A3 (https=)
JP (1) JP5139039B2 (https=)
KR (1) KR20090052282A (https=)
CN (1) CN101441992A (https=)
TW (1) TW200931595A (https=)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4121542B1 (ja) * 2007-06-18 2008-07-23 新光電気工業株式会社 電子装置の製造方法
JP2012134270A (ja) * 2010-12-21 2012-07-12 Shinko Electric Ind Co Ltd 半導体装置及びその製造方法
US20130183823A1 (en) * 2012-01-18 2013-07-18 Chipbond Technology Corporation Bumping process
JP2019054172A (ja) * 2017-09-15 2019-04-04 東芝メモリ株式会社 半導体装置
KR102543996B1 (ko) * 2019-09-20 2023-06-16 주식회사 네패스 반도체 패키지 및 이의 제조방법
CN112885793B (zh) * 2021-03-12 2025-03-14 苏州晶方半导体科技股份有限公司 芯片封装结构及其制造方法

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3129161B2 (ja) 1995-08-18 2001-01-29 松下電器産業株式会社 チップの実装装置および実装方法
US6707153B2 (en) * 2000-03-23 2004-03-16 Seiko Epson Corporation Semiconductor chip with plural resin layers on a surface thereof and method of manufacturing same
JP2002057252A (ja) * 2000-08-07 2002-02-22 Hitachi Ltd 半導体装置及びその製造方法
JP5070661B2 (ja) 2001-04-27 2012-11-14 パナソニック株式会社 半導体装置およびその製造方法
US6818475B2 (en) * 2001-10-22 2004-11-16 Wen-Kun Yang Wafer level package and the process of the same
JP3614828B2 (ja) 2002-04-05 2005-01-26 沖電気工業株式会社 チップサイズパッケージの製造方法
JP2004134709A (ja) * 2002-10-15 2004-04-30 Seiko Epson Corp 半導体装置及びその製造方法、回路基板並びに電子機器
JP2004193497A (ja) * 2002-12-13 2004-07-08 Nec Electronics Corp チップサイズパッケージおよびその製造方法
JP4322181B2 (ja) * 2004-07-29 2009-08-26 三洋電機株式会社 半導体装置の製造方法
JP3976043B2 (ja) * 2004-10-25 2007-09-12 セイコーエプソン株式会社 半導体装置及びその製造方法
KR100660868B1 (ko) * 2005-07-06 2006-12-26 삼성전자주식회사 칩의 배면이 몰딩된 반도체 패키지 및 그의 제조방법

Also Published As

Publication number Publication date
US7906833B2 (en) 2011-03-15
CN101441992A (zh) 2009-05-27
KR20090052282A (ko) 2009-05-25
JP2009129982A (ja) 2009-06-11
US20090127665A1 (en) 2009-05-21
EP2065928A3 (en) 2011-01-26
TW200931595A (en) 2009-07-16
EP2065928A2 (en) 2009-06-03

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