JP5107512B2 - 外部応力層を持つバイポーラ・トランジスタ - Google Patents
外部応力層を持つバイポーラ・トランジスタ Download PDFInfo
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- JP5107512B2 JP5107512B2 JP2005247839A JP2005247839A JP5107512B2 JP 5107512 B2 JP5107512 B2 JP 5107512B2 JP 2005247839 A JP2005247839 A JP 2005247839A JP 2005247839 A JP2005247839 A JP 2005247839A JP 5107512 B2 JP5107512 B2 JP 5107512B2
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- 230000006355 external stress Effects 0.000 title 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 38
- 229910052710 silicon Inorganic materials 0.000 claims description 24
- 239000010703 silicon Substances 0.000 claims description 24
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims description 12
- HMDDXIMCDZRSNE-UHFFFAOYSA-N [C].[Si] Chemical compound [C].[Si] HMDDXIMCDZRSNE-UHFFFAOYSA-N 0.000 claims description 8
- 239000000758 substrate Substances 0.000 claims description 6
- 230000037230 mobility Effects 0.000 description 36
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 20
- 230000007935 neutral effect Effects 0.000 description 17
- 238000000034 method Methods 0.000 description 15
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 15
- 229920005591 polysilicon Polymers 0.000 description 15
- 238000004519 manufacturing process Methods 0.000 description 14
- 239000000463 material Substances 0.000 description 14
- 150000004767 nitrides Chemical class 0.000 description 13
- 239000010409 thin film Substances 0.000 description 12
- 239000004065 semiconductor Substances 0.000 description 11
- 125000006850 spacer group Chemical group 0.000 description 9
- 238000002955 isolation Methods 0.000 description 8
- 239000000969 carrier Substances 0.000 description 7
- 238000000151 deposition Methods 0.000 description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 239000012535 impurity Substances 0.000 description 6
- 230000008569 process Effects 0.000 description 6
- 229910021332 silicide Inorganic materials 0.000 description 6
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 6
- 239000010408 film Substances 0.000 description 5
- 238000007373 indentation Methods 0.000 description 5
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 4
- 230000008901 benefit Effects 0.000 description 4
- 229910052796 boron Inorganic materials 0.000 description 4
- 230000008021 deposition Effects 0.000 description 4
- 239000002019 doping agent Substances 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 238000001020 plasma etching Methods 0.000 description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 3
- 239000002800 charge carrier Substances 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 230000006872 improvement Effects 0.000 description 3
- 239000012212 insulator Substances 0.000 description 3
- 238000001459 lithography Methods 0.000 description 3
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- 239000011574 phosphorus Substances 0.000 description 3
- 235000012239 silicon dioxide Nutrition 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- 238000004088 simulation Methods 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 2
- 230000006835 compression Effects 0.000 description 2
- 238000007906 compression Methods 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 238000001451 molecular beam epitaxy Methods 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 238000001289 rapid thermal chemical vapour deposition Methods 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 229910000676 Si alloy Inorganic materials 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 229910052787 antimony Inorganic materials 0.000 description 1
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 238000000429 assembly Methods 0.000 description 1
- 230000000712 assembly Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000012552 review Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66242—Heterojunction transistors [HBT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/73—Bipolar junction transistors
- H01L29/737—Hetero-junction transistors
- H01L29/7371—Vertical transistors
- H01L29/7378—Vertical transistors comprising lattice mismatched active layers, e.g. SiGe strained layer transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8248—Combination of bipolar and field-effect technology
- H01L21/8249—Bipolar and MOS technology
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/24—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22
- H01L29/242—AIBVI or AIBVII compounds, e.g. Cu2O, Cu I
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Bipolar Transistors (AREA)
Description
説明を簡単にするために、図のいくつかにおける特定の要素は、省略するか、または縮尺に合わせずに図示されるであろう。説明を簡単にするために、断面図は、「スライス」または「拡大」断面図の形式とし、「真の」断面図では見えるはずの特定の背景線を省略する場合がある。
多くの場合、同様の要素は、図面の中の各図において同様の番号で参照され、この場合には、典型的には、最後の2つの有効数字は同じであり、最上位の数字は図面の番号である。
ベース薄膜について、厚さ(図の垂直方向)は、10から50nm
コレクタ領域について、幅(図のSTI間の水平方向)は、100から200nm
スペーサについて、幅/厚さ(図の水平方向)は、10から50nm
応力層について、厚さ(図の垂直方向)は、10から50nm(後述されるように、応力層は一部分のみが埋め込まれるため、下層のベース薄膜と同じ厚さとするか、またはそれよりも厚くすることもできる)
エミッタ構造体について、全体の高さは、100から200nm
エミッタの幅は、100から200nm
応力層を導入したシミュレーション結果は、図18から図20に示される。
図18は、対象となるデバイス領域の半分の断面を示す。両軸は、距離をミクロンで示す。シミュレーション効率のために、デバイスの半分のみが示される。応力層は、ベース薄膜の上にある。横方向応力を表す等応力線が構造体内に示される。エミッタ層の垂直部分の下では、横方向応力は、ベース薄膜とエミッタ薄膜との間の界面近くに大きな応力を伴う圧縮性のものである。応力層の下では、ベース層には、同様に表面近くで大きさが最大になる張力がかかっている。
202 コレクタ領域
204 ベース薄膜
220 本発明に係るBJT
400 本発明に係るBJT
402 基板
404 エピタキシャル層
406a、406b、406c シャロー・トレンチ
408 シャロー・トレンチ分離酸化物
410、412 メサ
416 エッチング停止層
420、420´、421、421´ シリコン層
420´´ 外部ベース領域
422、422´ 酸化物層
424、424´ 窒化物層
426 エミッタ・マンドレル
428、428´ 酸化物層
430 エミッタ構造体
432 エミッタ開口
434 側壁スペーサ
436 ハード・マスク
438 窒化物側壁スペーサ
440a、440b、440c シリサイド層
450、451 応力層
450´ 外部ベース領域
452 酸化物誘電体
454b、454c、454d コンタクト
460 ポリシリコン層
Claims (4)
- コレクタ領域と、
前記コレクタ領域の上に配置されたベース層と、
前記ベース層の上に形成されたエミッタ構造体と、
前記エミッタ構造体に隣接して配置され、少なくとも一部が前記ベース層内に埋め込まれた応力層とを備え、
前記応力層が、前記ベース層内に形成された内部ベースの上に配置され、
前記内部ベースはシリコンからなり、
npnバイポーラ・デバイスの場合には、前記応力層は、シリコン・ゲルマニウムからなり、前記内部ベースより大きい格子定数を有し、
pnpバイポーラ・デバイスの場合には、前記応力層は、シリコン・カーボンからなり、前記内部ベースより小さい格子定数を有する、バイポーラ・デバイス。 - コレクタ領域と、
前記コレクタ領域の上に配置されたベース層と、
前記ベース層の上に形成されたエミッタ構造体と、
前記エミッタ構造体に隣接して配置され、少なくとも一部が前記ベース層内に埋め込まれた応力層とを備え、
前記応力層が、前記ベース層内に形成された内部ベースの上に配置され、
前記内部ベースはシリコンからなり、
npnバイポーラ・デバイスの場合には、前記応力層が、シリコン・ゲルマニウムからなり、前記内部ベース内に垂直方向の引っ張り歪みを生じさせて該内部ベースにおける電子移動度を増加させ、該内部ベース内に水平方向の圧縮歪みを生じさせて該内部ベースにおける正孔移動度を増加させ、
pnpバイポーラ・デバイスの場合には、前記応力層が、シリコン・カーボンからなり、前記内部ベース内に垂直方向の圧縮歪みを生じさせて該内部ベースにおける正孔移動度を増加させ、該内部ベース内に水平方向の引っ張り歪みを生じさせて該内部ベースにおける電子移動度を増加させる、バイポーラ・デバイス。 - コレクタ領域と、
前記コレクタ領域の上に配置されたベース層と、
前記ベース層の上に形成されたエミッタ構造体と、
前記エミッタ構造体に隣接して配置され、少なくとも一部が前記ベース層内に埋め込まれた応力層とを備え、
前記応力層が、前記ベース層内に形成された内部ベースの上に配置され、
前記内部ベースはシリコン・ゲルマニウムからなり、
前記応力層は、シリコンまたはシリコン・カーボンからなり、前記内部ベースより小さい格子定数を有する、pnpバイポーラ・デバイス。 - コレクタ領域と、
前記コレクタ領域の上に配置されたベース層と、
前記ベース層の上に形成されたエミッタ構造体と、
前記エミッタ構造体に隣接して配置され、少なくとも一部が前記ベース層内に埋め込まれた応力層とを備え、
前記応力層が、前記ベース層内に形成された内部ベースの上に配置され、
前記内部ベースはシリコン・ゲルマニウムからなり、
前記応力層が、シリコンまたはシリコン・カーボンからなり、前記内部ベース内に垂直方向の圧縮歪みを生じさせて該内部ベースにおける正孔移動度を増加させ、該内部ベース内に水平方向の引っ張り歪みを生じさせて該内部ベースにおける電子移動度を増加させる、pnpバイポーラ・デバイス。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/931,660 US7102205B2 (en) | 2004-09-01 | 2004-09-01 | Bipolar transistor with extrinsic stress layer |
US10/931660 | 2004-09-01 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2006074040A JP2006074040A (ja) | 2006-03-16 |
JP5107512B2 true JP5107512B2 (ja) | 2012-12-26 |
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Application Number | Title | Priority Date | Filing Date |
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JP2005247839A Expired - Fee Related JP5107512B2 (ja) | 2004-09-01 | 2005-08-29 | 外部応力層を持つバイポーラ・トランジスタ |
Country Status (4)
Country | Link |
---|---|
US (1) | US7102205B2 (ja) |
JP (1) | JP5107512B2 (ja) |
CN (1) | CN100407442C (ja) |
TW (1) | TW200623392A (ja) |
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JPH0766981B2 (ja) * | 1987-03-26 | 1995-07-19 | 日本電気株式会社 | 赤外線センサ |
JPH04179235A (ja) * | 1990-11-14 | 1992-06-25 | Toshiba Corp | ヘテロ接合バイポーラトランジスタ |
JP3085553B2 (ja) * | 1991-11-20 | 2000-09-11 | 日本電信電話株式会社 | 半導体装置の表層構造 |
JPH06275814A (ja) * | 1993-03-17 | 1994-09-30 | Sankyo Seiki Mfg Co Ltd | 半導体材料 |
JP3326427B2 (ja) * | 1996-09-17 | 2002-09-24 | 松下電器産業株式会社 | 半導体装置及びその製造方法 |
FR2804247B1 (fr) * | 2000-01-21 | 2002-04-12 | St Microelectronics Sa | Procede de realisation d'un transistor bipolaire a emetteur et base extrinseque auto-alignes |
US20030199153A1 (en) * | 2000-01-27 | 2003-10-23 | Kovacic Stephen J. | Method of producing SI-GE base semiconductor devices |
US6852602B2 (en) * | 2001-01-31 | 2005-02-08 | Matsushita Electric Industrial Co., Ltd. | Semiconductor crystal film and method for preparation thereof |
JP4569026B2 (ja) * | 2001-03-30 | 2010-10-27 | 信越半導体株式会社 | 半導体基板及びその製造方法 |
US7060582B2 (en) * | 2001-06-05 | 2006-06-13 | Sony Corporation | Adjusting the germanium concentration of a semiconductor layer for equal thermal expansion for a hetero-junction bipolar transistor device |
JP2003151987A (ja) * | 2001-11-19 | 2003-05-23 | Mitsubishi Heavy Ind Ltd | 半導体基板、及び、半導体基板の製造方法 |
JP4182177B2 (ja) * | 2002-10-30 | 2008-11-19 | 富士通マイクロエレクトロニクス株式会社 | 半導体装置の製造方法 |
US7101742B2 (en) * | 2003-08-12 | 2006-09-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Strained channel complementary field-effect transistors and methods of manufacture |
US7005359B2 (en) * | 2003-11-17 | 2006-02-28 | Intel Corporation | Bipolar junction transistor with improved extrinsic base region and method of fabrication |
-
2004
- 2004-09-01 US US10/931,660 patent/US7102205B2/en active Active
-
2005
- 2005-08-29 JP JP2005247839A patent/JP5107512B2/ja not_active Expired - Fee Related
- 2005-08-30 CN CN2005100978284A patent/CN100407442C/zh active Active
- 2005-08-31 TW TW094129854A patent/TW200623392A/zh unknown
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CN100407442C (zh) | 2008-07-30 |
CN1763968A (zh) | 2006-04-26 |
TW200623392A (en) | 2006-07-01 |
US20060043529A1 (en) | 2006-03-02 |
US7102205B2 (en) | 2006-09-05 |
JP2006074040A (ja) | 2006-03-16 |
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