JP5106424B2 - シリコンに対する誘電材料の選択エッチング方法及びシステム - Google Patents
シリコンに対する誘電材料の選択エッチング方法及びシステム Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Inorganic Chemistry (AREA)
- General Chemical & Material Sciences (AREA)
- Plasma & Fusion (AREA)
- Drying Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
Claims (16)
- スペーサエッチングプロセスにおいて凹部を減少させる方法であって、
当該方法は:
ドライプラズマエッチングシステム内の基板ホルダ上に、ポリシリコンの特徴部位と単結晶シリコン基板表面の上に存在するスペーサ誘電体層を有するシリコン基板を設ける基板設置手順;
前記スペーサ誘電体層と前記単結晶シリコン基板表面とのエッチング選択性が5:1以上の比を有するようなプロセス条件を選択するプロセス条件選択手順;
を有し、さらに
前記プロセス条件を前記ドライプラズマエッチングシステムに適用するプロセス条件適用手順;及び
前記基板を前記プロセス条件に曝露することで、前記単結晶シリコン基板表面内に形成される凹部を最小限に抑制しながら、前記スペーサ誘電体層を前記単結晶シリコン基板表面までエッチングする、基板曝露手順;
を有し、
前記プロセス条件選択手順は:
前記ドライプラズマエッチングシステム内の圧力を設定する圧力設定手順;
第1流速の希ガス、第2流速のCHF3、及び第3流速のCH2F2 からなるプロセスガスを導入するプロセスガス導入手順;及び
前記ドライプラズマエッチングシステム内の電極と結合するように出力を設定することで前記プロセスガスからプラズマを生成するプラズマ生成手順;
を有する、
方法。 - 前記基板設置手順が、ポリシリコンの特徴部位の上に二酸化シリコン(SiO2)を有するシリコン基板を設ける手順を有する、請求項1に記載の方法。
- 前記プロセス条件選択手順が、前記スペーサ誘電体層と前記シリコン基板との間でのエッチング選択性を7:1以上に到達するようにプロセス条件を選択する手順を有する、請求項2に記載の方法。
- 前記圧力設定手順が、5mTorrから1000mTorrの範囲で圧力を設定する手順を有する、請求項2に記載の方法。
- 前記圧力設定手順が、40mTorrから100mTorrの範囲で圧力を設定する手順を有する、請求項2に記載の方法。
- 前記第1流速を設定する手順が、0sccmから500sccmの範囲でアルゴンの流速を設定する手順を有する、請求項2に記載の方法。
- 前記第2流速を設定する手順が、1sccmから1000sccmの範囲でCHF3の流速を設定する手順を有する、請求項2に記載の方法。
- 前記第2流速を設定する手順が、20sccmから50sccmの範囲でCHF3の流速を設定する手順を有する、請求項2に記載の方法。
- 前記第3流速を設定する手順が、1sccmから1000sccmの範囲でCH2F2の流速を設定する手順を有する、請求項2に記載の方法。
- 前記第3流速を設定する手順が、2sccmから6sccmの範囲でCH2F2の流速を設定する手順を有する、請求項2に記載の方法。
- 前記出力を設定する手順が、前記基板ホルダ上の前記基板に対向する上部電極と結合する高周波(RF)出力を第1周波数に設定する手順を有する、請求項2に記載の方法。
- 前記上部電極への前記RF出力を設定する手順が、0Wから2000Wまでの範囲で出力を設定する手順を有する、請求項11に記載の方法。
- 前記上部電極への前記RF出力を設定する手順が、100Wから1000Wまでの範囲で出力を設定する手順を有する、請求項11に記載の方法。
- 前記出力を設定する手順が、前記基板ホルダ上の前記基板に対向する上部電極と結合する第1高周波(RF)出力を第1周波数に設定する手順、及び、前記基板ホルダと結合する第2高周波(RF)出力を第2周波数に設定する手順を有する、請求項2に記載の方法。
- 前記第1RF出力を設定する手順が、100Wから1000Wまでの範囲で出力を設定する手順を有し、かつ
前記第2RF出力を設定する手順が、50Wから950Wまでの範囲で出力を設定する手順を有する、
請求項14に記載の方法。 - コンピュータシステム上で実行するためのプログラム命令を有するコンピュータによる読み取り可能な媒体であって:
ドライプラズマエッチングシステム内の基板ホルダ上に、ポリシリコンの特徴部位と単結晶シリコン基板表面の上に存在するスペーサ誘電体層を有するシリコン基板を設ける基板設置手順;
前記スペーサ誘電体層と前記単結晶シリコン基板表面とのエッチング選択性が5:1以上の比を有するようなプロセス条件を選択するプロセス条件選択手順;さらに
前記プロセス条件を前記ドライプラズマエッチングシステムに適用するプロセス条件適用手順;及び
前記基板を前記プロセス条件に曝露することで、前記単結晶シリコン基板表面内に形成される凹部を最小限に抑制しながら、前記スペーサ誘電体層を前記単結晶シリコン基板表面までエッチングする、基板曝露手順;
を、前記コンピュータシステムによって実行されるときに、前記コンピュータに実行させ、
前記プロセス条件選択手順は:
前記ドライプラズマエッチングシステム内の圧力を設定する圧力設定手順;
第1流速の希ガス、第2流速のCHF3、及び第3流速のCH2F2 からなるプロセスガスを導入するプロセスガス導入手順;及び
前記ドライプラズマエッチングシステム内の電極と結合するように出力を設定することで前記プロセスガスからプラズマを生成するプラズマ生成手順;
を有する、
コンピュータによる読み取り可能な媒体。
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US11/350,765 | 2006-02-10 | ||
US11/350,765 US7393788B2 (en) | 2006-02-10 | 2006-02-10 | Method and system for selectively etching a dielectric material relative to silicon |
PCT/US2006/046967 WO2007094853A2 (en) | 2006-02-10 | 2006-12-12 | Method and system for selectively etching a dielectric material relative to silicon |
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JP (2) | JP5106424B2 (ja) |
KR (2) | KR101308241B1 (ja) |
CN (1) | CN101366100B (ja) |
TW (1) | TWI331776B (ja) |
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JP5103006B2 (ja) | 2006-11-16 | 2012-12-19 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
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US8501630B2 (en) | 2010-09-28 | 2013-08-06 | Tokyo Electron Limited | Selective etch process for silicon nitride |
TWI476832B (zh) * | 2011-09-28 | 2015-03-11 | Tokyo Electron Ltd | 蝕刻方法及裝置 |
US8765613B2 (en) * | 2011-10-26 | 2014-07-01 | International Business Machines Corporation | High selectivity nitride etch process |
JP5932599B2 (ja) * | 2011-10-31 | 2016-06-08 | 株式会社日立ハイテクノロジーズ | プラズマエッチング方法 |
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US6777299B1 (en) * | 2003-07-07 | 2004-08-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for removal of a spacer |
JP2005039015A (ja) * | 2003-07-18 | 2005-02-10 | Hitachi High-Technologies Corp | プラズマ処理方法および装置 |
CN1246498C (zh) * | 2003-09-25 | 2006-03-22 | 北京大学 | 基于电感耦合等离子体刻蚀多晶硅及制备超细线条的方法 |
US7008878B2 (en) * | 2003-12-17 | 2006-03-07 | Taiwan Semiconductor Manufacturing Co., Ltd. | Plasma treatment and etching process for ultra-thin dielectric films |
JP4550507B2 (ja) * | 2004-07-26 | 2010-09-22 | 株式会社日立ハイテクノロジーズ | プラズマ処理装置 |
US20070032081A1 (en) * | 2005-08-08 | 2007-02-08 | Jeremy Chang | Edge ring assembly with dielectric spacer ring |
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TW200737345A (en) | 2007-10-01 |
KR20130040261A (ko) | 2013-04-23 |
JP2009526398A (ja) | 2009-07-16 |
KR101274822B1 (ko) | 2013-06-13 |
US20070190792A1 (en) | 2007-08-16 |
CN101366100B (zh) | 2010-12-08 |
US7393788B2 (en) | 2008-07-01 |
JP5468113B2 (ja) | 2014-04-09 |
CN101366100A (zh) | 2009-02-11 |
TWI331776B (en) | 2010-10-11 |
JP2012256907A (ja) | 2012-12-27 |
KR20080104299A (ko) | 2008-12-02 |
WO2007094853A3 (en) | 2007-12-21 |
KR101308241B1 (ko) | 2013-09-30 |
WO2007094853A2 (en) | 2007-08-23 |
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