JP5106028B2 - 半導体記憶装置及びその製造方法 - Google Patents
半導体記憶装置及びその製造方法 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims description 37
- 238000004519 manufacturing process Methods 0.000 title claims description 24
- 230000015654 memory Effects 0.000 claims description 63
- 239000000758 substrate Substances 0.000 claims description 29
- 239000002184 metal Substances 0.000 claims description 13
- 229910052751 metal Inorganic materials 0.000 claims description 13
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 10
- 238000005530 etching Methods 0.000 claims description 9
- 238000000034 method Methods 0.000 claims description 7
- 229910021332 silicide Inorganic materials 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 5
- 239000012212 insulator Substances 0.000 claims 2
- 238000009413 insulation Methods 0.000 claims 1
- PXHVJJICTQNCMI-UHFFFAOYSA-N nickel Substances [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 17
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 13
- 229920005591 polysilicon Polymers 0.000 description 13
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 11
- 229910052710 silicon Inorganic materials 0.000 description 11
- 239000010703 silicon Substances 0.000 description 11
- 238000009792 diffusion process Methods 0.000 description 10
- 239000010410 layer Substances 0.000 description 10
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 8
- 238000002955 isolation Methods 0.000 description 8
- 229910052698 phosphorus Inorganic materials 0.000 description 8
- 239000011574 phosphorus Substances 0.000 description 8
- 229910052814 silicon oxide Inorganic materials 0.000 description 7
- 239000012535 impurity Substances 0.000 description 6
- 230000002093 peripheral effect Effects 0.000 description 5
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- 229910004298 SiO 2 Inorganic materials 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 238000001039 wet etching Methods 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 230000006870 function Effects 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 238000004380 ashing Methods 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 229910052681 coesite Inorganic materials 0.000 description 2
- 229910052906 cristobalite Inorganic materials 0.000 description 2
- PEUPIGGLJVUNEU-UHFFFAOYSA-N nickel silicon Chemical compound [Si].[Ni] PEUPIGGLJVUNEU-UHFFFAOYSA-N 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- WNUPENMBHHEARK-UHFFFAOYSA-N silicon tungsten Chemical compound [Si].[W] WNUPENMBHHEARK-UHFFFAOYSA-N 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 229910052682 stishovite Inorganic materials 0.000 description 2
- 239000002344 surface layer Substances 0.000 description 2
- 229910052905 tridymite Inorganic materials 0.000 description 2
- 238000007792 addition Methods 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 229910021334 nickel silicide Inorganic materials 0.000 description 1
- RUFLMLWJRZAWLJ-UHFFFAOYSA-N nickel silicide Chemical compound [Ni]=[Si]=[Ni] RUFLMLWJRZAWLJ-UHFFFAOYSA-N 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
- H01L21/28052—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/28008—Making conductor-insulator-semiconductor electrodes
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
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- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Description
以下、図面を参照しながら、本発明の実施形態に係る半導体記憶装置について詳細に説明する。
次に、上記したNANDフラッシュメモリの製造方法の実施の形態について図面を参照しながら詳細に説明する。図3から図14は、上記した実施の形態に係るNANDフラッシュメモリの製造工程を説明したものである。
以上、発明の実施の形態を説明したが、本発明はこれらに限定されるものではなく、発明の趣旨を逸脱しない範囲内において、種々の変更、追加等が可能である。例えば、上記した実施の形態ではNANDフラッシュメモリについて説明したが、NORフラッシュメモリ等他のスタックゲート型不揮発性メモリについても同様に適用可能である。
Claims (5)
- 半導体基板と、
この半導体基板上に形成されたゲート絶縁膜と、
前記半導体基板上に前記ゲート絶縁膜を介して形成された下側ゲートと、
この下側ゲート上に形成されたゲート間絶縁膜と、
前記下側ゲート上に前記ゲート間絶縁膜を介して形成され、シリサイド化された上側ゲートと、
を有するスタックゲート構造の複数のトランジスタを備えて構成され、
一部の前記トランジスタは、前記ゲート間絶縁膜に前記下側ゲートと前記上側ゲートとを接続する開口部を有し、前記上側ゲートの上に、前記開口部を覆う、前記上側ゲートよりも小さく前記開口部よりも大きい絶縁体からなるブロック膜を有する
ことを特徴とする半導体記憶装置。 - 半導体基板、この半導体基板上に形成されたゲート絶縁膜、前記半導体基板上に前記ゲート絶縁膜を介して形成された浮遊ゲートとなる下側ゲート、この下側ゲート上に形成されたゲート間絶縁膜及び前記下側ゲート上に前記ゲート間絶縁膜を介して形成されシリサイド化された制御ゲートとなる上側ゲートを有する複数のメモリセルと、
前記メモリセルと同時に形成された前記半導体基板、ゲート絶縁膜、下側ゲート、ゲート間絶縁膜及び上側ゲートを備え、前記ゲート間絶縁膜に前記下側ゲートと前記上側ゲートとを接続する開口部を有し、前記上側ゲートの上に、前記開口部を覆う、前記上側ゲートよりも小さく前記開口部よりも大きい絶縁体からなるブロック膜を有するトランジスタと
を備えたことを特徴とする半導体記憶装置。 - 前記シリサイド化された上側ゲート中の金属原子が、前記開口部を通じて前記ゲート絶縁膜までは拡散していないことを特徴とする請求項1又は2記載の半導体記憶装置。
- 半導体基板上にゲート絶縁膜を形成する工程と、
前記ゲート絶縁膜の上に第1導電性膜を形成する工程と、
前記第1導電性膜の上にゲート間絶縁膜を形成する工程と、
エッチングにより、前記ゲート間絶縁膜のトランジスタを形成するべき領域の一部に選択的に開口部を形成する工程と、
前記ゲート間絶縁膜の上に第2導電性膜を形成する工程と、
前記第2導電性膜の上に第1の絶縁膜を形成する工程と、
前記第1の絶縁膜の一部を選択的に除去して前記開口部を覆う、前記開口部よりも大きなブロック膜を形成する工程と、
前記ブロック膜の側面に第2の絶縁膜から成るサイドウォールを形成すると共にメモリセルの制御ゲートを形成するべき領域に前記第2の絶縁膜から成るゲートパターンを形成する工程と、
前記ブロック膜、サイドウォール及びゲートパターンをエッチングマスクとして前記第2導電性膜、ゲート間絶縁膜及び第1の導電性膜を、エッチングにより選択的に除去して前記メモリセル及びトランジスタのゲートを形成する工程と、
前記形成されたゲートの周囲に第3の絶縁膜を埋め込む工程と、
前記第3の絶縁膜を埋め込んだ後前記第2の絶縁膜を除去する工程と、
前記第2の絶縁膜を除去した部分にシリサイド金属を堆積させて前記第2の導電性膜をシリサイド化する工程と
を有することを特徴とする半導体記憶装置の製造方法。 - 前記ブロック膜を形成する工程と同時に前記メモリセルのゲート間位置に前記第1の絶縁膜から成るラインパターンを形成する工程を備え、
前記サイドウォール及びゲートパターンを形成する工程は、前記ブロック膜及びラインパターンの上に前記第2の絶縁膜を堆積した後、この堆積された第2の絶縁膜をエッチバックし、更に前記メモリセルを形成するべき領域で、前記第1絶縁膜を選択的に除去することにより、前記第1絶縁膜のラインパターンのパターンピッチよりも小さいパターンピッチの前記ゲートパターンを形成する工程である
ことを特徴とする請求項4記載の半導体記憶装置の製造方法。
Priority Applications (4)
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JP2007260039A JP5106028B2 (ja) | 2007-10-03 | 2007-10-03 | 半導体記憶装置及びその製造方法 |
KR1020080097010A KR101001777B1 (ko) | 2007-10-03 | 2008-10-02 | 반도체 기억 장치 및 그 제조 방법 |
US12/244,523 US20090096007A1 (en) | 2007-10-03 | 2008-10-02 | Semiconductor memory device and method of manufacturing the same |
US12/929,125 US8460997B2 (en) | 2007-10-03 | 2011-01-03 | Semiconductor memory device and method of manufacturing the same |
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JP2007260039A JP5106028B2 (ja) | 2007-10-03 | 2007-10-03 | 半導体記憶装置及びその製造方法 |
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JP2009094091A JP2009094091A (ja) | 2009-04-30 |
JP5106028B2 true JP5106028B2 (ja) | 2012-12-26 |
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US (2) | US20090096007A1 (ja) |
JP (1) | JP5106028B2 (ja) |
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JP4703669B2 (ja) | 2008-02-18 | 2011-06-15 | 株式会社東芝 | 半導体記憶装置及びその製造方法 |
JP2010080498A (ja) * | 2008-09-24 | 2010-04-08 | Toshiba Corp | 不揮発性半導体記憶装置およびその製造方法 |
KR20120019208A (ko) * | 2010-08-25 | 2012-03-06 | 삼성전자주식회사 | 비휘발성 메모리 장치의 제조 방법 |
JP2012160567A (ja) * | 2011-01-31 | 2012-08-23 | Toshiba Corp | 不揮発性半導体記憶装置及びその製造方法 |
JP5606388B2 (ja) * | 2011-05-13 | 2014-10-15 | 株式会社東芝 | パターン形成方法 |
JP2013105891A (ja) * | 2011-11-14 | 2013-05-30 | Toshiba Corp | 半導体装置およびその製造方法 |
US9698047B2 (en) * | 2015-06-17 | 2017-07-04 | United Microelectronics Corp. | Dummy gate technology to avoid shorting circuit |
TWI692078B (zh) * | 2019-03-29 | 2020-04-21 | 華邦電子股份有限公司 | 記憶體結構及其製造方法 |
US20230163029A1 (en) * | 2021-11-19 | 2023-05-25 | International Business Machines Corporation | Selective metal residue and liner cleanse for post-subtractive etch |
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JP2002176114A (ja) * | 2000-09-26 | 2002-06-21 | Toshiba Corp | 半導体装置及びその製造方法 |
JP4457688B2 (ja) | 2004-02-12 | 2010-04-28 | ソニー株式会社 | 半導体装置 |
US7390746B2 (en) * | 2005-03-15 | 2008-06-24 | Micron Technology, Inc. | Multiple deposition for integration of spacers in pitch multiplication process |
JP4921723B2 (ja) * | 2005-04-18 | 2012-04-25 | 株式会社東芝 | 半導体装置の製造方法 |
JP4799196B2 (ja) * | 2006-01-31 | 2011-10-26 | 株式会社東芝 | 不揮発性半導体記憶装置 |
US7553729B2 (en) * | 2006-05-26 | 2009-06-30 | Hynix Semiconductor Inc. | Method of manufacturing non-volatile memory device |
KR100760634B1 (ko) | 2006-10-02 | 2007-09-20 | 삼성전자주식회사 | 낸드형 비휘발성 기억 소자 및 그 형성 방법 |
JP2008192905A (ja) * | 2007-02-06 | 2008-08-21 | Toshiba Corp | スタックゲート型不揮発性半導体メモリ、及びその製造方法 |
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2007
- 2007-10-03 JP JP2007260039A patent/JP5106028B2/ja not_active Expired - Fee Related
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2008
- 2008-10-02 US US12/244,523 patent/US20090096007A1/en not_active Abandoned
- 2008-10-02 KR KR1020080097010A patent/KR101001777B1/ko not_active IP Right Cessation
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KR20090034755A (ko) | 2009-04-08 |
JP2009094091A (ja) | 2009-04-30 |
US20090096007A1 (en) | 2009-04-16 |
US20110097888A1 (en) | 2011-04-28 |
US8460997B2 (en) | 2013-06-11 |
KR101001777B1 (ko) | 2010-12-15 |
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