JP5101263B2 - 半導体ヘテロ構造 - Google Patents
半導体ヘテロ構造 Download PDFInfo
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- JP5101263B2 JP5101263B2 JP2007325121A JP2007325121A JP5101263B2 JP 5101263 B2 JP5101263 B2 JP 5101263B2 JP 2007325121 A JP2007325121 A JP 2007325121A JP 2007325121 A JP2007325121 A JP 2007325121A JP 5101263 B2 JP5101263 B2 JP 5101263B2
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- 239000004065 semiconductor Substances 0.000 title claims description 38
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 59
- 229910052710 silicon Inorganic materials 0.000 claims description 51
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 47
- 239000010703 silicon Substances 0.000 claims description 47
- 239000000203 mixture Substances 0.000 claims description 42
- 229910052732 germanium Inorganic materials 0.000 claims description 37
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 33
- 239000000758 substrate Substances 0.000 claims description 33
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 6
- 238000005498 polishing Methods 0.000 claims description 5
- 239000001257 hydrogen Substances 0.000 claims description 4
- 229910052739 hydrogen Inorganic materials 0.000 claims description 4
- 125000004435 hydrogen atom Chemical class [H]* 0.000 claims description 3
- 239000000126 substance Substances 0.000 claims description 3
- 238000003475 lamination Methods 0.000 claims 2
- 235000012431 wafers Nutrition 0.000 description 37
- 238000000034 method Methods 0.000 description 15
- 239000000463 material Substances 0.000 description 14
- 239000002243 precursor Substances 0.000 description 7
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 6
- 125000004429 atom Chemical group 0.000 description 5
- 230000007547 defect Effects 0.000 description 5
- 239000007789 gas Substances 0.000 description 5
- 238000002513 implantation Methods 0.000 description 5
- 238000000926 separation method Methods 0.000 description 5
- 229910045601 alloy Inorganic materials 0.000 description 4
- 239000000956 alloy Substances 0.000 description 4
- 230000008901 benefit Effects 0.000 description 4
- 150000001875 compounds Chemical class 0.000 description 4
- 239000013078 crystal Substances 0.000 description 4
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 229910003465 moissanite Inorganic materials 0.000 description 3
- 229910052594 sapphire Inorganic materials 0.000 description 3
- 239000010980 sapphire Substances 0.000 description 3
- 229910010271 silicon carbide Inorganic materials 0.000 description 3
- 229910003811 SiGeC Inorganic materials 0.000 description 2
- 238000000354 decomposition reaction Methods 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000005304 joining Methods 0.000 description 2
- 230000006911 nucleation Effects 0.000 description 2
- 238000010899 nucleation Methods 0.000 description 2
- 230000003746 surface roughness Effects 0.000 description 2
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 239000012159 carrier gas Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- -1 hydrogen ions Chemical class 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000001451 molecular beam epitaxy Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 230000008929 regeneration Effects 0.000 description 1
- 238000011069 regeneration method Methods 0.000 description 1
- 238000004381 surface treatment Methods 0.000 description 1
- 230000003313 weakening effect Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/15—Structures with periodic or quasi periodic potential variation, e.g. multiple quantum wells, superlattices
- H01L29/151—Compositional structures
- H01L29/152—Compositional structures with quantum effects only in vertical direction, i.e. layered structures with quantum effects solely resulting from vertical potential variation
- H01L29/155—Comprising only semiconductor materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
- H01L21/02441—Group 14 semiconducting materials
- H01L21/0245—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02494—Structure
- H01L21/02496—Layer structure
- H01L21/02505—Layer structure consisting of more than two layers
- H01L21/02507—Alternating layers, e.g. superlattice
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02494—Structure
- H01L21/02496—Layer structure
- H01L21/0251—Graded layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys
- H01L29/165—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys in different semiconductor regions, e.g. heterojunctions
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Recrystallisation Techniques (AREA)
Description
Claims (3)
- 半導体ヘテロ構造であって
第1の面内格子定数(a1)をもつ支持基板(1)であって、少なくとも最上部がシリコンである支持基板と、
該支持基板(1)上にエピタキシャルに形成されていて、格子緩和状態において第2の面内格子定数(a2)を上部にもつ、ゲルマニウム組成がゼロ%から20%まで増大していく組成傾斜したSiGe緩衝層であって、前記SiGe緩衝層の表面は、化学機械研磨が行われ、弗化水素酸に浸漬し水素H2中3分、800℃から850℃の範囲の温度で加熱され、表面の組成がSi0.8Ge0.2である前記組成傾斜したSiGe緩衝層と、
該組成傾斜したSiGe緩衝層上に形成され、ゲルマニウム組成が0%と前記組成傾斜したSiGe緩衝層の最大ゲルマニウム組成未満であるパーセンテージとの中間にあるゲルマニウム組成を持つ歪SiGe平坦化層(5,5’,5’’,5’’’,5’’’’)と、歪シリコン層(4,4’,4’’,4’’’,6)との交互積層と、
を備え、
前記交互積層は、臨界膜厚未満の厚さの前記歪シリコン層が形成され、該歪SiGe平坦化層が前記第1および第2の面内格子定数(a1,a2)の中間の第3の面内格子定数(a3)を格子緩和状態において有し、かつ、11%から19.5%の範囲のゲルマニウムの組成をもつ臨界膜厚未満の厚さの該歪SiGe平坦化層が形成され、その後、50Åから250Åの範囲の厚さの歪シリコン層と200Åから600Åの範囲の厚さの歪SiGe平坦化層が交互に3回積層され、最上部に、50Åから250Åの範囲の厚さの歪シリコン層が形成されたことを特徴とする半導体ヘテロ構造。 - 半導体ヘテロ構造であって
第1の面内格子定数(a1)をもつ支持基板(1)であって、少なくとも最上部がシリコンである支持基板と、
該支持基板(1)上にエピタキシャルに形成されていて、格子緩和状態において第2の面内格子定数(a2)を上部にもつ、ゲルマニウム組成がゼロ%から40%まで増大していく組成傾斜したSiGe緩衝層であって、前記SiGe緩衝層の表面は、化学機械研磨が行われ、弗化水素酸に浸漬し水素H2中3分、800℃から850℃の範囲の温度で加熱され、表面の組成がSi0.6Ge0.4である前記組成傾斜したSiGe緩衝層と、
該組成傾斜したSiGe緩衝層上に形成され、ゲルマニウム組成が0%と前記組成傾斜したSiGe緩衝層の最大ゲルマニウム組成未満であるパーセンテージとの中間にあるゲルマニウム組成を持つ歪SiGe平坦化層(5,5’,5’’,5’’’,5’’’’)と、歪シリコン層(4,4’,4’’,4’’’,6)との交互積層と、
を備え、
前記交互積層は、臨界膜厚未満の厚さの前記歪シリコン層が形成され、前記第1および第2の面内格子定数(a1,a2)の中間の第3の面内格子定数(a3)を格子緩和状態において有し、かつ、35%から39.5%の範囲のゲルマニウムの組成をもつ臨界膜厚未満の厚さの該歪SiGe平坦化層が形成され、その後、50Åから250Åの範囲の厚さの歪シリコン層と200Åから600Åの範囲の厚さの歪SiGe平坦化層が交互に3回積層され、最上部に、50Åから250Åの範囲の厚さの歪シリコン層が形成されたことを特徴とする半導体ヘテロ構造。 - 前記交互積層の厚さは1000Åから3400Åの範囲であることを特徴とする、請求項1または2に記載の半導体ヘテロ構造。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP06291955A EP1933384B1 (en) | 2006-12-15 | 2006-12-15 | Semiconductor heterostructure |
EP06291955.0 | 2006-12-15 |
Publications (3)
Publication Number | Publication Date |
---|---|
JP2008153671A JP2008153671A (ja) | 2008-07-03 |
JP2008153671A6 JP2008153671A6 (ja) | 2008-09-25 |
JP5101263B2 true JP5101263B2 (ja) | 2012-12-19 |
Family
ID=38016685
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2007325121A Active JP5101263B2 (ja) | 2006-12-15 | 2007-12-17 | 半導体ヘテロ構造 |
Country Status (7)
Country | Link |
---|---|
US (1) | US7544976B2 (ja) |
EP (1) | EP1933384B1 (ja) |
JP (1) | JP5101263B2 (ja) |
KR (1) | KR100934039B1 (ja) |
CN (1) | CN101207016B (ja) |
SG (1) | SG144032A1 (ja) |
TW (1) | TWI354319B (ja) |
Families Citing this family (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1763069B1 (en) * | 2005-09-07 | 2016-04-13 | Soitec | Method for forming a semiconductor heterostructure |
EP1933384B1 (en) * | 2006-12-15 | 2013-02-13 | Soitec | Semiconductor heterostructure |
US7998835B2 (en) * | 2008-01-15 | 2011-08-16 | Globalfoundries Singapore Pte. Ltd. | Strain-direct-on-insulator (SDOI) substrate and method of forming |
TWI457984B (zh) * | 2008-08-06 | 2014-10-21 | Soitec Silicon On Insulator | 應變層的鬆弛方法 |
US20100044827A1 (en) * | 2008-08-22 | 2010-02-25 | Kinik Company | Method for making a substrate structure comprising a film and substrate structure made by same method |
JP5810718B2 (ja) * | 2011-03-18 | 2015-11-11 | 富士ゼロックス株式会社 | シリコン層転写用基板及び半導体基板の製造方法 |
US9105469B2 (en) * | 2011-06-30 | 2015-08-11 | Piquant Research Llc | Defect mitigation structures for semiconductor devices |
DE102011107657A1 (de) * | 2011-07-12 | 2013-01-17 | Nasp Iii/V Gmbh | Monolithische integrierte Halbleiterstruktur |
FR2995447B1 (fr) | 2012-09-07 | 2014-09-05 | Soitec Silicon On Insulator | Procede de separation d'au moins deux substrats selon une interface choisie |
CN103066157B (zh) * | 2013-01-07 | 2016-03-30 | 中国科学院上海微系统与信息技术研究所 | 一种降低InP基InGaAs异变材料表面粗糙度的方法 |
US9490123B2 (en) * | 2014-10-24 | 2016-11-08 | Globalfoundries Inc. | Methods of forming strained epitaxial semiconductor material(S) above a strain-relaxed buffer layer |
US9577042B1 (en) * | 2015-08-13 | 2017-02-21 | Globalfoundries Inc. | Semiconductor structure with multilayer III-V heterostructures |
US9685456B2 (en) * | 2015-09-04 | 2017-06-20 | Stmicroelectronics, Inc. | Method for manufacturing a transistor having a sharp junction by forming raised source-drain regions before forming gate regions and corresponding transistor produced by said method |
US9484439B1 (en) | 2015-09-21 | 2016-11-01 | International Business Machines Corporation | III-V fin on insulator |
JP6493197B2 (ja) * | 2015-12-18 | 2019-04-03 | 株式会社Sumco | シリコンゲルマニウムエピタキシャルウェーハの製造方法およびシリコンゲルマニウムエピタキシャルウェーハ |
JP7158842B2 (ja) * | 2017-01-23 | 2022-10-24 | アイメック・ヴェーゼットウェー | パワーエレクトロニクス装置用のiii-n系基板およびその製造方法 |
KR102618207B1 (ko) * | 2022-07-01 | 2024-01-02 | 주식회사 비아트론 | 에피택시 공정을 이용한 반도체 소자 제조 방법 및 이를 위한 제조 장치 |
WO2024005276A1 (ko) * | 2022-07-01 | 2024-01-04 | 주식회사 비아트론 | 에피택시 공정을 이용한 반도체 소자 제조 방법 및 이를 위한 제조 장치 |
Family Cites Families (12)
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CN1168147C (zh) * | 1999-01-14 | 2004-09-22 | 松下电器产业株式会社 | 半导体结晶的制造方法 |
JP3516623B2 (ja) * | 1999-01-14 | 2004-04-05 | 松下電器産業株式会社 | 半導体結晶の製造方法 |
JP4212228B2 (ja) * | 1999-09-09 | 2009-01-21 | 株式会社東芝 | 半導体装置の製造方法 |
JP4207548B2 (ja) * | 2002-11-28 | 2009-01-14 | 株式会社Sumco | 半導体基板の製造方法及び電界効果型トランジスタの製造方法並びに半導体基板及び電界効果型トランジスタ |
JP4296726B2 (ja) * | 2001-06-29 | 2009-07-15 | 株式会社Sumco | 半導体基板の製造方法及び電界効果型トランジスタの製造方法 |
JP3970011B2 (ja) * | 2001-12-11 | 2007-09-05 | シャープ株式会社 | 半導体装置及びその製造方法 |
AU2003274922A1 (en) * | 2002-08-23 | 2004-03-11 | Amberwave Systems Corporation | Semiconductor heterostructures having reduced dislocation pile-ups and related methods |
WO2004061944A1 (en) * | 2003-01-07 | 2004-07-22 | S.O.I.Tec Silicon On Insulator Technologies | Recycling of a wafer comprising a multi-layer structure after taking-off a thin layer |
US7217949B2 (en) * | 2004-07-01 | 2007-05-15 | International Business Machines Corporation | Strained Si MOSFET on tensile-strained SiGe-on-insulator (SGOI) |
JP2006080278A (ja) * | 2004-09-09 | 2006-03-23 | Toshiba Ceramics Co Ltd | 歪みシリコンウエハおよびその製造方法 |
KR100601976B1 (ko) * | 2004-12-08 | 2006-07-18 | 삼성전자주식회사 | 스트레인 실리콘 온 인슐레이터 구조체 및 그 제조방법 |
EP1933384B1 (en) * | 2006-12-15 | 2013-02-13 | Soitec | Semiconductor heterostructure |
-
2006
- 2006-12-15 EP EP06291955A patent/EP1933384B1/en active Active
-
2007
- 2007-02-08 US US11/672,663 patent/US7544976B2/en active Active
- 2007-10-12 TW TW096138302A patent/TWI354319B/zh active
- 2007-11-13 KR KR1020070115542A patent/KR100934039B1/ko active IP Right Grant
- 2007-11-15 SG SG200717773-6A patent/SG144032A1/en unknown
- 2007-12-17 CN CN2007101996984A patent/CN101207016B/zh active Active
- 2007-12-17 JP JP2007325121A patent/JP5101263B2/ja active Active
Also Published As
Publication number | Publication date |
---|---|
US7544976B2 (en) | 2009-06-09 |
TWI354319B (en) | 2011-12-11 |
JP2008153671A (ja) | 2008-07-03 |
KR20080055624A (ko) | 2008-06-19 |
SG144032A1 (en) | 2008-07-29 |
TW200826160A (en) | 2008-06-16 |
EP1933384A1 (en) | 2008-06-18 |
CN101207016A (zh) | 2008-06-25 |
KR100934039B1 (ko) | 2009-12-28 |
EP1933384B1 (en) | 2013-02-13 |
US20080142844A1 (en) | 2008-06-19 |
CN101207016B (zh) | 2012-04-25 |
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