JP5086039B2 - 半導体モジュールおよび撮像装置 - Google Patents
半導体モジュールおよび撮像装置 Download PDFInfo
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- JP5086039B2 JP5086039B2 JP2007296147A JP2007296147A JP5086039B2 JP 5086039 B2 JP5086039 B2 JP 5086039B2 JP 2007296147 A JP2007296147 A JP 2007296147A JP 2007296147 A JP2007296147 A JP 2007296147A JP 5086039 B2 JP5086039 B2 JP 5086039B2
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- semiconductor element
- semiconductor
- signal
- camera shake
- electrode
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05553—Shape in top view being rectangular
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
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- H—ELECTRICITY
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- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
- H01L2225/06562—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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Description
手振れのない場合には、撮像装置に角速度が生じないため、ジャイロイコライザ24の出力する信号は“0”となる。VCM80によって駆動されるレンズ60の位置は、その光軸と撮像装置に備えられるCCDなどの撮像素子(図示せず)の中心が一致するため、ホール素子70および増幅回路14によるアナログの位置信号は、ADC22により“0”を示すデジタルの位置信号に変換された後、ホールイコライザ40に出力される。サーボ回路44は、位置信号の値が“0”のとき、現在のレンズ60の位置を維持するようにVCM80を制御する信号を出力する。
VCM80によって駆動されるレンズ60の位置は、その光軸と撮像装置に備えられる撮像素子の中心が一致するため、ホール素子70および増幅回路14によるアナログの位置信号は、ADC22により“0”を示すデジタルの位置信号に変換された後、ホールイコライザ40に出力される。
Claims (5)
- 一方の主表面に基板電極が設けられた配線基板と、
前記配線基板に搭載され、ロジック信号を入力または出力するためのロジック信号用電極を有する第1の半導体素子と、
前記第1の半導体素子の上に搭載され、大電流を出力するための電流出力用電極を有する第2の半導体素子と、
前記ロジック信号用電極とこれに対応する前記基板電極とを電気的に接続する第1のボンディングワイヤと、
前記電流出力用電極とこれに対応する前記基板電極とを電気的に接続する第2のボンディングワイヤと、
前記第1の半導体素子と前記配線基板の上に並設して搭載されたメモリ素子と、
を備え、
前記配線基板の前記主表面側から見て、前記メモリ素子は、前記第2のボンディングワイヤが横切る前記第2の半導体素子の辺の対辺側に位置していることを特徴とする半導体モジュール。 - 前記メモリ素子は、前記配線基板の角部近傍に設けられていることを特徴とする請求項1に記載の半導体モジュール。
- 前記第1の半導体素子は、撮像装置の手振れ補正用の手振れ補正信号を出力し、
前記第2の半導体素子は、前記手振れ補正信号に従って前記撮像装置のレンズを駆動する駆動手段に供される大電流を出力することを特徴とする請求項1または2に記載の半導体モジュール。 - 前記駆動手段は、ボイスコイルモータであることを特徴とする請求項3に記載の半導体モジュール。
- 請求項1乃至4のいずれか1項に記載の半導体モジュールを備えることを特徴とする撮像装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007296147A JP5086039B2 (ja) | 2007-11-14 | 2007-11-14 | 半導体モジュールおよび撮像装置 |
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JP2007296147A JP5086039B2 (ja) | 2007-11-14 | 2007-11-14 | 半導体モジュールおよび撮像装置 |
Publications (2)
Publication Number | Publication Date |
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JP2009123910A JP2009123910A (ja) | 2009-06-04 |
JP5086039B2 true JP5086039B2 (ja) | 2012-11-28 |
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JP2007296147A Expired - Fee Related JP5086039B2 (ja) | 2007-11-14 | 2007-11-14 | 半導体モジュールおよび撮像装置 |
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Families Citing this family (1)
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JP5865220B2 (ja) * | 2012-09-24 | 2016-02-17 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
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JP3093603B2 (ja) * | 1994-04-15 | 2000-10-03 | 松下電器産業株式会社 | 半導体装置及びその製造方法 |
JP3658946B2 (ja) * | 1997-10-16 | 2005-06-15 | 日産自動車株式会社 | 電力用トランジスタの実装構造 |
JP2005252099A (ja) * | 2004-03-05 | 2005-09-15 | Sharp Corp | 高周波用半導体装置 |
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