JP5094371B2 - 半導体モジュールおよび撮像装置 - Google Patents
半導体モジュールおよび撮像装置 Download PDFInfo
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- JP5094371B2 JP5094371B2 JP2007333033A JP2007333033A JP5094371B2 JP 5094371 B2 JP5094371 B2 JP 5094371B2 JP 2007333033 A JP2007333033 A JP 2007333033A JP 2007333033 A JP2007333033 A JP 2007333033A JP 5094371 B2 JP5094371 B2 JP 5094371B2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/494—Connecting portions
- H01L2224/4943—Connecting portions the connecting portions being staggered
- H01L2224/49433—Connecting portions the connecting portions being staggered outside the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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- H01L2924/181—Encapsulation
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Description
手振れのない場合には、撮像装置に角速度が生じないため、ジャイロイコライザ24の出力する信号は“0”となる。VCM80によって駆動されるレンズ60の位置は、その光軸と撮像装置に備えられるCCDなどの撮像素子(図示せず)の中心が一致するため、ホール素子70および増幅回路14によるアナログの位置信号は、ADC22により“0”を示すデジタルの位置信号に変換された後、ホールイコライザ40に出力される。サーボ回路44は、位置信号の値が“0”のとき、現在のレンズ60の位置を維持するようにVCM80を制御する信号を出力する。
VCM80によって駆動されるレンズ60の位置は、その光軸と撮像装置に備えられる撮像素子の中心が一致するため、ホール素子70および増幅回路14によるアナログの位置信号は、ADC22により“0”を示すデジタルの位置信号に変換された後、ホールイコライザ40に出力される。
Claims (7)
- 一方の主表面に基板電極が設けられた配線基板と、
前記配線基板に搭載され、ロジック信号を入力または出力するためのロジック信号用電極を有する第1の半導体素子と、
前記第1の半導体素子に並設して搭載され、大電流を出力するための電流出力用電極を有する第2の半導体素子と、
前記ロジック信号用電極とこれに対応する前記基板電極とを電気的に接続する第1のボンディングワイヤと、
前記電流出力用電極とこれに対応する前記基板電極とを電気的に接続する第2のボンディングワイヤと、
前記第2の半導体素子と並設して前記配線基板の上に搭載されたメモリ素子と、
を備え、
前記配線基板の前記主表面側から見て、前記第2のボンディングワイヤは、前記メモリ素子が設けられた側の辺とは異なる前記第2の半導体素子の辺を横切っており、かつ、前記第2のボンディングワイヤは、前記メモリ素子が設けられた側の辺に設けられていないことを特徴とする半導体モジュール。 - 前記電流出力用電極は、前記第2のボンディングワイヤが横切る前記第2の半導体素子の辺に沿って設けられていることを特徴とする請求項1に記載の半導体モジュール。
- 前記第1の半導体素子は、撮像装置の手振れ補正用の手振れ補正信号を出力し、
前記第2の半導体素子は、前記手振れ補正信号に従って前記撮像装置のレンズを駆動する駆動手段に供される大電流を出力することを特徴とする請求項1または2に記載の半導体モジュール。 - 前記駆動手段は、ボイスコイルモータであることを特徴とする請求項3に記載の半導体モジュール。
- 前記第2のボンディングワイヤが横切る前記第2の半導体素子の辺と、当該辺に対向する前記配線基板の辺との距離が、前記第2のボンディングワイヤが横切る前記第2の半導体素子の辺の対辺と、当該対辺に対向する前記配線基板の辺との距離に比べて短いことを特徴とする請求項1乃至4のいずれか1項に記載の半導体モジュール。
- 前記第2のボンディングワイヤが横切る前記第2の半導体素子の辺と直交する方向において、前記第1の半導体素子と前記第2の半導体素子とが互いにずれて配置されていることを特徴とする請求項5に記載の半導体モジュール。
- 請求項1乃至6のいずれか1項に記載の半導体モジュールを備えることを特徴とする撮像装置。
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JP2007333033A JP5094371B2 (ja) | 2007-12-25 | 2007-12-25 | 半導体モジュールおよび撮像装置 |
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JP2009158608A JP2009158608A (ja) | 2009-07-16 |
JP5094371B2 true JP5094371B2 (ja) | 2012-12-12 |
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Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2004039689A (ja) * | 2002-06-28 | 2004-02-05 | Sony Corp | 電子回路装置 |
JP4748648B2 (ja) * | 2005-03-31 | 2011-08-17 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
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