JP5079646B2 - 半導体パッケージ及びその製造方法と半導体装置 - Google Patents

半導体パッケージ及びその製造方法と半導体装置 Download PDF

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Publication number
JP5079646B2
JP5079646B2 JP2008242066A JP2008242066A JP5079646B2 JP 5079646 B2 JP5079646 B2 JP 5079646B2 JP 2008242066 A JP2008242066 A JP 2008242066A JP 2008242066 A JP2008242066 A JP 2008242066A JP 5079646 B2 JP5079646 B2 JP 5079646B2
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Japan
Prior art keywords
lead pin
resin
solder
resin layer
layer
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JP2008242066A
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English (en)
Japanese (ja)
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JP2010080457A5 (https=
JP2010080457A (ja
Inventor
直幸 小泉
昭彦 立岩
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Shinko Electric Industries Co Ltd
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Shinko Electric Industries Co Ltd
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Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Priority to JP2008242066A priority Critical patent/JP5079646B2/ja
Priority to US12/512,277 priority patent/US8120166B2/en
Publication of JP2010080457A publication Critical patent/JP2010080457A/ja
Publication of JP2010080457A5 publication Critical patent/JP2010080457A5/ja
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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/28—Applying non-metallic protective coatings
    • H05K3/284—Applying non-metallic protective coatings for encapsulating mounted components
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/093—Connecting or disconnecting other interconnections thereto or therefrom, e.g. connecting bond wires or bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/685—Shapes or dispositions thereof comprising multiple insulating layers
    • H10W70/687—Shapes or dispositions thereof comprising multiple insulating layers characterized by the outer layers being for protection, e.g. solder masks, or for protection against chemical or mechanical damage
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09009—Substrate related
    • H05K2201/091—Locally and permanently deformed areas including dielectric material
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10227—Other objects, e.g. metallic pieces
    • H05K2201/1031—Surface mounted metallic connector elements
    • H05K2201/10318—Surface mounted metallic pins
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10954—Other details of electrical connections
    • H05K2201/10977—Encapsulated connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4682—Manufacture of core-less build-up multilayer circuits on a temporary carrier or on a metal foil
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63—Vias, e.g. via plugs
    • H10W70/635—Through-vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H10W70/654—Top-view layouts
    • H10W70/655—Fan-out layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/685—Shapes or dispositions thereof comprising multiple insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/69—Insulating materials thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
JP2008242066A 2008-08-26 2008-09-22 半導体パッケージ及びその製造方法と半導体装置 Active JP5079646B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2008242066A JP5079646B2 (ja) 2008-08-26 2008-09-22 半導体パッケージ及びその製造方法と半導体装置
US12/512,277 US8120166B2 (en) 2008-08-26 2009-07-30 Semiconductor package and method of manufacturing the same, and semiconductor device and method of manufacturing the same

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2008216325 2008-08-26
JP2008216325 2008-08-26
JP2008242066A JP5079646B2 (ja) 2008-08-26 2008-09-22 半導体パッケージ及びその製造方法と半導体装置

Publications (3)

Publication Number Publication Date
JP2010080457A JP2010080457A (ja) 2010-04-08
JP2010080457A5 JP2010080457A5 (https=) 2011-08-18
JP5079646B2 true JP5079646B2 (ja) 2012-11-21

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US (1) US8120166B2 (https=)
JP (1) JP5079646B2 (https=)

Families Citing this family (38)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7688237B2 (en) * 2006-12-21 2010-03-30 Broadcom Corporation Apparatus and method for analog-to-digital converter calibration
KR20110058938A (ko) * 2009-11-27 2011-06-02 삼성전기주식회사 반도체 패키지용 리드핀 및 반도체 패키지
JP5590985B2 (ja) * 2010-06-21 2014-09-17 新光電気工業株式会社 半導体装置及びその製造方法
JP2012009586A (ja) * 2010-06-24 2012-01-12 Shinko Electric Ind Co Ltd 配線基板、半導体装置及び配線基板の製造方法
JP5548062B2 (ja) * 2010-08-11 2014-07-16 株式会社日立製作所 配管用モジュール向け仮設部材の施工方法及び配管モジュールの搬送方法
JP2012164965A (ja) 2011-01-21 2012-08-30 Ngk Spark Plug Co Ltd 配線基板及びその製造方法
JP2012169591A (ja) * 2011-01-24 2012-09-06 Ngk Spark Plug Co Ltd 多層配線基板
US8952540B2 (en) * 2011-06-30 2015-02-10 Intel Corporation In situ-built pin-grid arrays for coreless substrates, and methods of making same
US8872358B2 (en) * 2012-02-07 2014-10-28 Shin-Etsu Chemical Co., Ltd. Sealant laminated composite, sealed semiconductor devices mounting substrate, sealed semiconductor devices forming wafer, semiconductor apparatus, and method for manufacturing semiconductor apparatus
US9354748B2 (en) 2012-02-13 2016-05-31 Microsoft Technology Licensing, Llc Optical stylus interaction
US9360893B2 (en) 2012-03-02 2016-06-07 Microsoft Technology Licensing, Llc Input device writing surface
US9064654B2 (en) * 2012-03-02 2015-06-23 Microsoft Technology Licensing, Llc Method of manufacturing an input device
US9870066B2 (en) * 2012-03-02 2018-01-16 Microsoft Technology Licensing, Llc Method of manufacturing an input device
US9075566B2 (en) 2012-03-02 2015-07-07 Microsoft Technoogy Licensing, LLC Flexible hinge spine
USRE48963E1 (en) 2012-03-02 2022-03-08 Microsoft Technology Licensing, Llc Connection device for computing devices
US9426905B2 (en) 2012-03-02 2016-08-23 Microsoft Technology Licensing, Llc Connection device for computing devices
US9134807B2 (en) 2012-03-02 2015-09-15 Microsoft Technology Licensing, Llc Pressure sensitive key normalization
US8935774B2 (en) 2012-03-02 2015-01-13 Microsoft Corporation Accessory device authentication
US8873227B2 (en) 2012-03-02 2014-10-28 Microsoft Corporation Flexible hinge support layer
US20130300590A1 (en) 2012-05-14 2013-11-14 Paul Henry Dietz Audio Feedback
US10031556B2 (en) 2012-06-08 2018-07-24 Microsoft Technology Licensing, Llc User experience adaptation
US9019615B2 (en) 2012-06-12 2015-04-28 Microsoft Technology Licensing, Llc Wide field-of-view virtual image projector
US9073123B2 (en) 2012-06-13 2015-07-07 Microsoft Technology Licensing, Llc Housing vents
US8964379B2 (en) 2012-08-20 2015-02-24 Microsoft Corporation Switchable magnetic lock
US8654030B1 (en) 2012-10-16 2014-02-18 Microsoft Corporation Antenna placement
EP2908971B1 (en) 2012-10-17 2018-01-03 Microsoft Technology Licensing, LLC Metal alloy injection molding overflows
WO2014059624A1 (en) 2012-10-17 2014-04-24 Microsoft Corporation Metal alloy injection molding protrusions
WO2014059618A1 (en) 2012-10-17 2014-04-24 Microsoft Corporation Graphic formation via material ablation
JP2014103176A (ja) * 2012-11-16 2014-06-05 Shin Etsu Chem Co Ltd 支持基材付封止材、封止後半導体素子搭載基板、封止後半導体素子形成ウエハ、半導体装置、及び半導体装置の製造方法
US8946884B2 (en) * 2013-03-08 2015-02-03 Xilinx, Inc. Substrate-less interposer technology for a stacked silicon interconnect technology (SSIT) product
US9304549B2 (en) 2013-03-28 2016-04-05 Microsoft Technology Licensing, Llc Hinge mechanism for rotatable component attachment
US10120420B2 (en) 2014-03-21 2018-11-06 Microsoft Technology Licensing, Llc Lockable display and techniques enabling use of lockable displays
US10324733B2 (en) 2014-07-30 2019-06-18 Microsoft Technology Licensing, Llc Shutdown notifications
JP6358431B2 (ja) * 2014-08-25 2018-07-18 新光電気工業株式会社 電子部品装置及びその製造方法
US9424048B2 (en) 2014-09-15 2016-08-23 Microsoft Technology Licensing, Llc Inductive peripheral retention device
JP7107120B2 (ja) * 2018-09-14 2022-07-27 富士電機株式会社 半導体装置、半導体装置の製造方法
US11427466B2 (en) * 2019-07-19 2022-08-30 Advanced Semiconductor Engineering, Inc. Semiconductor package structure and method for manufacturing the same
EP3859776B1 (en) * 2020-01-31 2026-02-25 Infineon Technologies AG Power semiconductor device and method for fabricating a power semiconductor device

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01100958A (ja) 1987-10-14 1989-04-19 Hitachi Ltd 樹脂被覆セラミック配線基板
JP2000058736A (ja) * 1998-08-07 2000-02-25 Sumitomo Kinzoku Electro Device:Kk 樹脂基板へのピン接続方法
JP2001148441A (ja) 1999-11-19 2001-05-29 Shinko Electric Ind Co Ltd 半導体パッケージ及びその製造方法
JP2006216631A (ja) * 2005-02-02 2006-08-17 Ngk Spark Plug Co Ltd 配線基板およびその製造方法
JP4993754B2 (ja) * 2008-02-22 2012-08-08 新光電気工業株式会社 Ｐｇａ型配線基板及びその製造方法

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US8120166B2 (en) 2012-02-21
US20100052153A1 (en) 2010-03-04
JP2010080457A (ja) 2010-04-08

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