JP5044201B2 - 半導体記憶装置 - Google Patents
半導体記憶装置 Download PDFInfo
- Publication number
- JP5044201B2 JP5044201B2 JP2006323022A JP2006323022A JP5044201B2 JP 5044201 B2 JP5044201 B2 JP 5044201B2 JP 2006323022 A JP2006323022 A JP 2006323022A JP 2006323022 A JP2006323022 A JP 2006323022A JP 5044201 B2 JP5044201 B2 JP 5044201B2
- Authority
- JP
- Japan
- Prior art keywords
- high voltage
- memory cell
- gate
- switching circuit
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
- G11C16/0425—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a merged floating gate and select transistor
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/12—Programming voltage switching circuits
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Read Only Memory (AREA)
- Non-Volatile Memory (AREA)
Description
書き込み時に、不揮発性メモリセルトランジスタの制御ゲートとドレインに所定の電圧を印加し、前記第1及び第2のスイッチを通してソースに高電圧を印加し、チャネル電流を流すことにより、ゲート絶縁膜を通してフローティングゲートにチャネルホットエレクトロンを注入することを特徴とする。
13 第1の転送ゲート 14 第2の転送ゲート
15 第3の転送ゲート 16 ワード線デコーダ
17 定電流回路 101 P型半導体基板
102 ドレイン 103 ソース
104 チャネル 105 ゲート絶縁膜
106 フローティングゲート 107 厚い絶縁膜
108 トンネル絶縁膜 109 制御ゲート
112 セット用MOSトランジスタ
113 リセット用MOSトランジスタ
114 Pチャネル型MOSトランジスタ
INV1 第1のCMOSインバータ
INV2 第2のCMOSインバータ
SL ソース線 WL ワード線
Claims (2)
- 電気的にデータの消去及び書込みが可能な複数の不揮発性メモリセルトランジスタと、
前記複数の不揮発性メモリセルトランジスタのソースが接続されたソース線と、
前記複数の不揮発性メモリセルトランジスタの制御ゲートが接続されたワード線と、
データの消去及び書き込みのための高電圧を発生する高電圧発生回路と、
選択信号に応じてスイッチングし、高電圧発生回路から発生された高電圧を高電圧出力ノードから出力するラッチ型の高電圧スイッチング回路と、
書き込み時に、書き込みイネーブル信号に応じて導通し、高電圧スイッチング回路から出力された高電圧をソース線に出力する第1のスイッチと、
消去時に、消去イネーブル信号に応じて導通し、高電圧スイッチング回路から出力された高電圧をワード線に出力する第2のスイッチと、
書き込み時に、高電圧スイッチング回路の低電圧出力ノードからの信号に応じて導通し、前記高電圧発生回路から発生された高電圧を、高電圧スイッチング回路を介さずに前記ソース線に出力する第3のスイッチと、を備え、
書き込み時に、不揮発性メモリセルトランジスタの制御ゲートとドレインに所定の電圧を印加し、前記第1及び第2のスイッチを通してソースに高電圧を印加し、チャネル電流を流すことにより、ゲート絶縁膜を通してフローティングゲートにチャネルホットエレクトロンを注入することを特徴とする半導体記憶装置。 - 前記第1のスイッチ、前記第2のスイッチ及び前記第3のスイッチは、転送ゲートからなることを特徴とする請求項1に記載の半導体記憶装置。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006323022A JP5044201B2 (ja) | 2006-11-30 | 2006-11-30 | 半導体記憶装置 |
TW096140928A TWI354296B (en) | 2006-11-30 | 2007-10-31 | Semiconductor memory device |
US11/946,674 US7542349B2 (en) | 2006-11-30 | 2007-11-28 | Semiconductor memory device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006323022A JP5044201B2 (ja) | 2006-11-30 | 2006-11-30 | 半導体記憶装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2008140430A JP2008140430A (ja) | 2008-06-19 |
JP5044201B2 true JP5044201B2 (ja) | 2012-10-10 |
Family
ID=39475524
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2006323022A Active JP5044201B2 (ja) | 2006-11-30 | 2006-11-30 | 半導体記憶装置 |
Country Status (3)
Country | Link |
---|---|
US (1) | US7542349B2 (ja) |
JP (1) | JP5044201B2 (ja) |
TW (1) | TWI354296B (ja) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8320191B2 (en) | 2007-08-30 | 2012-11-27 | Infineon Technologies Ag | Memory cell arrangement, method for controlling a memory cell, memory array and electronic device |
US7914609B2 (en) * | 2007-10-29 | 2011-03-29 | Briggs & Stratton Corporation | Cyclonic air cleaner assembly |
KR102103544B1 (ko) | 2013-01-22 | 2020-04-23 | 삼성전자주식회사 | 고전압 스위치 및 그것을 포함하는 불휘발성 메모리 장치 |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB9423038D0 (en) * | 1994-11-15 | 1995-01-04 | Sgs Thomson Microelectronics | An integrated circuit memory device with voltage boost |
US6047352A (en) * | 1996-10-29 | 2000-04-04 | Micron Technology, Inc. | Memory system, method and predecoding circuit operable in different modes for selectively accessing multiple blocks of memory cells for simultaneous writing or erasure |
JP3561647B2 (ja) | 1998-12-10 | 2004-09-02 | 三洋電機株式会社 | 1チップマイクロコンピュータ |
JP2000349263A (ja) * | 1999-06-09 | 2000-12-15 | Sanyo Electric Co Ltd | 抵抗調整装置及びrc発振回路 |
JP2003045192A (ja) * | 2001-07-30 | 2003-02-14 | Sanyo Electric Co Ltd | 不揮発性メモリ |
-
2006
- 2006-11-30 JP JP2006323022A patent/JP5044201B2/ja active Active
-
2007
- 2007-10-31 TW TW096140928A patent/TWI354296B/zh not_active IP Right Cessation
- 2007-11-28 US US11/946,674 patent/US7542349B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
JP2008140430A (ja) | 2008-06-19 |
US7542349B2 (en) | 2009-06-02 |
TWI354296B (en) | 2011-12-11 |
TW200832433A (en) | 2008-08-01 |
US20080130374A1 (en) | 2008-06-05 |
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