JP5042038B2 - 半導体装置を製造する方法 - Google Patents
半導体装置を製造する方法 Download PDFInfo
- Publication number
- JP5042038B2 JP5042038B2 JP2007553093A JP2007553093A JP5042038B2 JP 5042038 B2 JP5042038 B2 JP 5042038B2 JP 2007553093 A JP2007553093 A JP 2007553093A JP 2007553093 A JP2007553093 A JP 2007553093A JP 5042038 B2 JP5042038 B2 JP 5042038B2
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- gate stack
- dopant
- plasma
- dielectric layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28079—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a single metal, e.g. Ta, W, Mo, Al
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
- H01L21/02321—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
- H01L21/02337—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour
- H01L21/0234—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour treatment by exposure to a plasma
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/60—Electrodes characterised by their materials
- H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
- H10D64/665—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of elemental metal contacting the insulator, e.g. tungsten or molybdenum
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
- H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Power Engineering (AREA)
- Plasma & Fusion (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
- Formation Of Insulating Films (AREA)
- Thin Film Transistor (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US11/045,124 | 2005-01-31 | ||
| US11/045,124 US7393761B2 (en) | 2005-01-31 | 2005-01-31 | Method for fabricating a semiconductor device |
| PCT/US2005/043293 WO2006083380A2 (en) | 2005-01-31 | 2005-11-30 | Method for fabricating a semiconductor device |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2008532262A JP2008532262A (ja) | 2008-08-14 |
| JP2008532262A5 JP2008532262A5 (enExample) | 2009-02-19 |
| JP5042038B2 true JP5042038B2 (ja) | 2012-10-03 |
Family
ID=36757111
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2007553093A Expired - Fee Related JP5042038B2 (ja) | 2005-01-31 | 2005-11-30 | 半導体装置を製造する方法 |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US7393761B2 (enExample) |
| JP (1) | JP5042038B2 (enExample) |
| KR (1) | KR101161468B1 (enExample) |
| CN (1) | CN101128922B (enExample) |
| WO (1) | WO2006083380A2 (enExample) |
Families Citing this family (24)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007088199A (ja) * | 2005-09-22 | 2007-04-05 | Canon Inc | 処理装置 |
| US7667247B2 (en) * | 2007-03-30 | 2010-02-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for passivating gate dielectric films |
| US7713757B2 (en) * | 2008-03-14 | 2010-05-11 | Applied Materials, Inc. | Method for measuring dopant concentration during plasma ion implantation |
| US9711373B2 (en) * | 2008-09-22 | 2017-07-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of fabricating a gate dielectric for high-k metal gate devices |
| US7807961B2 (en) * | 2008-10-08 | 2010-10-05 | Varian Semiconductor Equipment Associates, Inc. | Techniques for ion implantation of molecular ions |
| US8664070B2 (en) * | 2009-12-21 | 2014-03-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | High temperature gate replacement process |
| US8836035B2 (en) * | 2010-03-10 | 2014-09-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method and apparatus for reducing gate resistance |
| US8436318B2 (en) * | 2010-04-05 | 2013-05-07 | Varian Semiconductor Equipment Associates, Inc. | Apparatus for controlling the temperature of an RF ion source window |
| WO2011145633A1 (en) * | 2010-05-21 | 2011-11-24 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
| JP2013534712A (ja) * | 2010-06-23 | 2013-09-05 | 東京エレクトロン株式会社 | プラズマドーピング装置、プラズマドーピング方法、半導体素子の製造方法、および半導体素子 |
| US8003503B1 (en) | 2010-09-30 | 2011-08-23 | Tokyo Electron Limited | Method of integrating stress into a gate stack |
| US20130149852A1 (en) * | 2011-12-08 | 2013-06-13 | Tokyo Electron Limited | Method for forming a semiconductor device |
| JP2013165254A (ja) * | 2012-01-13 | 2013-08-22 | Tokyo Electron Ltd | プラズマドーピング装置、プラズマドーピング方法、半導体素子の製造方法、および半導体素子 |
| US20150132929A1 (en) * | 2012-05-01 | 2015-05-14 | Tokyo Electron Limited | Method for injecting dopant into substrate to be processed, and plasma doping apparatus |
| EP2885868A4 (en) | 2012-08-16 | 2016-04-13 | Bayer Ip Gmbh | LAMINATED AND COMPLIANT DIELECTRIC ELASTOMER ACTUATORS |
| EP2917945B1 (en) * | 2012-11-06 | 2019-01-09 | Parker-Hannifin Corporation | Stacked electroactive transducer and fabrication method thereof |
| CN104347411B (zh) * | 2013-08-01 | 2018-04-13 | 中国科学院微电子研究所 | 金属栅电极等效功函数调节方法 |
| TWI590329B (zh) * | 2014-03-02 | 2017-07-01 | 東京威力科創股份有限公司 | 藉由微波電漿處理以提升半導體裝置中之高介電常數膜成核速率及電移動度的方法 |
| US20180138292A1 (en) * | 2016-11-11 | 2018-05-17 | Sandisk Technologies Llc | Methods and apparatus for three-dimensional nonvolatile memory |
| US10431462B2 (en) * | 2017-02-15 | 2019-10-01 | Lam Research Corporation | Plasma assisted doping on germanium |
| US10332747B1 (en) | 2018-01-24 | 2019-06-25 | Globalfoundries Inc. | Selective titanium nitride deposition using oxides of lanthanum masks |
| JP2021048239A (ja) | 2019-09-18 | 2021-03-25 | キオクシア株式会社 | 半導体装置およびその製造方法 |
| US11355325B2 (en) * | 2020-05-28 | 2022-06-07 | Applied Materials, Inc. | Methods and systems for monitoring input power for process control in semiconductor process systems |
| US11854770B2 (en) * | 2021-01-14 | 2023-12-26 | Applied Materials, Inc. | Plasma processing with independent temperature control |
Family Cites Families (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6841203B2 (en) * | 1997-12-24 | 2005-01-11 | Tokyo Electron Limited | Method of forming titanium film by CVD |
| US6285038B1 (en) * | 2000-03-01 | 2001-09-04 | Micron Technology, Inc. | Integrated circuitry and DRAM integrated circuitry |
| TW445540B (en) * | 2000-08-07 | 2001-07-11 | Nano Architect Res Corp | Bundle concentrating type multi-chamber plasma reacting system |
| US6383880B1 (en) * | 2000-10-05 | 2002-05-07 | Advanced Micro Devices, Inc. | NH3/N2-plasma treatment for reduced nickel silicide bridging |
| JP4090225B2 (ja) * | 2001-08-29 | 2008-05-28 | 東京エレクトロン株式会社 | 半導体装置の製造方法、及び、基板処理方法 |
| JP4198903B2 (ja) * | 2001-08-31 | 2008-12-17 | 株式会社東芝 | 半導体記憶装置 |
| JP4001498B2 (ja) * | 2002-03-29 | 2007-10-31 | 東京エレクトロン株式会社 | 絶縁膜の形成方法及び絶縁膜の形成システム |
| JP4387355B2 (ja) * | 2003-02-19 | 2009-12-16 | パナソニック株式会社 | 不純物導入方法 |
| US7015534B2 (en) * | 2003-10-14 | 2006-03-21 | Texas Instruments Incorporated | Encapsulated MOS transistor gate structures and methods for making the same |
| US6936518B2 (en) * | 2004-01-21 | 2005-08-30 | Intel Corporation | Creating shallow junction transistors |
| US7514360B2 (en) * | 2004-03-17 | 2009-04-07 | Hong Yu Yu | Thermal robust semiconductor device using HfN as metal gate electrode and the manufacturing process thereof |
-
2005
- 2005-01-31 US US11/045,124 patent/US7393761B2/en not_active Expired - Lifetime
- 2005-11-30 WO PCT/US2005/043293 patent/WO2006083380A2/en not_active Ceased
- 2005-11-30 KR KR1020077014095A patent/KR101161468B1/ko not_active Expired - Fee Related
- 2005-11-30 CN CN2005800474755A patent/CN101128922B/zh not_active Expired - Fee Related
- 2005-11-30 JP JP2007553093A patent/JP5042038B2/ja not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| CN101128922A (zh) | 2008-02-20 |
| WO2006083380A2 (en) | 2006-08-10 |
| CN101128922B (zh) | 2010-06-09 |
| KR20070100719A (ko) | 2007-10-11 |
| US20060172474A1 (en) | 2006-08-03 |
| US7393761B2 (en) | 2008-07-01 |
| JP2008532262A (ja) | 2008-08-14 |
| KR101161468B1 (ko) | 2012-07-02 |
| WO2006083380A3 (en) | 2007-06-21 |
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