JP5032449B2 - Mramデバイス - Google Patents
Mramデバイス Download PDFInfo
- Publication number
- JP5032449B2 JP5032449B2 JP2008302810A JP2008302810A JP5032449B2 JP 5032449 B2 JP5032449 B2 JP 5032449B2 JP 2008302810 A JP2008302810 A JP 2008302810A JP 2008302810 A JP2008302810 A JP 2008302810A JP 5032449 B2 JP5032449 B2 JP 5032449B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- mram
- magnetic
- mram device
- conductive layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N50/00—Galvanomagnetic devices
- H10N50/01—Manufacture or treatment
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/14—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using thin-film elements
- G11C11/15—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using thin-film elements using multiple magnetic layers
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
Landscapes
- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Nanotechnology (AREA)
- Physics & Mathematics (AREA)
- Mathematical Physics (AREA)
- Theoretical Computer Science (AREA)
- Crystallography & Structural Chemistry (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Semiconductor Memories (AREA)
- Hall/Mr Elements (AREA)
- Mram Or Spin Memory Techniques (AREA)
Description
12 セパレータ
16 絶縁層
18 第1バリヤ層
19 第2バリヤ層
20 第1導電性層
21 シード層
22 第1磁性層
23 反強磁性層
24 側壁
26 凹み領域
28 非磁性層
30 第2磁性層
31 第3バリヤ層
32 MRANスタック
34 島
36 第2導電性層
38 底部部分
Claims (17)
- 基板と、
該基板上に設けられ、側壁および該側壁の間に配列された層からなる絶縁層と、
前記配列された層上で、かつ前記側壁の間に設けられている第1バリヤ層と、
前記第1バリヤ層上に設けられた第1導電性層と、
前記第1導電性層上に設けられた第2バリヤ層と、
前記第2バリヤ層上に設けられたシード層と、
前記シード層上に設けられた反強磁性層と、
前記反強磁性層上で、かつ前記側壁の間に設けられた第1磁性層であって、前記第1磁性層が固定磁気配向を有し、その部分中に上部凹み領域を有する、前記第1磁性層と、
前記第1磁性層の前記領域上に設けられ、少なくとも部分的に前記第1磁性層の前記上部凹み領域の内部にある非磁性層と、
前記非磁性層上に設けられ、自由な磁気配向を有する、第2磁性層と、
前記第2磁性層上の第3バリヤ層と、
前記第3バリヤ層上にあり、かつ前記第1導性電層に対して直交する第2導電性層と
を備えたことを特徴とするMRAMデバイス。 - 前記絶縁層が、窒化物を含むことを特徴とする請求項1に記載のMRAMデバイス。
- 前記第1、第2および第3バリヤ層が、タンタルを含むことを特徴とする請求項1に記載のMRAMデバイス。
- 前記第1導電性層が、銅を含むことを特徴とする請求項1に記載のMRAMデバイス。
- 前記シード層が、ニッケル鉄を含むことを特徴とする請求項1に記載のMRAMデバイス。
- 前記反強磁性層が、鉄マンガンを含むことを特徴とする請求項1に記載のMRAMデバイス。
- 前記第1磁性層が、ニッケル鉄を含むことを特徴とする請求項1に記載のMRAMデバイス。
- 前記非磁性層が、アルミニウム酸化物を含むことを特徴とする請求項1に記載のMRAMデバイス。
- 前記第2磁性層が、ニッケル鉄を含むことを特徴とする請求項1に記載のMRAMデバイス。
- 前記第2導電性層が、銅を含むことを特徴とする請求項1に記載のMRAMデバイス。
- 前記第1導電性層がビット線であり、前記第2導電性層がワード線であることを特徴とする請求項1に記載のMRAMデバイス。
- 誘電体層を前記第2導電性層上に設けたことを特徴とする請求項1に記載のMRAMデバイス。
- プロセッサと、該プロセッサに結合されたMRAMメモリ回路を含むプロセッサシステムであって、前記MRAMメモリ回路が、請求項1に記載のMRAMデバイスからなることを特徴とするプロセッサシステム。
- 前記側壁および該側壁の間に配列された層が、窒化物を含むことを特徴とする請求項13に記載のプロセッサシステム。
- 前記バリヤ層がタンタルを含み、前記第1導電性層が銅を含み、前記シード層がニッケル鉄を含み、前記反強磁性層が鉄マンガンを含み、前記第1磁性層がニッケル鉄を含み、前記非磁性層がアルミニウム酸化物を含み、前記第2磁性層がニッケル鉄を含み、前記第2導電性層がセンス線であり、前記第1導電性層がディジット線であることを特徴とする請求項13に記載のプロセッサシステム。
- 前記第2導電性層上に誘電体層を設けたことを特徴とする請求項13に記載のプロセッサシステム。
- プロセッサおよびMRAM回路が、単一チップ上に集積されていることを特徴とする請求項13に記載のプロセッサシステム。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/805,916 | 2001-03-15 | ||
US09/805,916 US6653154B2 (en) | 2001-03-15 | 2001-03-15 | Method of forming self-aligned, trenchless mangetoresistive random-access memory (MRAM) structure with sidewall containment of MRAM structure |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2002574699A Division JP4589603B2 (ja) | 2001-03-15 | 2002-03-12 | Mram構造を側壁によって閉じ込める、自己整合型かつトレンチなし磁気抵抗ランダムアクセスメモリ(mram)構造の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2009088544A JP2009088544A (ja) | 2009-04-23 |
JP5032449B2 true JP5032449B2 (ja) | 2012-09-26 |
Family
ID=25192864
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2002574699A Expired - Lifetime JP4589603B2 (ja) | 2001-03-15 | 2002-03-12 | Mram構造を側壁によって閉じ込める、自己整合型かつトレンチなし磁気抵抗ランダムアクセスメモリ(mram)構造の製造方法 |
JP2008302810A Expired - Lifetime JP5032449B2 (ja) | 2001-03-15 | 2008-11-27 | Mramデバイス |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2002574699A Expired - Lifetime JP4589603B2 (ja) | 2001-03-15 | 2002-03-12 | Mram構造を側壁によって閉じ込める、自己整合型かつトレンチなし磁気抵抗ランダムアクセスメモリ(mram)構造の製造方法 |
Country Status (7)
Country | Link |
---|---|
US (3) | US6653154B2 (ja) |
EP (1) | EP1368830B1 (ja) |
JP (2) | JP4589603B2 (ja) |
KR (1) | KR100605637B1 (ja) |
AU (1) | AU2002258488A1 (ja) |
DE (1) | DE10291412B4 (ja) |
WO (1) | WO2002075782A2 (ja) |
Families Citing this family (50)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE10043947A1 (de) * | 2000-09-06 | 2002-04-04 | Infineon Technologies Ag | Integrierte Schaltungsanordnung |
WO2002068508A1 (en) * | 2001-02-23 | 2002-09-06 | The Gates Corporation | Process for directly bonding rubber to at least a second substrate, and the resulting article |
JP2002314049A (ja) * | 2001-04-18 | 2002-10-25 | Nec Corp | 磁性メモリ及びその製造方法 |
AU2003243244A1 (en) * | 2002-05-16 | 2003-12-02 | Micron Technology, Inc. | STACKED 1T-nMEMORY CELL STRUCTURE |
US6940748B2 (en) * | 2002-05-16 | 2005-09-06 | Micron Technology, Inc. | Stacked 1T-nMTJ MRAM structure |
US7042749B2 (en) * | 2002-05-16 | 2006-05-09 | Micron Technology, Inc. | Stacked 1T-nmemory cell structure |
US6896730B2 (en) * | 2002-06-05 | 2005-05-24 | Micron Technology, Inc. | Atomic layer deposition apparatus and methods |
US6780653B2 (en) * | 2002-06-06 | 2004-08-24 | Micron Technology, Inc. | Methods of forming magnetoresistive memory device assemblies |
US6828639B2 (en) * | 2002-07-17 | 2004-12-07 | Micron Technology, Inc. | Process flow for building MRAM structures |
US6916374B2 (en) * | 2002-10-08 | 2005-07-12 | Micron Technology, Inc. | Atomic layer deposition methods and atomic layer deposition tools |
US6884630B2 (en) * | 2002-10-30 | 2005-04-26 | Infineon Technologies Ag | Two-step magnetic tunnel junction stack deposition |
JP3931876B2 (ja) * | 2002-11-01 | 2007-06-20 | 日本電気株式会社 | 磁気抵抗デバイス及びその製造方法 |
US7394626B2 (en) | 2002-11-01 | 2008-07-01 | Nec Corporation | Magnetoresistance device with a diffusion barrier between a conductor and a magnetoresistance element and method of fabricating the same |
AU2003290956A1 (en) * | 2002-11-15 | 2004-06-15 | President And Fellows Of Harvard College | Atomic layer deposition using metal amidinates |
JP2004200245A (ja) | 2002-12-16 | 2004-07-15 | Nec Corp | 磁気抵抗素子及び磁気抵抗素子の製造方法 |
KR100481876B1 (ko) * | 2003-02-20 | 2005-04-11 | 삼성전자주식회사 | 자기 터널 접합을 구비하는 자기 메모리 및 그 제조 방법 |
US7199055B2 (en) | 2003-03-03 | 2007-04-03 | Cypress Semiconductor Corp. | Magnetic memory cell junction and method for forming a magnetic memory cell junction |
US7911832B2 (en) * | 2003-08-19 | 2011-03-22 | New York University | High speed low power magnetic devices based on current induced spin-momentum transfer |
US8755222B2 (en) | 2003-08-19 | 2014-06-17 | New York University | Bipolar spin-transfer switching |
US7573737B2 (en) * | 2003-08-19 | 2009-08-11 | New York University | High speed low power magnetic devices based on current induced spin-momentum transfer |
US20050073878A1 (en) * | 2003-10-03 | 2005-04-07 | Taiwan Semiconductor Manufacturing Co., Ltd. | Multi-sensing level MRAM structure with different magnetoresistance ratios |
US9029189B2 (en) * | 2003-11-14 | 2015-05-12 | President And Fellows Of Harvard College | Bicyclic guanidines, metal complexes thereof and their use in vapor deposition |
EP1687899A4 (en) * | 2003-11-18 | 2008-10-08 | Halliburton Energy Serv Inc | HIGH VOLTAGE TRANSISTORS ON INSULATING SUBSTRATES |
US7705340B2 (en) * | 2004-10-05 | 2010-04-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Inflected magnetoresistive structures and memory cells having inflected magnetoresistive structures |
US9812184B2 (en) | 2007-10-31 | 2017-11-07 | New York University | Current induced spin-momentum transfer stack with dual insulating layers |
KR100949804B1 (ko) * | 2007-12-14 | 2010-03-30 | 한국전자통신연구원 | 자기장 감지소자 |
KR100952468B1 (ko) * | 2007-12-14 | 2010-04-13 | 한국전자통신연구원 | 자기장 감지소자의 제조방법 |
US7919407B1 (en) * | 2009-11-17 | 2011-04-05 | Magic Technologies, Inc. | Method of high density field induced MRAM process |
US8564039B2 (en) | 2010-04-07 | 2013-10-22 | Micron Technology, Inc. | Semiconductor devices including gate structures comprising colossal magnetocapacitive materials |
JP6043478B2 (ja) | 2010-12-07 | 2016-12-14 | 三星電子株式会社Samsung Electronics Co.,Ltd. | 磁気異方性物質の自由磁性層を含むストレージノード、これを含む磁気メモリ素子及びその製造方法 |
CN102572323B (zh) * | 2011-12-28 | 2014-12-10 | 中国科学院上海高等研究院 | 图像传感器像素电路 |
TWI462278B (zh) * | 2012-02-16 | 2014-11-21 | Macronix Int Co Ltd | 半導體結構及其製造方法 |
CN103258825B (zh) * | 2012-02-21 | 2015-08-12 | 旺宏电子股份有限公司 | 半导体结构及其制造方法 |
JP6072478B2 (ja) * | 2012-09-07 | 2017-02-01 | 株式会社日立ハイテクノロジーズ | 磁気抵抗素子の製造方法 |
US9082950B2 (en) | 2012-10-17 | 2015-07-14 | New York University | Increased magnetoresistance in an inverted orthogonal spin transfer layer stack |
US9082888B2 (en) | 2012-10-17 | 2015-07-14 | New York University | Inverted orthogonal spin transfer layer stack |
KR101967352B1 (ko) * | 2012-10-31 | 2019-04-10 | 삼성전자주식회사 | 자기 메모리 소자 및 그 제조 방법 |
US8982613B2 (en) | 2013-06-17 | 2015-03-17 | New York University | Scalable orthogonal spin transfer magnetic random access memory devices with reduced write error rates |
WO2015050982A1 (en) | 2013-10-01 | 2015-04-09 | E1023 Corporation | Magnetically enhanced energy storage system and methods |
US9263667B1 (en) | 2014-07-25 | 2016-02-16 | Spin Transfer Technologies, Inc. | Method for manufacturing MTJ memory device |
US9337412B2 (en) | 2014-09-22 | 2016-05-10 | Spin Transfer Technologies, Inc. | Magnetic tunnel junction structure for MRAM device |
US9728712B2 (en) | 2015-04-21 | 2017-08-08 | Spin Transfer Technologies, Inc. | Spin transfer torque structure for MRAM devices having a spin current injection capping layer |
US10468590B2 (en) | 2015-04-21 | 2019-11-05 | Spin Memory, Inc. | High annealing temperature perpendicular magnetic anisotropy structure for magnetic random access memory |
US9853206B2 (en) | 2015-06-16 | 2017-12-26 | Spin Transfer Technologies, Inc. | Precessional spin current structure for MRAM |
US9773974B2 (en) | 2015-07-30 | 2017-09-26 | Spin Transfer Technologies, Inc. | Polishing stop layer(s) for processing arrays of semiconductor elements |
US9614003B1 (en) * | 2015-10-21 | 2017-04-04 | Globalfoundries Inc. | Method of forming a memory device structure and memory device structure |
US9741926B1 (en) | 2016-01-28 | 2017-08-22 | Spin Transfer Technologies, Inc. | Memory cell having magnetic tunnel junction and thermal stability enhancement layer |
US10665777B2 (en) | 2017-02-28 | 2020-05-26 | Spin Memory, Inc. | Precessional spin current structure with non-magnetic insertion layer for MRAM |
US10672976B2 (en) | 2017-02-28 | 2020-06-02 | Spin Memory, Inc. | Precessional spin current structure with high in-plane magnetization for MRAM |
US10580827B1 (en) | 2018-11-16 | 2020-03-03 | Spin Memory, Inc. | Adjustable stabilizer/polarizer method for MRAM with enhanced stability and efficient switching |
Family Cites Families (24)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3260735B2 (ja) * | 1993-03-15 | 2002-02-25 | 株式会社東芝 | 磁気抵抗効果素子、磁気抵抗効果ヘッド、および磁気記録再生装置 |
US5587943A (en) * | 1995-02-13 | 1996-12-24 | Integrated Microtransducer Electronics Corporation | Nonvolatile magnetoresistive memory with fully closed flux operation |
DE19534856A1 (de) * | 1995-09-20 | 1997-03-27 | Forschungszentrum Juelich Gmbh | Digitale Speichereinrichtung für Lese- und Schreiboperationen sowie ein Verfahren zu deren Herstellung |
US5650958A (en) | 1996-03-18 | 1997-07-22 | International Business Machines Corporation | Magnetic tunnel junctions with controlled magnetic response |
JPH09306160A (ja) * | 1996-05-09 | 1997-11-28 | Oki Electric Ind Co Ltd | 磁気メモリ素子および情報記憶装置 |
US5804458A (en) | 1996-12-16 | 1998-09-08 | Motorola, Inc. | Method of fabricating spaced apart submicron magnetic memory cells |
JP4066477B2 (ja) * | 1997-10-09 | 2008-03-26 | ソニー株式会社 | 不揮発性ランダムアクセスメモリー装置 |
US6346741B1 (en) * | 1997-11-20 | 2002-02-12 | Advanced Technology Materials, Inc. | Compositions and structures for chemical mechanical polishing of FeRAM capacitors and method of fabricating FeRAM capacitors using same |
US6169686B1 (en) * | 1997-11-20 | 2001-01-02 | Hewlett-Packard Company | Solid-state memory with magnetic storage cells |
JP3148703B2 (ja) * | 1997-12-05 | 2001-03-26 | 株式会社日立製作所 | 磁気抵抗効果型ヘッドおよび磁気記録再生装置 |
US5956267A (en) | 1997-12-18 | 1999-09-21 | Honeywell Inc | Self-aligned wordline keeper and method of manufacture therefor |
DE19836567C2 (de) * | 1998-08-12 | 2000-12-07 | Siemens Ag | Speicherzellenanordnung mit Speicherelementen mit magnetoresistivem Effekt und Verfahren zu deren Herstellung |
US5940319A (en) | 1998-08-31 | 1999-08-17 | Motorola, Inc. | Magnetic random access memory and fabricating method thereof |
US6185079B1 (en) * | 1998-11-09 | 2001-02-06 | International Business Machines Corporation | Disk drive with thermal asperity reduction circuitry using a magnetic tunnel junction sensor |
JP2000150985A (ja) * | 1999-01-01 | 2000-05-30 | Nec Corp | 磁気抵抗効果素子 |
KR100408576B1 (ko) * | 1999-03-19 | 2003-12-03 | 인피니언 테크놀로지스 아게 | 기억 셀 어레이 및 그의 제조 방법 |
JP2000285668A (ja) | 1999-03-26 | 2000-10-13 | Univ Nagoya | 磁気メモリデバイス |
US6165803A (en) * | 1999-05-17 | 2000-12-26 | Motorola, Inc. | Magnetic random access memory and fabricating method thereof |
US6872993B1 (en) * | 1999-05-25 | 2005-03-29 | Micron Technology, Inc. | Thin film memory device having local and external magnetic shielding |
US6164803A (en) * | 1999-10-25 | 2000-12-26 | Attwood Corporation | Fold-up navigation light |
JP3854767B2 (ja) * | 1999-12-13 | 2006-12-06 | ローム株式会社 | 強磁性トンネル接合素子を用いた装置、およびその製造方法 |
JP3877490B2 (ja) * | 2000-03-28 | 2007-02-07 | 株式会社東芝 | 磁気素子およびその製造方法 |
DE10043947A1 (de) * | 2000-09-06 | 2002-04-04 | Infineon Technologies Ag | Integrierte Schaltungsanordnung |
US6677631B1 (en) * | 2002-08-27 | 2004-01-13 | Micron Technology, Inc. | MRAM memory elements and method for manufacture of MRAM memory elements |
-
2001
- 2001-03-15 US US09/805,916 patent/US6653154B2/en not_active Expired - Lifetime
-
2002
- 2002-03-12 EP EP02728437.1A patent/EP1368830B1/en not_active Expired - Lifetime
- 2002-03-12 AU AU2002258488A patent/AU2002258488A1/en not_active Abandoned
- 2002-03-12 KR KR1020027016306A patent/KR100605637B1/ko active IP Right Grant
- 2002-03-12 JP JP2002574699A patent/JP4589603B2/ja not_active Expired - Lifetime
- 2002-03-12 DE DE10291412.5T patent/DE10291412B4/de not_active Expired - Lifetime
- 2002-03-12 WO PCT/US2002/007284 patent/WO2002075782A2/en active Search and Examination
-
2003
- 2003-04-08 US US10/408,450 patent/US6689624B2/en not_active Expired - Lifetime
- 2003-04-09 US US10/409,145 patent/US6765250B2/en not_active Expired - Lifetime
-
2008
- 2008-11-27 JP JP2008302810A patent/JP5032449B2/ja not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
WO2002075782A3 (en) | 2003-06-05 |
JP2009088544A (ja) | 2009-04-23 |
US6689624B2 (en) | 2004-02-10 |
EP1368830A2 (en) | 2003-12-10 |
DE10291412T5 (de) | 2004-04-22 |
US6765250B2 (en) | 2004-07-20 |
JP4589603B2 (ja) | 2010-12-01 |
WO2002075782A2 (en) | 2002-09-26 |
US20030215961A1 (en) | 2003-11-20 |
US20030207471A1 (en) | 2003-11-06 |
KR20030014257A (ko) | 2003-02-15 |
EP1368830B1 (en) | 2019-08-28 |
US20020132375A1 (en) | 2002-09-19 |
DE10291412B4 (de) | 2019-08-29 |
JP2004519859A (ja) | 2004-07-02 |
KR100605637B1 (ko) | 2006-07-28 |
AU2002258488A1 (en) | 2002-10-03 |
US6653154B2 (en) | 2003-11-25 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5032449B2 (ja) | Mramデバイス | |
US6358756B1 (en) | Self-aligned, magnetoresistive random-access memory (MRAM) structure utilizing a spacer containment scheme | |
US7285811B2 (en) | MRAM device for preventing electrical shorts during fabrication | |
US7402879B2 (en) | Layered magnetic structures having improved surface planarity for bit material deposition | |
US7634851B2 (en) | Method of forming a magnetic random access memory element | |
US6927466B2 (en) | Magnetoresistive memory or sensor devices having improved switching properties and method of fabrication | |
US6780652B2 (en) | Self-aligned MRAM contact and method of fabrication | |
US6551852B2 (en) | Method of forming a recessed magnetic storage element | |
US6952360B2 (en) | Device with layer edges separated through mechanical spacing |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20111028 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20111101 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20120201 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20120221 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20120521 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20120608 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20120628 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 5032449 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20150706 Year of fee payment: 3 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
EXPY | Cancellation because of completion of term |