JP5002849B2 - Signal processor, game machine - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a signal processing system, which can easily perform the occurrence of freeze due to a failure of a display image with a simple configuration, or the like. <P>SOLUTION: A graphics logic 6 of the signal processing system includes: an instruction interpreting part 20 which interprets an instruction issued by a host CPU 10; an image decoding part 22 which performs decoding processing; a VRAM 23 wherein a composite image is stored; and a display circuit 24 which outputs a display image formed by performing prescribed image processing on the composite image to display the display image on an LCD 1. The display image outputted from the display circuit is returned to the VRAM 23 and the host CPU 10 detects the returned display image, consequently, the host CPU 10 can confirm the operation of the display circuit 24. <P>COPYRIGHT: (C)2011,JPO&amp;INPIT

Description

  The present invention relates to a signal processing apparatus and a gaming machine that can efficiently and comprehensively control image development, sound reproduction, operation of an accessory, lighting of a light emitting element, and the like particularly in an interactive gaming machine, a gaming machine, and the like. .

  In the field of gaming machines such as pachinko machines, the control unit is configured by a large number of LSIs so that they can be enjoyed while enhancing image effects and sound effects. Generally, LSIs that perform image processing and LSIs that perform sound processing. Are separately prepared, and the system configuration is such that a cooperative operation is performed by sending a predetermined command to these LSIs from the host CPU. In particular, image information has a large amount of information, and an image processing system that is devised based on an image compression technique and its expansion (decompression) technique is described in Patent Documents 1 and 2, for example.

  On the other hand, Patent Document 3 proposes a system that increases the use efficiency of the host CPU by linking the image LSI and the sound LSI while separately holding the image LSI and the sound LSI in order to reproduce the image and sound in cooperation. . Further, cited document 4 describes an invention in which compressed data is decompressed using a first decompression unit and a second decompression unit based on the format of video data.

Japanese Patent No. 3970291 JP 2009-294990 A JP 2007-156519 A JP 2006-121338 A

  However, in a recent game machine, the game effect is not limited to images and sounds, but in the so-called actor motor control such as opening / closing an attacker or changing the movement of a character object, the player already exists on the board. It is controlled to change the way it moves or to appear suddenly.

  Even in such a system, individual LSIs are usually used to control images, sound, motors, and LEDs for commands from the host CPU, and each LSI is individually controlled depending on the commands from the host CPU. Therefore, there is a problem that the burden on the program of the host CPU becomes large in order to perform such cooperative operation.

  On the other hand, in recent years, there are cases where the image information includes a transparent or translucent image, and a state in which a plurality of pieces of color information overlap in the same pixel region is displayed as graphics. Conventionally, in the decoding process in such a case, first, normal pixel decoding is performed, and after that, α decoding based on an α value indicating a transparent value is performed, and a plurality of decodings are performed based on the results of both decodings. The procedure of blending the images of was taken. However, this method takes time for processing, and there is a problem that even if the invention according to the cited document 4 is used, such an adverse effect cannot be removed.

  The present invention has been made in view of the above problems, and can efficiently and comprehensively control image development in interactive game machines, game machines, etc., and graphics data with transparent and translucent graphics processing. It is an object of the present invention to provide a signal processing device and a gaming machine that can process and display a game quickly.

  In order to solve such a problem, the invention according to claim 1 of the present invention is a signal processing device whose operation is controlled by an instruction of a host CPU, and is a graphics for controlling output of image data displayed on a display means. And the graphics logic includes instruction decoding means for decoding the instruction of the host CPU, and image decoding means for performing decoding processing based on the result of decoding the instruction in the instruction decoding section, The decoding means includes a plurality of pixel decoders that perform decompression processing of the compressed pixel data as the decoding processing, and decompression processing of α data as an α value that indicates the transparent value of the compressed pixel data as the decoding processing. A plurality of α decoders, and monitoring of operation states of the pixel decoder and the α decoder and bus control as operation control are performed. A bus control means, wherein the bus control means is in an execution state in which a plurality of the pixel decoders and a plurality of α decoders are each performing the decoding process or in a standby state in which the decoding process is not being performed. And when the decoding result of the instruction is acquired from the instruction decoding unit, the pixel decoder and the α decoder in the standby state perform the decoding process based on the monitoring result. .

  The invention described in claim 2 is characterized in that, in addition to the configuration described in claim 1, the pixel decoder and the α decoder are configured to perform the decoding process in parallel operation.

  According to a third aspect of the present invention, in addition to the configuration according to the first or second aspect, the bus includes a buffer unit that temporarily stores data before the decoding processing in the pixel decoder and the α decoder. The control unit manages a correspondence relationship between each of the pixel decoders and each of the α decoders, and stores data stored in the buffer unit in the pixel decoder or the α decoder in the correspondence relationship. And

  According to a fourth aspect of the present invention, there is provided a gaming machine comprising the signal processing device according to any one of the first to third aspects.

  According to the first aspect of the present invention, the bus control means monitors whether the plurality of pixel decoders and the plurality of α decoders are in the execution state or the standby state, and based on the monitoring result, the pixel decoder and α in the standby state By causing the decoder to perform decoding processing, it is possible to perform normal pixel decoding and α decoding using α values without delay in an image including transparent and translucent pixels. As a result, image development and the like can be efficiently and comprehensively controlled in interactive gaming machines, game machines, etc., and graphics data with transparent and translucent graphics processing can be quickly processed and displayed. In addition, image development and the like can be efficiently and comprehensively controlled in interactive game machines and game machines.

  According to the second aspect of the present invention, since the pixel decoder and the α decoder are configured to be able to perform decoding processing in parallel operation, it is necessary to wait for completion of the decoding processing in the pixel decoder before decoding the α decoder. Thus, graphics data with transparent and translucent graphics processing can be quickly processed and displayed.

  According to the third aspect of the present invention, the buffer unit temporarily stores the data before performing the decoding process in the pixel decoder and the α decoder, and the bus control means includes the pixel decoder and each of the pixel decoders. By managing the correspondence relationship with the α decoder and supplying the data stored in the buffer unit to the pixel decoder or α decoder in the correspondence relationship according to the situation, the data acquisition timing and the decoding processing timing The data can be prepared before decoding.

1 is a block diagram schematically showing an internal configuration of a graphics logic of the present invention and showing a relationship with an external memory according to an embodiment of the present invention. It is a block diagram explaining the detail of the decoder part of the logic for graphics of this invention. It is a flowchart which shows the decoding operation | movement of this invention. It is the figure which compared the sector structure and arrangement | positioning state of audio | voice data of the NAND memory based on this invention with the prior art example. It is a flowchart which illustrates the conventional decoding operation | movement. (A) Timing chart of conventional pixel decoding processing and α decoding processing, (b) Time chart of pixel decoding processing and α decoding processing of this embodiment.

  1 to 4 and 6 show an embodiment of the present invention, and FIGS. 5 and 6 show conventional examples. Hereinafter, an embodiment of the present invention will be described with reference to these drawings.

  FIG. 1 is an overall block diagram showing a signal processing apparatus and a signal processing system according to an embodiment of the present invention. This signal processing system 1A appeals visually and audibly to the LCD 1 as a “display means” disposed on the board surface of the gaming machine and to output devices (not shown) such as speakers, motors, and LEDs. And an integrated LSI 5 as a “signal processing device” for controlling the operation of the peripheral device for enhancing playability.

  The LCD 1 is connected to a later-described graphics logic 6 to display various graphics. A speaker (not shown) is connected to a later-described audio logic 17 and outputs various audio.

  The integrated LSI 5 is configured as one LSI chip, and in this embodiment includes a graphics logic 6, audio logic 7, motor control logic 8, and LED control logic 9.

  The CPU 10 is a processor corresponding to the upper CPU of the integrated LSI 5, generates a command group 11 (command list) to be executed by the integrated LSI 5, and controls the operation of the integrated LSI 5. In this embodiment, the CPU 10 is provided separately from the integrated LSI 5, but the CPU 10 may be built in the integrated LSI 5.

  The CPU 10 has a function of issuing a display list 12 in which a series of instructions to be executed by the integrated LSI 5 are described in a substantially time-series manner. In the display list 12, the image processing procedure is defined by a series of instructions described in a substantially chronological order, and in terms of image units, the transfer procedure of the material necessary for drawing one frame of the image is defined. Yes. Here, the material refers to a unit of a predetermined size defined in advance in image data stored in a CGROM (actually, a NOR or NAND flash memory) that is an external memory. . Furthermore, the display list 12 of the present embodiment is characterized in that it also includes a motor control transfer procedure and an LED lighting control procedure.

  In addition to the instruction decoding unit 20 and the audio decoding unit 21 related to the linkage between image output and audio reproduction, the graphics logic 6 includes an image decoding unit 22 as an “image decoding unit”, a VRAM 23, A display circuit 24 is provided.

  The instruction decoding unit 20 decodes the display list 12, transmits the decoding result of the graphic list (not shown) among the decoding results to the image decoding unit 22, and receives the decoding result of the audio list (not shown). It transmits to the audio decoding unit 21.

  The image decoding unit 22 performs a decoding process based on a result of decoding a graphic list (not shown) in the instruction decoding unit 20. Details of the decoding process will be described later. The VRAM 23 stores image data of a composite image obtained as a result of the decoding process of the image decoding unit 22. The display circuit 24 reads the synthesized image data and supplies it to the LCD 1.

The integrated LSI 5 is connected to the external memory 25. The external memory 25 includes a plurality of NOR memories 26 ₁ to 26 _n (n> 1), NAMD memories 27 ₁ to 27 _m (m> 1), and an expansion RAM controller 28 as an interface circuit. NOR memory ₂₆ 1, ··· ₂₆ n, NAND memory ₂₇ 1, various data in · · · 27 _m (image data, audio data, LED lighting data, the motor driving data, etc.) is stored.

The NOR memories 26 ₁ ,... 26 _n are connected to the data bus 41 of the data path, and the NAND memories 27 ₁ ,... 27 _m are connected to the command bus 42 of the command path. For the sake of simplicity, the following description will be expressed as a NOR memory 26 and a NAND memory 27 unless otherwise required.

  FIG. 2 is a block diagram illustrating details of the decoder portion of the graphics logic 6, and FIG. 3 is a flowchart showing the decoding operation. FIG. 5 and FIG. 6 are a flowchart illustrating the conventional decoding operation in comparison with the decoder operation of this embodiment, and a timing chart showing the timing of start and completion of decoding.

  The image decoding unit 22 includes a plurality (two in the present embodiment) of pixel decoders 30 and 30, a plurality (two in the present embodiment) of α decoders 31 and 31, and a bus control unit as “bus control means”. 32 and a buffer unit 33. The number of pixel decoders 30 and α decoders 31 may be more or less than two.

  Each pixel decoder 30 performs decompression processing of the compressed pixel data as decoding processing. Each of the α decoders 31 performs a decompression process of the α data as an α value indicating the transparency value of the compressed pixel data as a decoding process. The bus control unit 32 performs bus control as monitoring of the operation state of the pixel decoders 30 and 30 and the α decoders 31 and 31 and operation control. The bus control unit 32 detects the empty state of the buffer 33 in the image decoding unit 22, and when there is a decode instruction from the instruction decoding unit 20 and there is an empty buffer, the compressed data is read from the external memory 25. The data before being acquired and supplied to the pixel decoders 30 and 30 and the α decoders 31 and 31 are stored in the buffer unit 33. At this time, the bus control unit 32 performs independent control without depending on the CPU 10.

  In the present embodiment, the buffer unit 33 has the same number of distinguished data areas 331, 332, 333, and 334 as the number of decodes of the image decoding unit 22. Note that the correspondence between the pixel decoders 30 and 30 and the α value decoders 31 and 31 (which data area stores the data stored in which decoder 30, 30, 31, 31) is determined by the bus control unit 32. Manage and control. Therefore, the number of the data areas 331, 332, 333, and 334 may be larger or smaller than the total number of the pixel decoders 30 and 30 and the α decoders 31 and 31 if there is a quantity relationship that can be managed by the bus control unit 32. Good. At the same time, after one of these decoders 30, 30, 31, 31 is in an empty state, that is, after it has been changed from the operating state to the standby state, the decoder that has become empty (for example, one pixel decoder 30). On the other hand, the bus control unit 32 takes in the compressed data to be newly decoded from the NAND memory 27 or the NOR memory 26 which is the external memory 25 and stores it. Meanwhile, the CPU 10 that processes the drawing command only needs to be secured for a drawing command that does not depend on the data transfer operation between the image decoding unit 22 and the buffer unit 33. The instruction decoding unit 20 receives a drawing instruction from the CPU 10 and refers to a decompressed (decompressed) area table (not shown) while referring to the address of the compressed data stored in the NAND memory 27 and the decompressed data. Check the deployment size that defines the size. The development area table serves as an index for preventing inconvenience in the development of the file data by collectively reading and writing in the case of large file data. Transfer control of file data from the NAND memory 27 is performed via the bus control unit 32.

  The bus control unit 32 detects whether each of the two pixel decoders 30 and 30 and the two α decoders 31 and 31 is in an operating state or in a standby state. The decision is made to decide whether or not to operate the decoder, and the operation state of each decoder 30, 30, 31, 31 is controlled. Here, the “operation state” means that each of the decoders 30, 30, 31, and 31 of the image decoding unit 22 is in a “standby state” in which decoding processing is not performed, or is being decompressed by decoding processing. This is status information indicating whether the state is “execution state”.

  The control procedure of the bus control unit 32 will be specifically described. The bus control unit 32 monitors whether the plurality of pixel decoders 30 and 30 and the plurality of α decoders 31 and 31 are in an execution state or a standby state, respectively. When the bus control unit 32 acquires the result of decoding the instruction from the instruction decoding unit 20, a standby pixel decoder (for example, one pixel decoder 30) and / or a standby α decoder (for example, based on the monitoring result) For example, one α decoder 31) performs decoding processing.

  FIG. 3 is a flowchart showing the decoding process of the pixel decoder 30 and the decoding process of the α decoder 31 of the present embodiment. The decoding process procedure will be described with reference to FIG.

  Prior to the decoding process of the present embodiment, instructions are formed in the CPU 10 and instructions are supplied from the CPU 10 to the instruction decoding unit 20 of the graphics logic 6. The CPU 10 also controls peripheral devices other than the graphics logic 6 connected to the CPU bus 34. The bus control unit 32 reads compressed data for one frame.

  The instruction decoding unit 20 and the bus control unit 32 operate independently of the CPU 10 until the next frame development information is confirmed from the CPU 10, and processing such as drawing command reception and preprocessing is independent of the decoder. This is a configuration in which a state that can be decoded in advance is constructed in advance. The decoding process is performed when the operations of the empty pixel decoders 30 and 30 and the empty α decoders 31 and 31 become possible.

  When the instruction decoding unit 20 decodes the instruction of the CPU 10, the pixel decoding process by the pixel decoder 30 and the α decoding process by the α decoder 31 are started (steps S11 and S21). The pixel decoder 30 acquires one pixel data from the compressed data recorded in the external memory 25 (step S12), and performs a pixel decoding process. When the pixel decoding process for each pixel is completed (“Yes” in step S13), the process returns to step S11 (step S14), and the same procedure is repeated for other pixel data.

  On the other hand, the α decoder 31 acquires one α data (image or pixel α value data) from the compressed data or the like recorded in the external memory (step S22), and performs α decoding processing using the α value. When α decoding is completed (“Yes” in step S23), the process returns to step S21 to repeat the same procedure for other α data.

  FIG. 5 shows, as a reference example, a flowchart showing a procedure of conventional pixel decoding processing and α decoding processing. In the conventional examples shown here, first, the blending operation of the conventional pixel decoding and α decoding is confirmed. Here, α blending is a method of blending two pieces of image data using an α value as a value indicating transparency in order to display an image including transparent or translucent pixels. Since the image data is compressed (encoded) by an appropriate compression method, after the decoding is started (step S31), the compressed data is acquired (step S32) and decompressed (decoded). After completion (“Yes” in step S33), α decoding is completed (“Yes” in step S34), and the process is repeated (step S35).

  In the conventional α blending, (1) the upper CPU constantly checks the completion of decoding, and there is a problem that the load on the CPU increases. Further, (2) since the operation of the pixel decoder and the operation of the α decoder are integrated in time series, the next decoding process is started only after the operation of the continuous pixel decoder and the α decoder is completed ( Step S33, Step S34, Step S35).

  On the other hand, the image decoding unit 22 of the present embodiment shown in FIGS. 1 and 2 includes a plurality of pixel decoders 30 for pixel expansion and the same plurality of α decoders 31 for α expansion.

  FIG. 6 (a) shows a conventional pixel decoding process and α decoding process, and FIG. 6 (b) shows a time chart of the pixel decoding process and α decoding process of this embodiment. If the flowchart of this embodiment shown in FIG. 3 is compared with the conventional flowchart shown in FIG. 5, the determination of data acquisition and decoder completion confirmation has the same function. However, as shown in FIG. 5, conventionally, the pixel decoding process and the α decoding process can be controlled only in a serial relationship. Since the pixel and α decoding process is completed and the CPU 10 needs to check the state, the CPU 10 is burdened and the timing span 35 of the decoding process is long ((a in FIG. 6). )reference). On the other hand, in this embodiment, the pixel decoder 30 and the α decoder 31 can be individually operated in parallel in parallel. Conventionally, code and α decoding must be performed in order on a pixel-by-frame basis, but in this embodiment, processing independent of the frame can also be performed. That is, the pixel decoder 30 and the α decoder 31 can process image data of different frames at the same timing. Further, the processing of the pixel decoder 30 and the α decoder 31 is performed above by the control of the bus control unit 32, and the procedure for checking the state by the CPU 10 existing in the conventional procedure (see FIG. 6A). Do not do. Therefore, the timing span 36 can be shortened compared to the timing span 35 of the conventional example (see FIG. 6B), and the load on the CPU 10 can be reduced.

  In addition, the said embodiment is an illustration of this invention, and it cannot be overemphasized that this invention is not meant to be limited only to the said embodiment.

1A Signal processing system 1 LCD
2 Speaker 3 Motor 4 LED
5 Integrated LSI (signal processing equipment)
6 Graphics logic 7 Audio logic 8 Motor control logic 9 LED control logic 10 CPU (upper CPU)
11 instruction group 12 display list 20 instruction decoding unit (instruction decoding means)
22 Image decoding unit (audio decoding means)
25 External memory 26 NOR memory 27 NAND memory 30, 30 Pixel decoder 31, 31 α decoder 32 Bus control unit (bus control means)
33 buffer unit 38 _1, 38 ₂ alpha data 39 _1, 39 ₂ pixel data 331, 332, 333 and 334 the data area

Claims (4)

A signal processing device whose operation is controlled by a command from a host CPU,
A graphics logic for controlling the output of image data displayed on the display means;
The graphics logic includes instruction decoding means for decoding the instruction of the upper CPU, and image decoding means for decoding based on the result of decoding the instruction in the instruction decoding section,
The image decoding means includes
A plurality of pixel decoders that perform decompression processing of compressed pixel data as the decoding processing;
A plurality of α decoders that perform decompression processing of α data as compressed α values indicating transparency values of pixel data as the decoding processing;
Bus control means for performing bus control as monitoring and operation control of the pixel decoder and the α decoder,
The bus control means monitors whether each of the plurality of pixel decoders and the plurality of α decoders is in an execution state in which the decoding process is being performed or in a standby state in which the decoding process is not being performed. When the decoding result of the instruction is acquired from the unit, the signal processing apparatus causes the pixel decoder and the α decoder in the standby state to perform the decoding process based on the monitoring result.   The signal processing apparatus according to claim 1, wherein the pixel decoder and the α decoder are configured to be able to perform the decoding process in a parallel operation. A buffer unit for temporarily storing data before performing the decoding process in the pixel decoder and the α decoder;
The bus control means manages a correspondence relationship between each pixel decoder and each α decoder, and stores data stored in the buffer unit in the pixel decoder or the α decoder in the correspondence relationship. The signal processing apparatus according to claim 1 or 2.   A gaming machine comprising the signal processing device according to any one of claims 1 to 3.

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