JP5756990B2 - Communication system and communication method - Google Patents

Description

  The present invention relates to a technique for ensuring connectivity in a chip, various devices, various nodes, and the like.

  In order to perform various processes in various fields such as image and sound processing, machine operation control, and communication, various devices and nodes such as an integrated circuit such as an IC chip are used. Conventionally, a technique for connecting a plurality of chips via a bus or various interfaces is known (for example, see Patent Document 1). In addition, a technology for ensuring connectivity between connected chips is known (for example, non-patent literature) that communicates information between connected chips and enables memory resources to be used between chips. 1). On the other hand, when nodes such as a plurality of chips and computers are connected, it may be necessary to share a specific resource provided in the specific node, such as a system memory, among all the nodes. Conventionally, in the interconnection between a plurality of nodes (computers), a processor is provided in each node, and the memory interface can be shared by the plurality of processors, and the plurality of processors are connected to a specific node via an external bus. There is known a technique for transferring a packet to a system memory provided in (see, for example, Patent Document 2).

US Patent 6910092 JP 2001-344222 A (paragraphs [0014], [FIG. 1], etc.). C2CTM Chip to Chip LinkTM Inter-Chip Connectivity IP (URL: http://www.arteris.com/c2c_chip-to-chip_for_DRAM_memory_sharing)

  However, in Patent Document 1 and Non-Patent Document 1, there is a problem that even if chips are connected to each other, it is difficult to flexibly adapt to changes in the state or connection state between chips. In addition, Patent Document 1 and Non-Patent Document 1 have a problem that it is difficult to apply to connection modes other than the connection between chips.

  On the other hand, in Patent Document 2, the system memory provided in one node can be shared by processors of a plurality of nodes. However, in order to perform communication between nodes, other than the network used for communication between nodes. In addition, an external bus for sharing the system memory must be provided between the nodes, and there is a problem that hardware resources for connecting the nodes increase. On the other hand, in the configuration of Patent Document 2, it is conceivable to use a network used for communication between nodes instead of an external bus for system memory sharing. There occurs a situation in which data transmitted and received between the two devices collide with each other in the network, and latency of data transmitted and received between the processor and the system memory is likely to occur. The generation of this latency has a problem that it leads to a delay in processing of the entire node, and thus the entire system.

  The present invention has been made in view of the above problems, and ensures good connectivity among a plurality of configuration requirements between chips, between devices in a chip, between various devices other than chips, between various nodes, and the like. It is an object of the present invention to provide a communication system that can be connected to each other and that can suppress the occurrence of latency in a specific resource while saving hardware resources and can increase the processing speed of the system.

In order to achieve the above object, the invention according to claim 1 is a communication system that enables communication between a plurality of devices, and in the plurality of devices, at least intervenes in communication between the devices. One central device and a plurality of terminal devices, each of which is communicably connected to at least one central device, the central device comprising a main storage device used for data processing and / or recording, and the main device A path selection unit that is interposed between the storage device and the terminal device and selects the transmission path of the data in order to share the data among a plurality of devices, and is configured to be communicable with the path selection unit A plurality of first paths that form a data path between each of the path selection means and the main storage device, and can communicate with the path selection means separately from the first path. Setting Provided, and a second path forming a path of data between the terminal device, the main storage device is shared in each of the terminal devices, each of the first path, each of said terminal devices provided, is constituted by a data bus to form a path of the data between the terminal device and the main storage device, the second path is formed into an annular shape so as to circulate the data can be The path selection means is configured to transmit data addressed to the main storage device supplied from one terminal device to the first route between the terminal device and the main storage device. together to perform transmission and reception of the data, and transmit the data of another addressed the terminal device supplied from a said terminal equipment to said second path transmission of the data between a plurality of said terminal devices Characterized in that to perform the signal.

The invention according to claim 2 is a communication system that enables communication between a plurality of devices, wherein each of the plurality of devices includes at least one central device interposed in the communication between the devices. A plurality of terminal devices communicably connected to at least one of the central devices, wherein the central device is a main storage device used for processing and / or recording data to be calculated in an arithmetic device; and the main memory A path selection unit that is interposed between a device and the terminal device and that selects the data transmission path in order to share the data among a plurality of devices, and is configured to be communicable with the path selection unit. A plurality of first paths that form a data path between each of the path selection means and the main storage device, and can communicate with the path selection means separately from the first path And a second path that forms a data path between the terminal devices, and each of the first paths is provided for each of the terminal devices, and the main storage device. The second path is constituted by a data bus formed in a ring shape so that the data can be circulated, and the second path includes: The arithmetic device used for various operations of the data in the central device and an auxiliary storage device in which the data supplied to the main storage device are recorded are connected, and the route selection means is connected to the one terminal device. The supplied data addressed to the main storage device is transmitted to the first path to transmit / receive the data between the terminal device and the main storage device, and the one terminal device The data of the supplied other said terminal equipment addressed and transmitted to the second path to perform the transmission and reception of the data between a plurality of said terminal devices, and the computing device or the main from the auxiliary storage device The data addressed to the storage device is transmitted to the first route, and the data addressed to the arithmetic device or the auxiliary storage device is transmitted from the main storage device to the second route to transmit the data to the second route. The processing of the data in is performed.

According to a third aspect of the present invention, in addition to the configuration of the first or second aspect, the IC chip as the device is provided in a gaming machine.

The invention according to claim 4 includes at least one central device interposed in communication between a plurality of devices, and a plurality of terminal devices each connected so as to be able to communicate with at least one of the central devices, The central device is interposed between the main storage device used for data processing and / or recording, the main storage device and the terminal device, and the data transmission path for sharing the data among a plurality of devices. And a plurality of first paths that are communicable with the path selection means and that form a data path between the path selection means and the main storage device. Separately from the first route, a communication method in a communication system comprising a second route which is provided so as to be communicable with the route selection means and forms a data route between the terminal devices. The The main memory is shared in each of the terminal devices, each of said first path, it said provided for each terminal device, to form a path of the data between the terminal device and the main memory The second path is configured by a data bus that is formed in a ring shape so that the data can be circulated, and the path selection unit includes the main path supplied from one terminal device. the data storage device addressed by sending the first path causes perform transmission and reception of the data between the main storage device and the terminal device, other said terminal equipment supplied from a said terminal device the data addressed and transmitted to the second path, characterized in that it comprises the steps to perform the transmission and reception of the data between a plurality of said terminal devices.

According to the first , second and fourth aspects of the present invention, the route selection means provided in the central device uses the data addressed to the main storage device supplied from one terminal device as the first route. In order to transmit data addressed to other terminal devices supplied from one terminal device to the second route, the first route is used as a dedicated line to communicate with the main storage device, and the second route The path can be used as a general-purpose communication line used for transmission / reception of various data between devices. Therefore, without providing a dedicated line separate from the general-purpose communication line from each terminal device to the main storage device, it is possible to suppress delay in data transmission and reception between the terminal device and the main storage device, and Communication can be performed smoothly. As a result, it is possible to secure and connect with a plurality of configuration requirements, and it is possible to increase the processing speed of the system by suppressing the occurrence of latency in specific resources while saving hardware resources. .

According to the first, second, and fourth aspects of the invention, the first route is formed as a dedicated line between the route selection means and the specific internal resource, and the second route is an annular shape. Since it is formed as a communication line, a delay in communication between the terminal device and the main storage device can be surely suppressed, and data can be reliably transmitted and received while circulating the annular communication line between the devices.

According to the invention described in claim 1 , claim 2, or claim 4 , the first route is provided between the specific internal resource and each route selection means, so that there are a plurality of terminal devices. Even in this case, a situation in which the use of the same first route is competed by a plurality of terminal devices is suppressed, and a delay in communication between the terminal device and the main storage device can be reliably suppressed.

According to the inventions of claim 1 , claim 2, and claim 4 , in a system in which the main storage device is shared by a plurality of devices by increasing the speed of data transmission / reception performed by the main storage device, Processing delay of the entire system can be suppressed.

According to the third aspect of the present invention, it is possible to increase the processing speed of the system by suppressing the occurrence of latency in a specific resource while saving hardware resources among a plurality of communicable IC chips. Can do.

According to the third aspect of the present invention, in a plurality of IC chips that are provided in a gaming machine and can communicate with each other, the generation of latency in a specific resource is suppressed while saving hardware resources, and the processing of the system is reduced. The speed can be increased.

It is a figure which shows the whole structure of the communication system which concerns on Embodiment 1 of this invention. It is a conceptual diagram which shows the outline | summary of the process in the direction instruction | indication part of the communication system which concerns on the embodiment. It is a flowchart which shows the process sequence of the communication system which concerns on the embodiment. It is a conceptual diagram at the time of applying the communication system concerning the embodiment to a gaming machine. It is a conceptual diagram which shows the outline | summary of the process in the direction instruction | indication part of the communication system which concerns on Embodiment 2 of this invention.

Embodiment 1 of the Invention
1 to 4 show a first embodiment of the present invention.

  As shown in FIG. 1, the communication system 1A according to the first embodiment is used to connect a plurality of “devices” such as chips.

[Basic configuration]
FIG. 1 shows a basic configuration of a communication system 1A according to the first embodiment. FIG. 4 is a conceptual diagram when the communication system 1A is applied to a gaming machine.

  The communication system 1A of the first embodiment is configured by connecting a plurality of chips with an external bus.

The center chip 2 as “device” and “central device”, and m pieces (m>) as “device” and “terminal device”, which constitute the communication system 1A of the first embodiment shown in FIG. 1) Chip A3 ₁ , Chip B3 ₂ ,... Chip m3 _m is an IC chip used for image processing, sound processing, operation control of an accessory, etc., in a game machine such as a pachinko machine or an entertainment device, respectively. It is. The center chip 2, the chip A3 ₁ , the chip B3 ₂ ,..., The chip m3 _m are a display control of a moving image displayed on the display 101 such as an LCD disposed on the board surface of the gaming machine 100, and the main body of the gaming machine 100 Are used for lighting control of the lighting device 102 such as an LED, output control of sound generated from the speaker 103, operation control of the motor 105 for operating the accessory 104, and the like. Chip A3 ₁ , chip B3 ₂ ,... Chip m3 _m may each be specialized for moving picture display control, lighting control, audio output control, etc., or moving picture display and lighting equipment as the lighting or the like 102, to a plurality of control target may be one in which one chip for example, a chip A3 ₁ controls a plurality of chips for example, a chip A3 _1, chip B3 ₂ is one of the controlled object for example videos Display control may be performed.

As shown in FIG. 1, in the communication system 1A of the first embodiment, a center chip 2, a chip A3 ₁ , a chip B3 ₂ ... Chip m3 _m are provided. Each chip A3 ₁ a center chip 2, chip _B3 2, the ... chip m3 _m, are connected by an external bus _{4 1, 4 2, ··· 4} m. The external bus _{4 1,} 4 2, ... _{4 m,} each chip A3 ₁ a center chip 2, chip _B3 2, the data bus used to exchange data between the ... chip m3 _m is there.

  As shown in FIG. 1, the center chip 2 includes at least one CPU 5 and is connected to a ring bus 11 together with a ROM 6, an EEPROM 7, and the like.

The center chip 2 is provided with a DRAM 8 as a “specific internal resource”. The DRAM 8 constitutes a “main storage device” of the center chip 2 and is used as a temporary storage area during data processing. In the first embodiment, the DRAM 8 performs processing by the CPU 5 of the center chip 2 itself and processing by a CPU (not shown) provided in each of the chips A3 ₁ , chip B3 ₂ ,..., Chip m3 _m . Shared.

The center chip 2 is provided with a plurality of direction instruction sections 9 ₁ , 9 ₂ ,... 9 _m as “ route selection means”. The direction indicator unit _{9 1,} 9 2, ... _{9 m,} the chip A3 _1, chip _B3 2, provided the same number i.e. the m and ... chip m3 _m. The direction indicator unit _{9 1, 9 2, ··· 9} m is, DRAM 8 and the chip A3 _1, chip _B3 2, interposed between the ... chip m3 _m, chip A3 _1, chip _B3 2, · · Chip m3 A transmission path for data transmitted / received between _m and the center chip 2 or data transmitted / received inside the center chip 2 is selected.

Direction indicator unit _{9 1,} 9 2, and · · · _{9 m} and DRAM 8, respectively, 1 direct bus ₁₀ as a "first _path", 10 2 are connected by · · · 10 _m. The direct bus _{10 1,} 10 2, · · · 10 _m is a chip internal bus of the center chip 2, and connected in the direction indicating section _{9 1,} 9 2, and · · · _{9 m} and DRAM8 directly each direction instruction section _{9 1,} 9 2, constitute the data bus as a dedicated line between the · · · _{9 m} and DRAM 8.

Inside the center chip 2, a ring bus 11 as a “second route” is provided separately from the direct buses 10 ₁ , 10 ₂ ,... 10 _m . The ring bus 11 is a chip internal bus of the center chip 2 formed in an annular shape, and constitutes a data bus that forms a data circulation path. In order to circulate data within the ring bus 11, any configuration may be used, for example, a known token may be circulated within the ring bus 11.

As described above, the CPU 5, ROM 6, EEPROM 7, etc. of the center chip 2 are connected to the ring bus 11. Further, as described below, the ring bus 11 the chip A3 ₁ via the external bus _{4 1, 4 2, ··· 4} m, the chip _B3 2, is also connected to ... chip m3 _m. The ring bus 11 forms a circulation path for data and the like, and exchanges data and the like between the chips A3 ₁ , chip B3 ₂ ,..., Chips m3 _m, and the CPU 5, ROM 6, EEPROM 7, etc. of the center chip 2. A general-purpose line for transmitting and receiving data and the like between them is formed.

Ring bus 11 and each of the external bus _{4 1,} 4 2, and · · · _{4 m,} connecting portions _{12 1,} 12 2 are connected in · · · 12 _m. The connection units 12 ₁ , 12 ₂ ,... 12 _m constitute communication interfaces with the external buses 4 ₁ , 4 ₂ ,... 4 _m , respectively, and the external buses 4 ₁ , 4 ₂ ,. Data transmission / reception between _m and the chip internal bus of the center chip 2 such as the ring bus 11 is realized.

Each of the connecting portions _{12 1,} 12 2, · · · 12 _m and each of the direction indicating section _{9 1,} 9 2, and · · · _{9 m,} contact bus _{13 1,} 13 2, connected by · · · 13 _m Has been. The communication buses 13 ₁ , 13 ₂ ,... 13 _m are chip internal buses of the center chip 2 and constitute a data bus.

The chip A3 ₁ , the chip B3 ₂ ,..., The chip m3 _m include at least one CPU (not shown) and a chip internal bus (not shown), and each performs processing such as data. As described above, the chip A3 _1, chip _B3 2, · · · chip m3 _m is connected to an external bus _{4 1,} 4 2, DRAM 8 of the center chip 2 via · · · _{4 m} or the like, share the DRAM 8 . Chip A3 ₁ , chip B3 ₂ ,..., Chip m3 _m may have a main storage device such as a DRAM separately from DRAM 8.

[Outline of processing in direction indicator]
As described above, the direction instructing units 9 ₁ , 9 ₂ ,... 9 _m select a transmission path for data or the like. Specifically, each of the direction instruction units 9 ₁ , 9 ₂ ,... 9 _m selects a data transmission destination by a procedure as shown in the following (Method 1) (Method 2), for example.

(Method 1)
As shown in the conceptual diagram of FIG. 2, each chip A3 ₁ , chip B3 ₂ ,..., Chip m3 _m , CPU 5, ROM 6, EEPROM 7, DRAM 8, etc. of the center chip 2 are assigned unique addresses. ing.

Further, the data 31 transmitted and received by the CPU 5, ROM 6, EEPROM 7, DRAM 8, etc. of the center chip 2 and chips A3 ₁ , chip B3 ₂ ,..., Chip m3 _m are composed of a data body portion 32 and a header portion 33. . The header section 33 has a function of recording a destination address as address information. The data 31 may be divided for each predetermined data length for communication, such as a frame or a packet, or may be a series of data that is not divided. The header section 33 may also record address information of the transmission source device.

Each of the direction indicating units 9 ₁ , 9 ₂ ,... 9 _m has a reference table 21 illustrated in FIG. The connection portions _{12 1,} 12 2, · · · 12 _m is formed a branch of the data 31, the data 31 received, direction indicator unit _{9 1,} 9 2, designated by the · · · _{9 m} It has a configuration for transmitting in a direction (for example, a table similar to the reference table 21 or a configuration for determining a data transmission direction based on a collation result with the table). In FIG. 2, the reference table 21 in the direction indicating section 9 _1, but the state in which transmission direction is recorded relative to the direction indicating section 9 ₁ in the column "direction" is shown, the other direction in the column of the reference table of the indicator (e.g., direction instruction section 9 ₂ shown in FIG. ₂₎ (not shown in FIG. 2) for "direction", and the reference each direction instruction section (e.g., direction instruction section 9 ₂₎ The transmission direction is recorded.

Each of the direction indicating sections 9 ₁ , 9 ₂ ,... 9 _m reads the address information recorded in the header section 33 of the data 31 and collates the address information with the reference table 21 to check the transmission destination (DRAM 8 or The CPU 5, ROM 6, EEPROM 7, etc. of the center chip 2 connected to the ring bus 11, chip A 3 ₁ , chip B 3 ₂ ,... Chip m 3 _m ) are identified, and the transmission direction is determined. Then, the direction instructing units 9 ₁ , 9 ₂ ,... 9 _m transmit the data 31 in the transmission direction specified by the reference table 21.

Specifically, for example, transmitted from the chip A3 _1, direction indicator unit 9 ₁ receives the data 31 in which the address information is recorded in the "pqrs" to the header portion 33, matching the address information and the reference table 21 and, based on the designation of the first row 211 of the reference table 21, and transmits the data 31 to DRAM8 via a direct bus 10 _1.

Further, for example, transmitted from the chip A3 _1, direction indicator unit 9 ₁ address information receives the data 31 recorded in the "AAAB" header unit 33 collates the address information and the reference table 21, a reference table based on the designation of the third line 212 of 21, and transmits the data 31, contact bus 13 _1, the connecting portion 12 _1, ring bus 11, connecting portions 12 _2, the chip B3 ₂ via the external bus _{4 2.}

Further, for example, it sent from the DRAM 8, the direction instruction section _{9 1} receives the data 31 in which the address information is recorded in "uvwx" header unit 33 collates the address information and the reference table 21, the lookup table 21 Based on the designation in the fourth row 213, the data 31 is transferred to the CPU 5 via the communication bus 13 ₁ , the connection unit 12 ₁ , and the ring bus 11 (relaying the connection units 12 ₂ ,... 12 _m on the way). Send.

(Method 2)
Each chip A3 ₁ , chip B3 ₂ ,..., Chip m3 _m , center chip 2, etc. is given a unique external address for identifying each other, and the internal configuration of the center chip 2 (CPU 5 ROM 6, EEPROM 7, DRAM 8, etc.) are given unique internal addresses for identifying the internal configuration of the center chip 2.

Chip A3 ₁ , chip B3 ₂ ,... Chip m3 _m , center chip 2, and the internal configuration of center chip 2 are data to be transmitted to other chips (for example, from chip A 3 ₁ to chip B 3 ₂ ). Is added with an external address, and an internal address is assigned to data transmitted to the internal configuration of the center chip 2 (for example, from the CPU 5 to the DRAM 8). Each header portion 33 of the data 31 to be transmitted chips for example from the chip A3 ₁ in DRAM 8, records the internal address of the external address and DRAM 8 of the center chip 2, respectively.

Each of the direction instruction sections 9 ₁ , 9 ₂ ,... 9 _m has a reference table 21 in which information for determining the transmission direction of the data 31 is recorded based on the external address and the internal address. Each of the direction indicating units 9 ₁ , 9 ₂ ,... 9 _m collates the internal address or external address recorded in the header 33 of the acquired data 31 with the reference table 21, and similarly to (Method 1). Determine the data transmission direction and transmit.

Even the (Method 1) (Method 2) a method other than a direction instruction section 9 _1, 9 _2, if the transmission path of the data and the like in · · · 9 _m correct selections, what way The data transmission destination may be selected.

[Processing procedure]
FIG. 3 is a flowchart showing an operation procedure of the communication system 1A according to the first embodiment. The processing procedure will be described below based on the flowchart.

  First, a case where a chip other than the center chip 2 is included in a data transmission / reception target will be described based on the flowchart of FIG.

When one chip, for example, the chip A3 ₁ performs temporary storage of the data 31 (the data main body 32) in the DRAM 8 of the center chip 2, the chip A3 ₁ stores the address information “pqrs” of the DRAM 8 in the data main body 32. The recorded data 31 with the header portion 33 added (in the case of the above (Method 2), the address information of the center chip 2 is further recorded) is added via the external bus 4 ₁ , connection portion 12 ₁ , and communication bus 13 _1. and it transmits the direction indicating section _{9 1} of the center chip 2 (step S1). Direction indicator unit _{9 1} collates the address information of the header portion 33 of the data 31 and the reference table 21 (step S2).

Result of the collation, the direction instruction section _{9 1} detects that the address information coincides with the address of DRAM 8 ( "Yes" in step S3), and transmits the data 31, the DRAM 8 via the direct bus 10 ₁ (step S4). In the DRAM 8, the data 31 (the data main body 32) is temporarily stored.

On the other hand, when the DRAM 8 transmits the data 31 to the chip A3 ₁ after this step S4, the DRAM 8 records the address “AAAB” of the chip A3 _{1 in} the data main body 32 (the above (Method 2)). In such a case, a header 33 (in which address information of a chip A3 ₁ CPU (not shown) or the like is recorded) is further added, and data is transmitted in the opposite direction to the original communication path in the same procedure.

That is, data 31 DRAM8 sent is transmitted to the direction indicating section _{9 1} via the direct bus 10 ₁ (step S1). Direction indicator unit _{9 1} collates the address information of the header portion 33 of the data 31 and the reference table 21 (step S2), and detects that the address information coincides with the chip A3 ₁ address (i.e. DRAM8 other address) the direction indicating section _{9 1} which is ( "No" in step S3), and based on the collation result, and transmits the data 31, contact bus 13 _1, the connecting portion 12 _1, the chip A3 ₁ via the external bus _{4 1} (Step S5).

On the other hand, when transmitting one chip for example, a chip A3 ₁ other chips such as data on the chip B3 _2, chip A3 ₁ is the data body portion 32, a header portion 33 which chip B3 ₂ address "AAAB" is recorded the data 31 obtained by adding the external bus _{4 1,} the connecting portion 12 _1, via the communication bus 13 ₁ transmits to the direction indicating section _{9 1} of the center chip 2 (step S1). Direction indicator unit _{9 1} collates the address information of the header portion 33 of the data 31 and the reference table 21 (step S2). The direction indicating section _{9 1} detects that the address information is chip B3 ₂ (i.e. non-DRAM 8) Based on ( "No" in step S3), and the verification result, the data 31, via the ring bus 11 chips and it transmits to the B3 ₂ (step S5). Specifically, the direction instruction section _{9 1} transmits the data 31, contact bus 13 _1, the ring bus 11 via the connection portion 12 _1. The data 31 is circulated a ring bus 11, connecting portions 12 _2, it is transmitted to the chip B3 ₂ via the external bus _{4 2.}

After the step S5, when the chip B3 ₂ sends the data back to the chip A3 ₁ , the chip B3 ₂ transmits the data 31 in which the address of the chip A3 ₁ is recorded to the header 33 (step S1). This data, the external bus _{4 2,} connecting portions 12 ₂ is transmitted to the direction indicating section _{9 2} of the center chip 2 via the communication bus 13 _2. Direction indicating section 9 ₂ collates the address information and direction indicating portion 9 ₂ of the reference table of the header portion 33 (not shown in FIG. 2) (Step S2). The direction indicating section _{9 2} it is detected that the address information is chip A3 ₁ (i.e. non-DRAM 8) Based on ( "No" in step S3), and the verification result, the data 31, via the ring bus 11 chips A3 ₁ is transmitted (step S5). Specifically, the direction instruction section _{9 2} transmits the data 31, contact bus 13 _2, the ring bus 11 via the connection portion 12 _2. The data 31 circulates in the ring bus 11 and is transmitted to the chip A3 ₁ via the connection unit 12 ₁ and the external bus 4 ₁ . Incidentally, the chip B3 ₂ is sent back (step S1) the data 31 is transmitted to the direction indicating section _{9 1} again follows the original transmission path, the data by the matching direction instruction section _{9 first} reference table 21 (step S2) 31 there may be transmitted to the chip A3 ₁ (step S5) configuration.

  Next, based on the flowchart of FIG. 3, a case where only the internal configuration of the center chip 2 is a data transmission / reception target will be described.

First, in the configuration including the DRAM 8 of the center chip 2, for example, when the CPU 5 transmits / receives data to / from the DRAM 8, the CPU 5 stores the data 31 in which the header portion 33 in which the address information “pqrs” of the DRAM 8 is recorded is added to the data body portion 32. , ring bus 11, connecting portions 12 _1, transmits through the contact bus 13 ₁ in the direction indicating section _{9 1} of the center chip 2 via a (step S1). In the center chip 2, the direction instruction section 9 ₁ collates the reference table 21 and the address information of the header portion 33 of the data 31 (step S2).

Result of the collation, the direction instruction section _{9 1} detects that the address information coincides with the address of DRAM 8 ( "Yes" in step S3), and transmits the data 31, the DRAM 8 via the direct bus 10 ₁ (step S4). The DRAM 8 receives the data and temporarily stores the data.

  When the data 31 of the DRAM 8 is transmitted to the CPU 5 after step S4, the DRAM 8 adds the header portion 33 in which the address “uvwx” of the chip CPU 5 is recorded to the data main body portion 32, and performs the same procedure. Data is transmitted in the opposite direction to the original communication path (“No” to step S5 in steps S1 to S2 to S3).

On the other hand, when the center chip 2 does not include the DRAM 8, for example, when the CPU 5 transmits and receives data to and from the EEPROM 7, the CPU 5 adds a header portion 33 in which the address “uvwz” of the EEPROM 7 is recorded to the data body portion 32. Data 31 is transmitted to the ring bus 11. The transmitted data, ring bus 11, connecting portion 12 ₁ is transmitted to the direction indicating section _{9 1} via the communication bus 13 ₁ (step S1). Direction indicator unit _{9 1,} header part 33 collates the address information and the reference table 21 (step S2) of the data 31, a direction instruction detects that the address information is EEPROM7 address (i.e. DRAM8 other address) part _{9 1} ( "No" in step S3), and the data 31, contact bus 13 _1, the connecting portion 12 _1, and transmits the EEPROM7 via a ring bus 11 (step S5).

  On the other hand, when the EEPROM 7 returns the data 31 to the CPU 5 after this step S5, the EEPROM 7 adds a header portion 33 in which the address “uvwx” of the CPU 5 is recorded to the data body portion 32, and performs the same procedure. The data is transmitted in the opposite direction to the original communication path (“No” to Step S5 in Steps S1 to S2 to Step S3).

As described above, in this embodiment, the direction indicating sections 9 ₁ , 9 ₂ ,... 9 _m provided in the center chip 2 transfer the data addressed to the DRAM 8 supplied from one chip, for example, the chip A 3 ₁ to the direct bus. send to 10 _1, in order to transmit a one-chip data of another chip for example, a chip B3 ₂ destined supplied e.g. from chip A3 ₁ to the ring bus 11, direct bus _{10 1,} 10 2, the · · · 10 _m A dedicated line is used for communication up to the DRAM 8 and the ring bus 11 is connected to various chips A3 ₁ , chip B3 ₂ ,..., Chip m3 _m , the center chip 2 CPU 5, ROM 6, EEPROM 7, etc. It can be used as a general-purpose communication line used for data transmission / reception. Therefore, each of the chip A3 _1, chip _B3 2, without providing a separate dedicated line and a general-purpose communication lines from ... chip m3 _m to DRAM 8, the chip A3 _1, chip _B3 2, ... chip m3 _m and delay of data transmission / reception between the DRAM 8 and the chip A3 ₁ , chip B3 ₂ ,..., chip m3 _m, and the general-purpose communication between the CPU 5, ROM 6, EEPROM 7, etc. of the center chip 2. It can be carried out. As a result, it is possible to secure and connect with a plurality of configuration requirements, and it is possible to increase the processing speed of the system by suppressing the occurrence of latency in specific resources while saving hardware resources. .

In this embodiment, direct bus _{10 1,} 10 2, · · · 10 _m is, the direction instruction section _{9 1,} 9 2, while being formed as a dedicated line between the · · · _{9 m} and DRAM 2, ring bus 11 is formed as an annular communication line, so that a delay in communication between the chip A3 ₁ , the chip B3 ₂ ,..., The chip m3 _m and the DRAM 8 is surely suppressed, and the chip A3 ₁ , the chip B3 ₂ , ... Data can be reliably transmitted and received between the chips m3 _{m and} between the CPU 5, ROM 6, EEPROM 7, etc. of the center chip 2 while circulating the annular communication line.

In this embodiment, direct bus _{10 1,} 10 2, · · · 10 _m is DRAM 8 and the respective direction indicating section _{9 1,} 9 2, by being provided between the · · · _{9 m} , chip A3 _1, chip _B3 2, even if ... chip m3 _m there are multiple, identical direct bus _{10 1,} 10 2, the use of ... 10 _m are multiple chips A3 _1, chip B3 ₂ ,..., Chip m3 _m can be prevented from competing, and delay in communication between chip A3 ₁ , chip B3 ₂ ,... Chip m3 _m and DRAM 8 can be reliably suppressed.

Conventionally, when the chip internal bus of the center chip 2 is shared in communication with the DRAM 8 and in communication with other than the DRAM 8, it has been difficult to suppress the occurrence of a large latency. However, in this first embodiment, the communication speed transmission is required (i.e. communication when using the DRAM 8) Direct bus _{7 1,} 7 2, star-connected by · · · _{7 m,} a relatively low speed In communications that allow even simple transmission (for example, data exchange between chip A3 ₁ , chip B3 ₂ ... Chip m3 _m ), by using ring connection by ring bus 8 properly, normal bus connection, Communication between the center chip 2 and the chips A3 ₁ , chip B3 ₂ ... Chip m3 _m can be reliably performed while suppressing the occurrence of latency that tends to occur in the star-type or ring-type connection only.

  In this embodiment, since the specific internal resource is the DRAM 8 of the center chip 2, the entire system is shared in a system in which the DRAM 8 is shared by a plurality of devices by speeding up the transmission and reception of data processed by the DRAM 8. The processing delay can be suppressed.

In this embodiment, a plurality of communicable IC chips, such as chip A3 ₁ , chip B3 ₂ ,..., Chip m3 _m , and center chip 2, save hardware resources and use specific resources. It is possible to increase the processing speed of the system by suppressing the occurrence of latency.

[Embodiment 2 of the Invention]
FIG. 5 shows a second embodiment of the present invention.

In the communication system 1B of the second embodiment, the direction instructing sections 9 ₁ , 9 ₂ ,... 9 _m of the center chip 2 are connected to the connecting sections 12 ₁ , 12 _{2 ,.} It is provided in the position. Thus, for example the direction instruction section _{9 1,} the external bus _{4 1,} contact bus 13 _1, ring bus 11 is connected. Then, this communication system 1B, the connection portions _{12 1,} 12 2 in the first embodiment, · · · 12 _m and contact bus _{13 1,} 13 2, construction of · · · 13 _m is absent. Each of the direction indicating sections 9 ₁ , 9 ₂ ,... 9 _m is provided with a reference table 21 similar to that in the first embodiment. Other configurations are the same as those in the first embodiment.

In the communication system 1B of the second embodiment, each direction indicating unit, for example, the direction indicating unit 9 is provided at a location where the external bus 4 ₁ , the communication bus 13 ₁ , and the ring bus 11 are connected. The configuration of the reference table 12 can be simplified. That is, all routes can be selected by recording the route to the nearest node in the reference table 21 of each direction instruction unit 9 ₁ , 9 ₂ ,... 9 _m . As a result, data can be reliably transmitted and received while the system and the reference table 21 have a simple configuration.

  In each of the above embodiments, only one center chip 2 is provided. However, a configuration in which a plurality of center chips 2 exist may be used.

In the above embodiments, the "specific internal resources" is set to DRAM 8, what is not limited thereto, a plurality of chips A3 _1, if that can be shared by the chip B3 ₂ · · · chip m3 _m It may be a thing. For example, the “specific internal resource” may be an SRAM instead of the DRAM 8, the CPU 5 or the EEPROM 7, or an external storage medium such as a magnetic disk.

In each of the above embodiments, the center chip 2 and a plurality of, for example, m (m> 1) chips A3 ₁ , chip B3 ₂ ... Chip m3 _m are connected. It can also be used when nodes are connected.

  In the above embodiments, the communication systems 1A and 1B are used for the gaming machine 100 and the like. However, the communication systems 1A and 1B are used for various other devices, for example, electronic control of automobiles and various machines and all other applications. It may be used in any processing other than image processing and sound processing, such as rotation control of a motor, in a gaming machine or a device other than a gaming machine. Further, electronic devices other than IC chips, communication devices, and the like may be used.

  It is needless to say that each of the above embodiments is an exemplification of the present invention and does not mean that the present invention is limited to the above embodiment.

1A, 1B ... Communication system 2 ... Center chip (device, central device, IC chip)
3 ₁ , 3 ₂ ,... 3 _m ... Chip A, Chip B,... Chip m (device, terminal device, IC chip)
8 ... DRAM (specific internal resources, main memory)
9 ₁ , 9 ₂ ,... 9 _m, direction indicator (route selection means)
10 ₁ , 10 ₂ , ... 10 _m ... direct bus (first route)
11 ... Ring bus (second route)
100 ... gaming machine

Claims (4)

A communication system that enables communication between a plurality of devices,
In the plurality of devices,
At least one central device interposed in communication between the devices;
A plurality of terminal devices each communicatively connected to at least one central device;
The central device is
A main memory used for processing and / or recording data;
A path selection unit that is interposed between the main storage device and the terminal device and selects a transmission path of the data in order to share the data among a plurality of devices;
A plurality of first paths that are communicably provided to the path selection means and form a data path between each of the path selection means and the main storage device;
Separately from the first route, the second route is provided so as to be communicable with the route selection means, and forms a data route between the terminal devices,
The main storage device is shared by the terminal devices,
Each said 1st path | route is comprised by the data bus which forms the path | route of the said data of this terminal device and the said main memory provided for every said terminal device,
The second path is constituted by a data bus formed in a ring shape so that the data can be circulated,
The path selection means transmits / receives the data between the terminal device and the main storage device by transmitting the data addressed to the main storage device supplied from the one terminal device to the first route. And transmitting the data addressed to the other terminal device supplied from the one terminal device to the second path to transmit / receive the data between the plurality of terminal devices. Communications system. A communication system that enables communication between a plurality of devices,
In the plurality of devices,
At least one central device interposed in communication between the devices;
A plurality of terminal devices each communicatively connected to at least one central device;
The central device is
A main storage device used for processing and / or recording of data to be computed in the computing device;
A path selection unit that is interposed between the main storage device and the terminal device and selects a transmission path of the data in order to share the data among a plurality of devices;
A plurality of first paths that are communicably provided to the path selection means and form a data path between each of the path selection means and the main storage device;
Separately from the first route, the second route is provided so as to be communicable with the route selection means, and forms a data route between the terminal devices,
Each said 1st path | route is comprised by the data bus which forms the path | route of the said data of this terminal device and the said main memory provided for every said terminal device,
The second path is constituted by a data bus formed in a ring shape so that the data can be circulated,
The second path is connected to the arithmetic device used for various calculations of the data in the central device, and an auxiliary storage device in which the data supplied to the main storage device is recorded,
The route selection means includes
The data addressed to the main storage device supplied from the one terminal device is transmitted to the first path to transmit and receive the data between the terminal device and the main storage device. The data addressed to the other terminal device supplied from the terminal device is transmitted to the second path to transmit / receive the data between the plurality of terminal devices,
And while transmitting the data addressed to the main storage device from the arithmetic device or the auxiliary storage device to the first path, the data addressed to the arithmetic device or the auxiliary storage device from the main storage device A communication system, wherein the data is transmitted to a second path and the data in the central device is processed.   The communication system according to claim 1, wherein the device is an IC chip, and the IC chip as the device is provided in a gaming machine. At least one central device intervening in communication between a plurality of devices;
A plurality of terminal devices each communicatively connected to at least one central device;
The central device is
A main memory used for processing and / or recording data;
A path selection unit that is interposed between the main storage device and the terminal device and selects a transmission path of the data in order to share the data among a plurality of devices;
A plurality of first paths that are communicably provided to the path selection means and form a data path between each of the path selection means and the main storage device;
Separately from the first route, a communication method in a communication system comprising a second route which is provided so as to be communicable with the route selection means and forms a data route between the terminal devices. ,
The main storage device is shared by the terminal devices,
Each said 1st path | route is comprised by the data bus which forms the path | route of the said data of this terminal device and the said main memory provided for every said terminal device,
The second path is configured by a data bus formed in a ring shape so that the data can be circulated,
In the route selection means, the data addressed to the main storage device supplied from one terminal device is transmitted to the first route to transmit / receive the data between the terminal device and the main storage device. And a procedure for transmitting the data addressed to the other terminal device supplied from the one terminal device to the second path and transmitting and receiving the data between the plurality of terminal devices. A communication method characterized by the above.

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