JPH0415743A - Parallel arithmetic unit - Google Patents

Abstract

PURPOSE:To attain the parallel arithmetic operations at a high speed by connecting the arithmetic elements to each other and actuating these elements independently of each other for an access given to a memory means. CONSTITUTION:The programs of the arithmetic elements (PU0 - PU3) 211a - d of an arithmetic part 104 which are stored in a program memory PM are previously developed by a main CPU 101 and produced in the practicable code forms by the processors 212a - d (PROC). These produced programs are stored in an external storage 102 and then transferred to the processors 212a - d by the CPU 101 through a system bus 116 and a system bus I/F 109. These processors have own their program memories PM 213a - d respectively. Then each of the processors receives its own program from the CPU 101 and writes the program in a prescribed address of its own PM. Thus the parallel arithmetic operations are attained at a high speed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a parallel arithmetic device characterized by parallel processing operations.

[Prior Art] In general, image data contains a large amount of information compared to document data, etc., so image processing devices that process such image data require large computing power to perform numerical calculations on the image data. required. For this reason, various image processing apparatuses have been proposed in the past for the purpose of increasing the efficiency of calculation by effectively utilizing the spatial and temporal parallelism inherent in image processing.

r Information Processing J (Vol, 28. No, 1, pp
, 19-26), the basic methods employed in these image processing apparatuses are classified into the following four types.

(1) Fully parallel processing method This is a method in which calculation elements are arranged two-dimensionally corresponding to pixels and all pixels are processed simultaneously. Typically, computing elements are interconnected with adjacent computing elements for data transfer.

(2) Local parallel processing method This is a method in which each pixel is processed using the locality of image data, and this processing is applied to all pixels in turn. Spatial filtering is performed using a total of 9 pixels (a pixel matrix area consisting of 3 pixels each vertically and horizontally, with the pixel of interest as the center; this is called a window), consisting of 8 pixels adjacent in the vertical, horizontal, and diagonal directions. In this case, processing for the entire image is proceeded by shifting this window to the right one pixel column at a time.

(3) Pipeline method A method in which arithmetic units that perform basic processing of image data are connected in series to form a pipeline, and processing proceeds by transferring pixels one after another through this pipeline. be.

(4) Multiprocessor system This is a multiprocessor type system that combines multiple arithmetic modules or general-purpose processors.

[Problems to be Solved by the Invention] However, the above conventional example has the following problems.

First, in the completely parallel processing method (1), all pixels are processed at the same time, so calculation elements equal to the number of pixels are required. For this reason, the entire device tends to become large-scale. In order to avoid such an increase in scale, it is necessary to simplify the calculation elements, which causes problems such as specifying image calculations that can be handled and complicating programming. Furthermore, the overhead for distributing each pixel to each calculation element also increases.

In the local parallel processing method (2), the processing that can be executed is determined in advance by the hardware configuration, so
The disadvantage is that there is little flexibility in image processing.

The pipeline processing method (3) has the drawback of poor flexibility, such as the inability to perform image processing that does not follow the flow of the pipeline configured by the arithmetic units.

As described above, in the methods (1) to (3), the hardware level is determined for specific image processing, so there is a drawback that there is little flexibility in the content of image processing.

The multiprocessor system (4) is configured by combining a general-purpose processor or a plurality of arbitrarily programmable calculation modules, and is highly flexible in the processing content that can be handled. However, even in this multiprocessor system, problems remain from the viewpoints described below. That is, the size (number of pixels) of images to be handled varies depending on the application field of image processing. For example, if it is a TV image, 51
A pixel count of about 2 x 512 is sufficient, but for prints such as electronic publications, a pixel count of about 4096 x 4096 is required. Furthermore, when creating a block for printing, it is desirable to support image sizes with even larger numbers of pixels. In addition, it is desirable to be able to set the image size of the monitor display independently of the image data size to be processed.

In addition, regarding the processing speed of image calculations, flight
There are some differences, such as those that require real-time performance such as simulators, and those that require interactive processing such as electronic publishing that can be completed within a time that does not irritate humans. It is also desirable that the accessible image data area be variable depending on the type of calculation.

As discussed above, image processing devices vary depending on their application field: 1. Image size that can be processed.

2. Computing power and number of computing elements.

3. Image size for the monitor that can be changed independently of the image size that can be processed.

4. It is desirable that the image data area etc. that can be accessed from each calculation element can be freely set.

Further, even in the multiprocessor system described above, which is highly flexible in terms of the processing content that can be handled, its configuration is unsatisfactory from the viewpoints 1 to 4 above.

The present invention has been made in view of the above-mentioned conventional example, and an object of the present invention is to provide a parallel arithmetic device having flexibility in arithmetic operations on various types of data that can be processed.

[Means for Solving the Problems] In order to achieve the above object, a parallel processing device of the present invention has the following configuration. That is, a plurality of programmable arithmetic elements, communication means for connecting the arithmetic elements, memory means independently accessible from each of the arithmetic elements, and operating each of the arithmetic elements independently; , and control means for controlling access to the memory means by the arithmetic element.

[Operation] The above configuration has communication means for connecting a plurality of programmable computing elements, and each of these computing elements can independently access the memory means. Each of these computing elements is operated independently, and access to the memory means by these computing elements is controlled.

[Embodiments] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

<Description of Image Processing Apparatus (FIG. 1)> FIG. 1 is a block diagram showing a schematic configuration of the image processing apparatus of this embodiment.

In the figure, 101 is a main CPU that controls the entire system. 102 is a large-capacity external storage device that stores image data and the like. Reference numeral 103 indicates a parallel processing unit, which connects a calculation unit 104 consisting of a plurality of calculation elements, a data memory unit 107 that holds image data to be processed, etc., and a group of buses between the parallel processing unit 103 and the data memory unit 107.・
A bus connection/exchange unit 106 to be replaced, a bus connection/exchange control unit 1o5 that controls this bus connection/exchange unit 106, and an interface (1/F) unit 10 with the system bus 116.
9, a high-speed bus 117 for high-speed data transfer, and an interface (I/F) section 108.

A video memory 110 holds image data to be displayed on a monitor display 111, and is connected to a system bus 116 and a high-speed bus 117. 112 is a printer interface section (■/F), through which the printer 114 is connected to the system bus 116 and the high-speed bus 117.
It is connected to the. Reference numeral 113 denotes a scanner interface (F/F) unit, through which the image scanner (reader) 15 is connected to a system bus 116 and a high-speed bus 117.

Description of Parallel Processing Unit 103 Next, a method of loading a program from the main CPU 101 to each calculation element of the calculation unit 104 of the parallel processing unit 103 will be described. This will be explained below with reference to FIGS. 1 and 2.

FIG. 2 is a block diagram showing a schematic configuration of the parallel processing unit 103.

Each calculation element (PtlO to Pυ3) 211 of the calculation unit 104
The programs to be stored in the program memories (PM) of a to d are developed in advance by the main CPU 101 and created in a code format executable by each of the processors 2128 to 212d (PROC). These programs are stored in the external storage device 102 and are
tJ 101, the data is passed from the system bus 116 to each processor via the system bus I/F 109.

Each of these processors (PROC) 212 a-d has its own program memory (PM) 213 a-
Each of the processors 212a to 212d has a function of sequentially writing the corresponding program to a predetermined address in its own program memory (PM) upon receiving the program corresponding to it from the main CPU 101.

Description of Computing Unit> FIG. 3 is a diagram showing the state of communication paths connecting each processor of the computing unit 104.

Four serial communication paths are connected to each processor (PROC) separately from the bus, and the main purpose of these serial communication paths is to communicate between each processor, but there are other It is also used to download programs from the main CPU 101 to each processor. These processors 2128 to 212d have a reset signal line (not shown) and a boot method instruction line for selecting a boot method. When a reset signal is input through these reset signal lines, each processor is initialized, and the R assigned to a specific address for booting is determined by the signal level of the boot method instruction line when the reset signal is input.
It has a function to select whether to perform booting from OM or by data input from a serial communication path.

In this embodiment, the latter method of booting is performed using the serial communication path, and a representative example of a processor having such a function is a transputer manufactured by Inmos.

In FIG. 3, reference numeral 1000 denotes a switch circuit that can arbitrarily exchange communication paths, and is composed of a communication path exchange section 1002 and a communication path exchange control section 1001.

The communication path exchange unit 1002 includes four communication paths (16 in total) from each processor, and an external communication exchange unit connector l○05 for connecting to an external communication path.
8 communication lines to and parallel/serial converter 10
04 serial input/output line is connected. In addition, the serial input/output side of the parallel/serial converter 1003 is
It is connected to the communication path exchange control unit 1001. The parallel input/output sides of these parallel/serial converters 1003 and 1004 are both connected to the system bus 116 via the system bus I/FIO9. In addition, parallel/
The parallel input/output addresses of serial converters 1003 and 1004 are respectively assigned to different predetermined addresses on the address space of the system bus.

The main CPU 10I has a system bus 116° system bus I/F 109, and a parallel/serial converter 1003.
An instruction is given to the communication path switching control unit 1001 via the communication path switching unit 1001 to set the connection state of the communication path of the communication path switching unit 1002. At this time, the serial input/output of the parallel/serial converter 1004 is set to a communication path of one of the processors 212a to 212d through the communication path conversion unit 1002 and used. The remaining processors are connected to the communication path converter 10o2 via another communication path via the processor connected to the parallel/serial converter 1004. At this time, another processor may be interposed between the set processor and any of the remaining processors. In this state, main C
PUl01 transfers downloaded data to system bus 1.
16, System Has I/F109. Parallel/serial converter 1004. The data is transferred to a desired processor via the communication path exchange unit 1002. Then, when the program data transfer is completed, that program is executed.

Examples of circuit elements having the function of the switch circuit 1000 include a link switch COO4 made by Inmos, and parallel/serial converters 1003 and 100.
As a circuit element having the function of 4, for example, Inmos
For example, the link adapter CO12 manufactured by Co., Ltd. is available.

<Configuration of the parallel processing unit 103> In this embodiment, in order for the calculation elements of the calculation unit 104 to access the data memory 107, the address area of the data memory 107 is divided into a plurality of small areas, and these small areas are Each calculation element performs processing as a unit. In this case, the system is configured to realize a system in which each calculation element occupies each of these small areas, and a system in which each calculation element accesses a pixel at an arbitrary position in the data memory area. Hereinafter, the data memory area will be called a block memory, the access method that occupies a block will be called a block access method, and the method that accesses an arbitrary pixel will be called a pixel access method.

A functional block diagram of the parallel processing unit 103 that realizes the above two methods is shown in FIG.
This is a register for exchanging control commands and status between the CPU 3 and the main CPU 101. 210a
~210p represents a block memory obtained by dividing the data memory 107.

To facilitate the explanation of this embodiment, data memory section 1
07 has a capacity of 16 Mbytes, and the data memory section 107
is equally divided into 16 MBO-M815, and the arithmetic unit 104
The number of calculation elements (PUO-PI3) in is assumed to be four. 2
Reference numerals 11a to 211d are four computing elements that constitute the computing unit IO4, and each computing element includes arithmetic processors 212a to 212d (hereinafter simply referred to as processors), a program for driving the processors, and a temporarily small Each of them has one small capacity memory (hereinafter referred to as program memory) 213a to 213d for storing a large amount of data. 215 is the system bus 116 and high-speed bus 117
This is an interface bus that connects the bus interface sections 108 and 109 of the data memory section 107 and the data memory section 107. 2168-p are memory buses for exchanging data between each block memory 210a=p and the calculation unit 104, and 217aNd is a processor bus. 214.21
8. 219, 220, 221, 222, and 223 are all control signal lines. Among the control signal lines connected to the register 200, the signal line 214 is connected to the system bus interface unit 109, and the signal line 218 is connected to the bus.・The exchange control unit 1o5 (hereinafter abbreviated as bus controller), the signal line 220 connects the calculation unit 104, and the signal line 222 connects the high-speed bus interface unit 108, and these control signal lines exchange commands and status. There is. Further, among the control signal lines connected to the bus controller 105, the signal line 219 is connected to the arithmetic unit 104, and the signal line 221
Connects the bus connection/exchange unit 106 (hereinafter abbreviated as bus selector) and the signal line 223 connects the data memory unit 107 to perform similar exchanges.

Initialization of Parallel Computing Unit> The parallel computing unit 103 operates by loading image data and programs from the main CPU I0I.

The main CPU IO1 first initializes the parallel calculation unit 103. The main CPU 101 writes an initialization command to the register 200 via the system bus interface section 109 and the signal line 214. Therefore, the register 200 sends the initialization command to the signal lines 218, 219, 2.
20, 221, and 222 via the high-speed bus interface unit 108. Bus controller 1o5. path selector 1
06 and each arithmetic unit 211a-d of the arithmetic unit 104,
Initialize each. The downloading of the processor initialization program from the main CPU 101 to each program memory 213a-d of each calculation element 211a-d and the setting of communication path means between processors will be described later in a separate section.

By the above initialization, the interface bus 215 is brought into a connected state between the system bus interface section 109 and the data memory section 107, and all addresses and data are reset. Thereafter, the main CPU 101 switches the system bus 116 or the interface bus 215 to the high-speed bus interface section 108, and writes image data into the data memory section 107 from the outside.

Configuration of Data Memory Section 107> The data memory section 107 has consecutive addresses when viewed from the interface bus 215.

Here, to simplify the explanation, data for one pixel is Y (yellow), 9M (magenta), C (cyan), Bk
(black), and each color is represented by 8-bit data. Since the total capacity of the data memory section 107 is 16M bytes, the image size is 2048X2048, and its address area is 000000H-FFFFFFH (H is 1
(represents a hexadecimal number).

FIG. 4 shows the data structure of this data memory section 107. Y, M, C, B represent the data of each color, (
The numbers in ) indicate pixel positions in the image data.

Each memory block of data memory 107 is configured as a dual port memory, and each port of each block memory is connected to interface bus 215 and memory bus 216a-p, respectively. And interface bus 2
When accessing these memory blocks from the 15 side, it is done using the addresses from ○○○0OOH to FFFFFFH described above. The memory allocation of block memories 21Oa-p is as shown in FIG. The dotted lines indicate the order of addresses as viewed from the interface bus 215.

The address shown in square brackets "[]" indicates the address of the data memory 107 which stores 1 byte of seven color data for each pixel. The solid lines indicate the order of addresses as seen from memory buses 216a-p. Also, Yakatsuko "ku 〉"
The address indicated by is an address in which one byte of seven-color data of each pixel in the memory block 2101 is stored.

Configuration of Internal Bus> As shown in FIG. 2, the internal buses of the parallel processing unit 103 include an interface bus 215 and a memory bus 21.
6a to 6p and processor buses 217a to 217d, and the configuration of each bus will be explained below.

First, in the interface bus 215, the address and data widths may have the same configuration as the system bus at maximum, but here the address space is 16M hide. Therefore, the address width is 24 bits and the data width is 32 bits.

Next, since the memory buses 216a to 216p are used when accessing the memory blocks, they are 1M byte corresponding to the address space of each memory block. Therefore, the address width is 20 bits and the data width is 8 bits. Finally, the configuration of processor buses 217a to 217d is memory bus 216a.
- The configuration is similar to that of p.

Block access method> The block access method is based on each processor 212a-d.
This is a method in which a plurality of block memories from among the block memories 210a-p are occupied and accessed. That is, one block memory is not accessed by two or more processors at the same time. Here, when viewed from the processors PROC 212a to 212d, each processor generates a 24-bit address in order to be able to address the entire address space of 16 Mbytes. Therefore, the aforementioned processor buses 217a to 217
As shown in FIG. 6, 4 bits indicating the memory block number are added to the upper part of the 20 bits of the address 7d to make the address 24.
Allows bit addressing.

Such addresses are used on processor buses 217a to 217.
d, the aforementioned memory block number, ie, the upper 4 bits of the address, is sent to the bus controller 105. Thereby, the bus controller 105 switches the bus selector 106 according to the memory block number, thereby allowing each processor to access a desired memory block. If multiple processors try to access the same memory block, the processor with the highest priority will occupy it according to the preset priority order, and the other processors will either go into a waiting state or respond to requests from other processors. Perform operations such as switching the memory block to another memory block.

Pixel Access Method> The pixel access method is a method in which each of the processors 212a to 212d accesses an arbitrary pixel in the area of the data memory section 107. That is, one pixel is prevented from being accessed by two or more processors at the same time.

The address data generated by processors 212a-d is 24 bits similar to the block access method. The upper 4 bits of the address generated in this way are transmitted to the bus controller 105, and the remaining lower bits are transmitted to the processor bus (217a to 217d).

As a result, when each processor does not access the same memory block, the bus controller 105 uses the path selector 106 to connect the memory bus 216a-p and the corresponding processor bus 217a so that the pixel data requested by each processor can be obtained. - Connect to either of d.

If multiple processors attempt to access pixels in the same memory block, the processor with the higher priority accesses the memory block according to a preset priority order, and the other processors enter a wait state.

Then, in the next clock, the memory block is accessed by time sharing according to the priority order.

Configuration of Lotus Selector 106> The configuration of the lotus selector 106 will be described below with reference to FIGS. 7 and 8.

The inside of the lotus selector 106 can be separated into a data section including a bidirectional selector and an address section including a unidirectional selector. FIG. 7 is a block diagram of the data section of the path selector 106, and FIG. 8 is a block diagram of the address section of the path selector 106.

First, the configuration of the data section will be explained. In FIG. 7, 300 and 305 are bidirectional buffers that control the direction in which data flows. Reference numerals 301 and 304 are latch circuits for correcting data timing deviations due to delays in each element. 302 and 303 are selector sections.

In the bidirectional buffer 300, 306a-t are negative operation buffers 307a-p that are conductive when the control signal DI RB 310 is "○" and are in a high impedance state when it is "l".
is a normal operation buffer that is conductive when the control signal DIRB is "1" and becomes a high impedance state when the control signal DIRB is "O". In addition, 308a''p of the selector section 302 is a 4-1 selector that selects and outputs one out of four human forces.
03, 309a to 309p are 1-4 selectors that select one of four outputs from one input and output the selected one.

313a-p indicate data lines through which data of the memory buses 216a-p pass; for example, data line 313a is a data line from memory block 210a to memory bus 216a. The same applies to 313b to 313p below.

Further, 314a to 314d are data lines through which data passes among the processor buses 217a to 217d, and for example, the data line 314a indicates the data line of the processor bus 217a. The same applies to 314b-d below.

310.311, 312, 313 are bus controller 1
05, signal lines 310 and 311 are used to control each bidirectional buffer 300. It determines the direction. Note that the name of the signal passing through the signal line 310 is DI.
It is assumed to be RB and has a width of 16 bits. Further, the name of the signal passing through the signal line 311 is DIRP, and the width is 4 bits.

Furthermore, the signal lines 312 and 313 are connected to the processor 212a -
d or memory blocks 210a-p is being accessed, a selector signal is sent to switch the connection between selector sections 302 and 303. The signal name passing through the signal line 312 is 5ELR, and the signal width is equal to the number of processors for each memory block (in this case, 16X4=6
4 bit width). The name of the signal passing through signal line 313 is 5E.
LW and the signal width similar to 5ELR (in this case, 64
bit).

Next, the address section of the bus selector 106 will be explained with reference to FIG.

In FIG. 8, 1300a-d and 1302 are latch circuits for correcting data timing deviations due to delays in each element. 1301a to 1301d are 1- outputs that select one output from 16 outputs using one person's power.
16 selector.

1303a-d are address lines through which address information passes among the processor buses 217a-d. Here, for example, address line 1303a is an address line of processor bus 217a, and is connected to processor 212a. This signal name is PAO. Below, address line 1303b
The same applies to -d. Further, 1304a-p indicates address lines through which addresses of the memory buses 216a-d pass, and for example, address line 1304a supplies an address to the memory block 210a. Similarly, address lines] and 304b-p are memory blocks 2 and 304b-p.
An address is supplied to each of 10b to 10p.

FIG. 9 is a block diagram showing the configuration of the 1-16 selectors 1301a-d. Since the selectors 1301a-d all have the same configuration, the 1-16 selector 1301a will be explained as an example.

1800 is the address line of the processor bus 217a * 1801 a-p is the address line of each memory bus 216aA-p
It leads to the address part of. 1802a to 1802p are conductive when the control line SEL is "1" at the same time for the 20-bit output,
This is a direct operation buffer with high impedance at “0”. 18o3 is a control signal line (SEL) input from the bus controller 105, and the normal operation buffers 1802a to 1802p are controlled by this. The signal output to this control line connects the control line entering the normal operation buffer 1802a to M
This is a signal in which the control line entering 1802p is designated as SB and the control line entering 1802p is designated as LSB, and the bits are arranged one bit at a time according to the block diagram.

Operation of Bus Selector 106> Based on the above configuration, the operation of the bus selector 106 will be explained using an example.

First, a method for the processors 212a to 212ci to read data from the memory block 107 using a block access method will be described.

Here, the processor 212a is connected to the memory block 210
A case will be described in which 1 byte data is read from address 100H of a. First, processor 212a issues a 24-bit address as shown in FIG. in this case,
The address data becomes "000100□". The upper 4 bits of this address, the R/W signal that indicates read mode or write mode, and the access mode signal that indicates access are sent to the bus controller 1 via signal line 219.
Sent to 05. In this case, the R/W signal indicates reading, and the access mode signal indicates block access.

Here, the bus controller 105 determines whether there is an access conflict, and if there is no conflict, sends a signal indicating that access is possible to the processor 212a. If there is a conflict, the priorities of the processor 212a are compared with those of other processors that have conflicted, and if the priority of the processor 212a is higher than that of the other processor, a signal indicating that access is possible is sent to the processor 212a, and vice versa. If the processor 212a has a lower priority, a wait signal indicating that it is waiting for access is sent to the processor 212a.

The processor 212a that has received the access enable signal sends an access start signal to the bus controller 105 to start accessing the memory block 210a. The bus controller 105 sends necessary control signals to the path selector 106 via the signal line 221. This control signal is divided and sent to the path selector 106 into an address part and a data part, and the data part has signal names DIRB, DIRP, and 5EL.
It is sent as R, and in the address part it is sent as signal name 5ELA. Since this is a read, the DIRB and DI signals given to the bidirectional buffers 300 and 305
In RP, the signals input to the positive operation buffer 307q and the negative operation buffer 306q connected to the processor 212a are "0°", and the signals input to the positive operation buffer 307a and the negative operation buffer 30 connected to the memory block 210a are "0°".
The signal input to 6a is also "0". In this way, the data system spring 314a of the browser bus 217a and the data line 313a of the data bus 216a are connected.

A block diagram of the 1-4 selector 309a of the selector section 303 is shown in FIG.

400a to 400d are control lines 4 from the bus controller 105.
03a=d makes it “1” for 8 input bits at the same time
This is a direct-operation buffer that is conductive when the value is ``○'' and has high impedance when it is ``○''. Each of its output lines 402a-d is connected via a latch circuit 304 to negative operation buffers 306q-t.

Therefore, in order to connect the data line 314a of the processor bus and the data line 313a of the memory bus, 4038 of the control line 313 entering the 1-4 selector 309a must be set to "1".
"O" is input to 403b to 403d. At the same time, "O" is sent to the control line 403a of the other selectors 309b to 309P in the selector unit 303 to inhibit their output. Avoid collisions.

On the other hand, in the address section, the connection between the address section 1303a of the processor bus 217a and the address section 1304a of the memory bus 216a is switched by a 1-16 selector 1301a. In addition, the bus controller 105
3 to put the block memory 210a into read mode. That is, the signal line 3 entering the 1-16 selector 1301a
Part of the 13th input is the 16-bit signal line 1803 (9th
The MSB (most significant bit) of this 16-bit signal line is "1" and the other bits are "O".

To summarize the above, when the upper 4 bits of the 24-bit address issued by the processor 212a are input to the bus controller 105 and the memory block under that address is accessible, the address (20 bits) of the processor bus 217a is input to the bus controller 105. Latch 13 of selector 106
00a (FIG. 8), then the memory block 210a is selected by the signal line 1305 input to the 1-16 selector 1301a, and the address is latched into the latch 1302. Then address line 130
4a and sent to memory bus 216a for access.

On the other hand, data read from memory block 210a enters data line 313a from the data line of memory bus 216a, passes through negative operation buffer 306a, and is latched by latch 301. The latched data passes through the data line, 1-
4 selector 309a, direct operation buffer 400
a (FIG. 10) and is latched by latch 304.

The data line 314a is then connected to the data line 314a via the negative operation buffer 306q.
That is, it is input to the processor 212a from the data line of the processor bus 217a.

Hereinafter, when accessing an arbitrary address within the same block memory (210a), the processor 212a only needs to issue an address and receive the read data. In this manner, when the access to the same block memory is terminated and the access is changed to another block memory, the processor 212a sends an access termination signal to the bus controller 105.

Next, a case in which the processors 2128 to 212d write data to a memory block will be described. Here, an example will be described in which the processor 212a issues an address and data and writes 1 byte of data to the address "999" of the memory block 210p.

First, the processor 212a issues an address as shown in FIG. In this case, the address data is “FOO9
99,”.The upper 4 bits of this address and R/W
A mode signal (in this case write mode) and an access mode signal (in this case block access mode) are sent to bus controller 105 . The bus controller 105 determines whether there is a conflict in access to the block and sends an access permission or wait signal to the processor 212a.

The processor 212a that has received the access enable signal sends an access start signal to the bus controller 105 and starts accessing the memory block 210p.

First, the directionality of the multidirectional buffers 300 and 305 in the data section of the bus selector 106 is determined. First, regarding the bidirectional buffer 300, the LSB of the signal DIRB is set to "1", the positive operation buffer 307p is made conductive, and the negative operation buffer 306p is made high impedance. Further, regarding the bidirectional buffer 305, the MSB of the signal DIRP is set to "1", the positive operation buffer 307q is made conductive, and the negative operation buffer 307P is set to high impedance. Next, the data line 314a of the processor bus 217a and the memory bus 216 are connected to the 4-1 selector 308p in the selector unit 302.
It is connected to the data line 313p of a. The bus controller 105 sends a signal 5ELW to the 4-1 selector 308p.
is controlled through a signal line 312. 4-1 selector 30
8p has the same configuration as the other selectors 308a-o.

FIG. 11 is a block diagram showing the configuration of the selector 308p.

In FIG. 11, 500a-d are control signal lines 403a
It is a direct operation buffer that turns on 8 bits at the same time when "1" is input by ~d, and puts 8 bits into a high impedance state at the same time when "O" is input. 50
1 is the data line of the memory bus 216P, and 502a=
d are data lines of processor buses 217a-d, respectively. Therefore, in order to connect the data line of the processor bus 217a and the data line of the memory bus 216p, first, the bus controller 105 connects the data line of the processor bus 217a to the data line of the memory bus 216p.
Of the control signal 5ELW from the control signal 5ELW, only the signal line 403a must be "1" and the signal lines 403b-d must be "0".

The bus controller 105 also puts the block memory 210p into write mode via the control line 223 (FIG. 2).

Data to be written subsequently is issued by processor 212a and is sent to data line 314 of processor bus 217a.
a, and the latch 3 via the direct operation buffer 307q.
-H is latched at 04.

This data is then supplied to the 4-1 selector 308p,
It passes through the data line 502a (FIG. 11), the normal operation buffer 500a, the data line 501, and is latched into the latch circuit 3o1 (FIG. 7). Thereafter, this data passes through the normal operation buffer 307p of the bidirectional buffer 300, passes through the data line 313p of the memory bus 216p, reaches the memory block 210p, and is written to a predetermined address "999" in the memory block.

Hereinafter, when accessing an arbitrary address within the same block memory, the processor 2128 only needs to issue an address and output data, and then terminates the access to the same memory block and transfers it to another block memory. When changing the access, the processor 212a sends an access end signal to the bus controller 205.

Next, the case of accessing pixels in a memory block will be described. Here, an example will be described in which the processors 212a to 212d read and write arbitrary pixel values in the data memory 107 area.

Each of the processors 212a-212d issues a memory address where a pixel value is stored. This results in
The upper 4 bits of the 24-bit address from each processor, the R/W mode signal (different for each processor), and the access mode signal (pixel access mode in this case) are sent to the bus controller 105.
determines whether or not there is an access collision for each pixel access clock for each block including each pixel, and sends an access permission or wait signal to each processor via the signal line 219. Furthermore, a control signal is sent to the path selector 106 and the data memory unit 107 via the signal lines 221 and 223 so as to connect the processor bus of the processor that has become accessible and the memory bus of the other memory block. . Bus selector 10 receiving these control signals
6 and the data memory unit 107 connect the memory bus and the processor bus as in the case of block access described above.

(The following is a blank space) <Configuration of the bus controller 105> FIG. 12 is a block diagram showing the configuration of the bus controller 105.

The bus controller 105 receives the upper 4 bits of the address output from each processor 212a to 212d, that is, the memory block number, R/W signal, access mode signal, and access start or end signal, and receives the path selector 106 and the data memory section 107. sends a signal to control the 601
A-d are buffers for storing memory block numbers output from each processor 212a-d. Buffer 601a stores the memory block number output from processor 212a. Below, the buffer 601b
-d also stores the block number from each processor 212b-d, and to explain in more detail, the buffer 601a is configured so that the processor 212a can simultaneously occupy a read area and a write area to perform processing. Stores the number of the block memory to be read and the number of the block memory to be written.

Reference numeral 605 denotes a collision detector that detects collisions of accesses from each processor to these block memories. 606
is a priority holder that stores which processor should be given priority in the event of a conflict. A controller 607 inputs the presence or absence of a conflict and the priority of the processors and generates an access permission or wait signal for each processor. 602 is a delay circuit for eliminating switching timing errors due to delays caused by the collision detector 605 and controller 607. 603 is controller 6
This is a gate that sends only the memory block number of the processor that can be accessed by 07 to the subsequent stage. A decoder 604 receives each memory block number and R/W signal and generates a signal for controlling the path selector 106 and the memory blocks 210a-p.

608a-d each correspond to a respective processor 212a-"
This is a signal line for inputting the block memory number etc. requested by d. 627 is an R/W signal from each of the processors 212a to 212d, and 628 is an access start or end signal and an access mode signal to buffers 601a to 601a.
This is a signal line for input to d. 609a Nd,
61.1a Nd, 613a-d are read memory block numbers from each processor, 610a-d,
612aNd and 614a%d are signal lines for sending write memory block numbers from each processor to the respective subsequent stages. 618a-d are each processor 212a-
A signal line 617 is for outputting an accessible or wait signal to d, and 617 is a priority holder 60 that stores the access priority of each processor determined by the main CPU I0I.
This is the signal line sent to 6. Reference numeral 619 is a signal line that transmits the presence or absence of a collision from the collision detector 605 to the controller 607. 620 is a signal line that transmits an accessible or wait signal from the controller 607. A signal line 621 sends an R/W signal to each memory block 210a to 210p of the data memory section 107.

Operation of bus controller 105> First, access using the block access method will be explained. As an example, at the same time that processor 212a reads data from memory block 210a, performs some processing, and writes data to memory block 210p, processor 212b
An example will be explained in which the data is read from the memory block 210a, subjected to separate processing, and written to the memory block 210c. To simplify the explanation, it is assumed that there are no access requests from the other two processors 212c and 212d.

The processors 212a and 212b first set the read mode to the buffers 601a and 601b via the signal line 627, and set the read mode to the buffer 601a and 601b via the signal lines 608a and 608b.
The number of the memory block to be read, ie, the number "0" of the memory block 210a, is stored in 01a and 601b.

Next, similarly, the write mode to the buffer is set via the signal line 627, and the memory block number to be written, that is, the buffer 601a, is set to "FM (memory block 210
p), the buffer 601b! :: stores "2H (indicating the memory block 210c). After that, the buffers 601a and 601b are set to block access mode via the signal line 628. That is, the memory block number is set to the signal line 609a by the access start signal. ,b,
It is sent to 610a and 610b for the first time and is held until an access end signal is input.

In this state, when access start signals are input from the processors 212a and 212b to the buffers 601a and 601b, each block memory number is sent to the delay device 602 and the collision detector 60 through the signal lines 609a, b, 610a, b.
5. As a result, the collision detector 605 compares each block memory number to check whether there is a collision. In this example, it can be seen that there was a collision in accessing the memory block 210a. Therefore, the number of the processor causing the conflict is sent to the controller 607 via the signal line 619.
send to Here, the priority order holder 606 is configured in advance from the main CPU 101 to the system bus interface unit 10.
9. Signal line 214. Register 200. The priority order at the time of collision is stored via the signal line 218 (see above, FIG. 2). Here, it is assumed that the processor 212a has the highest priority, and the processors 212b, 212c, and 212d are given lower priority in this order.

In this way, when the controller 607 learns of the conflict between the processors 212a and 212b, it refers to the priorities in the priority holder 606 and assigns the memory block 2 to the processor 212a.
Allow access to 10a. Therefore, controller 6
07 sends an access enable signal to the processors 212a, 212c, and 212d via signal lines 618a, 618c, and 618d, and sends a wait signal to the processor 212b via a signal line 618b.

The signal line 620 is a line that bundles these four signal lines,
Similar information is also transmitted to gate 603. In this example, the memory block number is sent to signal lines other than signal lines 613b and 614b. Upon receiving this, decoder 6
04 is signal line 313, 312, 1305, 310, 62
1,311 to send a control signal.

The signals output from these decoders 604 will be explained below.

First, the signal 5ELR on the signal line 313 controls the 4-1 selector 309a (FIG. 7) to connect the processor 212a and the memory block 210a. Also,
The signal 5ELW on the signal line 312 causes the 1-4 selector 3 to
08p or processor 212a and memory block 210p
and control the connection. Furthermore, the signal line 1305
When the R/W signal is in the read mode in signal 5ELA of In mode, the 1-16 selectors 1301a-d are controlled so that the address line 1303a of the processor bus 217a is connected to the address line 1.3049 of the memory bus 216p.

Further, the signal DIRB on the signal line 310 is connected to the negative operation buffer 3.
06a is made conductive, and the normal operation buffer 307p is made conductive. Data line 314 of signal DIRP of signal line 311
Regarding a, when the R/W signal is in the read mode, the negative operation buffer of the data line 314a is made conductive (i.e., "o"
), and conversely, in the write mode, the normal operation buffer is made conductive (ie, 1°'). Furthermore, it is a 16-bit RW defect signal on the signal line 621, and is a 16-bit signal for each memory block 210a to 210a.
Each bit is connected to p, and the R/W signal from each processor is sent to the accessed memory block. Thus, when the access end signal is input to buffer 601a or 601b via signal line 628, the number of the next memory block stored in the buffer is output to signal lines 609a, b, 610a, b.

Next, the case of access using the pixel access method will be explained. For example, processor 212a and processor 21
2b performs pixel access, and for the sake of simplicity, it is assumed that there is no access from the other two processors.

The processors 212a and 212b first set the buffers 601a and 601b to pixel access mode via the signal line 628. Next, the processors 212a and 212b set the memory block number to be accessed to the buffers 601a and 601b via the signal lines 608a and 608b. Store. Thereafter, each memory block number is supplied to the delay device 602 and the collision detector 605 via signal lines 609a, b, 610a, and 610b. The collision detector 605 detects whether access requests to the same memory block collide in the same manner as when accessing a block.

Further, upon receiving this result, the controller 607 refers to the priority order and sends an access permission or wait signal to each processor and gate 603 in the same manner as when accessing a block. Based on this, the gate 603 sends the required memory block number to the decoder 604, and the decoder 604 outputs a control signal to each signal line in the same manner as when accessing a block. Thus, processor 212a
and 212b sequentially generate addresses or memory block numbers and output them to the bus controller 105, so the internal state of the bus controller 105 is switched at this timing for each pixel.

Change in system scale> The components within each system are the memory block 210a.
210p and processors 212a to 212d. Therefore, when changing the scale of the system, it is sufficient to simply increase or decrease the number of these circuits. By preparing in advance only the required number of these circuits and actually implementing them, it is possible to easily change the memory capacity and the number of processors. It is also possible to modularize these circuits, processors and their peripheries, and memory blocks and their peripheries so that the memory capacity and the number of processors can be changed as needed.

In addition to the circuit configuration described above, it is also possible to change the hardware, such as adding or removing a latch circuit for timing alignment, and bus collision detection and bus collision avoidance based on priority in the embodiment are limited to this. In addition, in the case where multiple processors read out the same pixel at the same time, it is also possible to use this embodiment, and in this case, the decoder 604 controls the All you have to do is change.

[Example of application utilizing block access] Here, a plurality of calculation elements of the calculation unit 104 of this embodiment are connected and exchanged with the data memory unit 107 using the bus connection/exchange control unit 105 and the bus connection/exchange unit 106. The functions will be explained using an example in which an operation to generate an image using the ray tracing method is executed.

As shown in Figure 13, the ray tracing method searches for the object that first intersects each line of sight passing through each pixel on the screen, and then searches for the object that first intersects each line of sight, and uses the surface color of this object to
The pixel value of each pixel is determined, and the same search method is repeated for each pixel on the screen. Note that it is possible to search between each pixel independently of each other. As can be easily inferred from FIG. 13, it is possible to process images in parallel in block units, with small areas of a plurality of images being treated as blocks.

In FIG. 14, the size of the image to be handled is composed of 2048 pixels x 48 pixels, and is divided into 16 square small areas each consisting of 512 pixels x 512 pixels. These 16 square small areas are numbered and distinguished as MBO-MB15.

In FIG. 2, for each calculation element 211a to 211d, shape data necessary for ray tracing, data expressing the arrangement of each shape, light source data, viewpoint data, screen position, and surface color data of each shape. A program memory 213a includes data describing a three-dimensional world, a program for executing an algorithm for rendering the data, and a screen area to be handled by each processor, and is arranged independently in each processor. ~213d, respectively, are downloaded using the method described above.

Here, the screen area refers to screen 1 in FIG.
Each SBO formed by dividing 101 into 16 areas ~
It is a small area on the screen named 5B15. These small areas 5BO to SB15 on the screen correspond to MBO to MB15 in FIG. 101 to the communication path exchange control unit 1001
(FIG. 3), settings are made as shown in FIG. 15.

In FIG. 15, 1401 indicates a serial communication path connecting the processor 212a and the processor 212b. Similarly, 1402 is the processor 212b and the processor 21
2C, 1403 is a serial communication path between processor 212C and processor 212d, and 1404 is a serial communication path between processor 212C and processor 2C.
12a, 1405 is a serial communication path between processor 212a and processor 212C, and 1406 is a serial communication path between processor 212b and processor 212d. In addition, 1400 is the parallel/serial converter 100 in FIG.
4 and the processor 212a. The parallel processing unit 103 downloads programs and data from the main CPU 101 through this communication path 1400, and also downloads programs and data from the main CPU 101 as necessary.
It communicates with o1.

The following description will be made based on the flowcharts shown in FIGS. 16 to 18. FIG. 16 is expressed as a program related to the processor 212a. The processor 212a processes small areas SBO, SB4 . SB8,5B1
2 is defined as the implicit processing area allocation. Further, the processor 212b includes SBI, SB5. SB9,5
B13, and SB2.B13 to the processor 212C. SB6,5
BIO, 5B14 or processor 212d has SB3.
SB7. SBI 1.5B15 is allocated as implicit processing area.

Processing starts in step S1. A small area SBO allocated as an implicit processing area of the processor 212a,
SB4. SB8. A flag indicating whether or not it is an unprocessed area for each block of [SB]2 (hereinafter, SBO processing flag, SB4 processing flag, SB8 processing flag, 5B1)
2 processing flag) is prepared.

In step S2, all these flags are reset, SBO, SB4 . SB8.5B12 initializes the flags, assuming that all are in an unprocessed state. In step S3, an unprocessed small area (hereinafter referred to as an empty area) is searched for according to the flowchart shown in FIG.

FIG. 17 is a flowchart showing the process of searching for this free area. Here, the flag corresponding to each small area is checked, and if it has been reset, the processing flag for that small area is set.
The block number of the small area is set in the processing block number register. Also, if there is an empty area in either of the small areas, a flag indicating the existence of an empty area (hereinafter referred to as an empty area existence flag) is set, but if there is no empty area, this empty area Reset the existence flag to clearly indicate that the empty space does not exist.

In step S4, it is determined whether or not there is a free space based on the state of the free space existence flag in step S3. If there is an empty area, the process proceeds to step S5; otherwise, the process proceeds to step Sll. In step S5, rendering processing is performed on the empty area specified by the empty area number stored in the processing block number register. Next, the process proceeds to step S6, in which it is determined whether or not there has been an inquiry from another processor via the serial communication path as to whether or not there is an empty area in the implicitly allocated processing area of the processor 212a. There is. If there is no inquiry, step S3
If there is an inquiry, the process goes to step S7.

In step S7, as in step S3, the existence of an empty area is checked and a empty area existence flag is set. If an empty area exists, the empty area number is set in the empty area number register. Next, the process proceeds to step S8, and the determination result in step S7 is examined based on the empty area existence flag. If an empty area exists, the process proceeds to step S9, and the empty area number is returned to the processor that has made an arrangement, and the process proceeds to step S6. return. on the other hand,
If there is no empty area, the process advances to step SIO, where a reply is sent to the processor that has arranged that there is no empty area, and the process returns to step S6.

On the other hand, if there is no free space in step S4, step S
Proceed to ll. At this time, all the small areas implicitly allocated to the processor 212a are no longer in an unprocessed state. Here, in order to ask other processors about the existence of empty space, the number of the other processor to be asked is set in the makeshift processor number register. Next, the process advances to step S12, and the presence or absence of an empty area is determined for the processor specified by the temporary processor number register,
If another processor has an empty area, the empty area is rendered. If there is no empty space, step S1
After completing the process of step 2, the process advances to step S13. Step S1
Further, in No. 2, when there is an inquiry about an empty area from another processor during the above processing, the processor replies that there is no empty area.

Next, the process advances to step S13, and the other processor number to be asked next is set in the makeshift processor number register. Then, in step S14, the same process as in step S12 is performed on the processor pointed to by the processor number set in the makeshift processor number register.

Next, in step S15, another processor number is set in the makeshift processor number register, and in step S16, the same processing as in step S12 and step S14 is performed. In this example, the processor 212b is activated in step Sll, and the processor 2 is activated in step S13.
12c, and the processor 212d is specified in step S15. Also, step S12. S14. S16 has the same processing content, and the details are shown in FIG.

FIG. 18 is a flowchart showing the process of determining whether or not there is free space in the processor that has been instructed to do so.

First, when the process is started in step S21, step S2
In step 2, it is determined whether there is free space in the processor specified by the make-up processor number register. Check whether there is a response in step S23, and if there is no response yet, step S23
Proceed to 24. In step S24, it is determined whether there is an inquiry about the empty area from another processor. If there is an inquiry about the empty area from another processor, step S25
The process proceeds to step S24, and replies to the processor that has arrived in time that there is no empty space, and returns to step S24.

If there is no inquiry about the empty area in step S24, the process returns to step S23, but if there is a response, the process proceeds to step S26. In step S26, it is determined whether there is an empty area,
If there is an empty area, the process advances to step S27, and if there is no empty area, the process advances to step S30. In step S27, it is determined whether or not there is an inquiry about free space from another processor. If there is an inquiry, the process advances to step S28, and a reply is sent to the incoming processor that there is no free space. Return to step S27. On the other hand, if there is no inquiry from another processor in step S27, the process advances to step S29, where the free space of the other processor received in response is subjected to rendering processing, and the process returns to step S22. Step S26
If there is no empty area, the process proceeds to step S30, where it is determined whether or not an inquiry has been received from another processor as to whether or not there is an empty area in the implicitly allocated area. , in step S31, it replies that there is no empty area and returns to step S30. If no inquiry has been received in step S30, the luck process is ended and the process returns to the main routine.

The above has been explained using the program for the processor 212a as an example, but the program for the processors 212b to 212d has been explained above.
, the program is completely similar, except that the small area that is implicitly allocated to the program is different, and the processor number that determines whether there is an empty area is different.

In this way, all the small areas on the screen shown in FIG. 13 are processed.

(Left below) [Transfer of image data from data memory to video frame memory] Here, in order to display the image data stored in the data memory 1.7 in the calculation unit 103 on the monitor display 111, The process of transferring image data to the video memory 110 at high speed will be explained using FIGS. 1 and 20. FIG. 20 is an excerpt from FIG. 1 of only the parts necessary for this embodiment. Components that operate in the same way as in FIG. 1 are designated by the same numbers.

Reference numeral 1010 denotes an address generator, which is a combination of the high-speed bus I/F section 108 and the system bus I/F section 109 in FIG. Reference numeral 107 denotes a data memory section in the calculation section, which is a memory section that stores image data for calculation. In order to simplify the explanation, in this example, 2048X2
048 pixels.

It is assumed that R, G, and B image data each have an 8-bit configuration. 1011 is an address generator, address generator 1
It is similar to 010. A video frame memory 1012 is a memory that stores image data to be displayed on the monitor display 111. To simplify the explanation, in this example, 1280 x 1024 pixels,
It is assumed that R, G, and B of one pixel each have a configuration of 8 bits.

A display converter 1013 performs D/A conversion of digital video image data stored in the video frame memory 1012 into an analog image. 111 is, for example, C
This is a monitor such as an RT display device, and displays images according to analog signals. In this example, the monitor resolution is set to 12
80×1024 pixels.

First, to explain the general operation, the operator enters information such as the start address in the data memory section to be transferred, the number of pixels in the main scanning/sub-scanning direction of the transfer area, and the start address in the video frame memory of the transfer destination, etc. for this transfer process. Necessary information is specified using a pointing device such as a keyboard or mouse (not shown). Based on this information, the main CPU 1.01 issues an address generator 1010 in the corresponding parallel processing unit 103 via the system bus 116.
and address generator 1 in video frame memory 110
011 to that effect, and the image data is transferred at high speed via the high-speed image transfer bus 117.

The operating principle will be explained in detail below.

FIG. 21 is a block diagram showing the configuration of address generators 1010/1011.

In the figure, 10200 is a bidirectional data multiplexer (MPX) that switches the flow of system data and image data. Similarly, 10201 is a multiplexer and switches between a system address and an internally generated address. The parallel processing unit 103 is composed of, for example, a DRAM, and can read and write image data at high speed according to a strobe signal.

On the other hand, 10205 is a Y register, which holds the Y address at which image data transfer starts. 10203 is RON
(row) counter, vertical synchronization (V-s) for transfer
ync) signal 10215 causes Y register 10205
After that, it is incremented by 1 by the horizontal synchronization (I-Sync) signal 10214 for transfer. Reference numeral 10204 denotes an X register that holds an X address at which to start transferring image data. 10202 is column 1 (column) counter, and ! -1-5 sync signal 10
214 to load the contents of the X register 10204, and then clock (CLK) signals 1-0 for transfer.
It is incremented by 1 by 213. 10207.
10208 is a shifter, which outputs each counter 10202, 10203 according to a command (internally generated address)
shift. 10206 is a control register, and column counter 10202. It holds information on which direction and how many bits to shift the output of the row counter 10203. That is, if register 10206=O, the MO” bit;
If =-1, shift "l" bits in the lower direction, and if =1, shift "1" bits in the upper direction. The same applies hereafter.

Also, l○209 and 10210 are registers, and shifter 1
10211.10, which holds address data to be added to the address information passed through 0207 and 10208, respectively.
212 is an adder, and shifters 10207 and 10208
Address information and register 10209.102 passed through
Add the contents of 10 respectively.

On the other hand, 10221 is a Y length register that holds the transfer Y length of image data. Reference numeral 10219 is a Y counter, which is incremented by 1 each time an H signal 10214 is input after being cleared by the ■ signal 10215. A comparator 10220 outputs a logic level signal while the content of the Y counter 10219 is smaller than the content of the Y length register 10211. Further, 10218 is an X length register which holds the transfer X length of image data.

10216 is a counter which is cleared by the H signal 10214, and after that, it is cleared every time the clock signal 10213 is input.
1 will be given. 10217 is a comparator, and X counter 10
While the contents of 216 are smaller than the contents of X length register 10218, a logic level signal is output. 10222
is an AND circuit, and comparators 10220 and 10217
The output of the logic level and the opening of the logic level output the chip enable signal CE to the RAMIO12. Therefore, this C
While the E-blemish signal is being output, image data can be written to the RAM 1012 in synchronization with the strobe signal.

A specific example of the transfer operation will be described below.

Same-size transfer> Arbitrary (12
80X 1024) Transfer the area of the pixel valve to the video frame memory 1012 at the same size. In this case, the main CPU
101 performs the following initial settings.

[Data memory section] X register 10204=X transfer start address Y register 10203=Y transfer start address MPX 10200=
High-speed image transfer bus connection MPX10201 = Internal address use register 10206 = 0 Register 102o9, register 10210 = OX length register 10218 = 1280Y length register 1
0221=1024 [Video frame memory] XL/Jister 10204=O Y register 10203=O MPXO203=O High XO203=O High speed 20 starts, the address X. of the data memory section 107 is set. Starting with Y (1280X1
024) Image data of pixel valve is stored in video frame memory 1
High-speed image data is transferred to the area starting at address 012 (0.0).

Thinning out transfer> Arbitrary (12
80Xl○24) Thin out the pixel valve area to 1/2,
Transfer to video frame memory 1012. In this case, the main CPU 101 initializes as follows.

[Data memory section Register 10221==1024 [Video frame memory code X register 10204=O Y register 10203=O MP10203=O High-speed image transfer bus connection MPX102
01=Internal address use register 10206.10209.10210=O /Starting with X, Y (128
Image data for pixels (0x1024) is thinned out and transferred to the area starting at address (0,0) of the video frame memory 1012. This thinning is performed by
, Y are both 1-bit shifts in the upper direction, so
, 1/2 in the Y direction.

In this section, we will consider the case where image data is transferred in batches.

FIG. 22 is a conceptual diagram illustrating the image data transfer operation of this embodiment.

In the figure, 1031 is a part of the data memory section 107;
Reference numeral 1033 indicates a part of the video frame memory 1012. Note that the contents of the video frame memory 1012 are cleared in advance. If K=4 times, the image data 1031 in the data memory 107 is divided into blocks for each (2×2) pixels, for example, the first time is all of the ○ marks, the second time is all of the Δ marks, 3
The 4 screens are transferred in order, such as all of the X marks are transferred the first time, all of the 0 marks are transferred the fourth time, and so on. By transferring in this manner, it is possible to quickly grasp the general image of the entire O mark on the monitor 111 at the end of the first transfer. Furthermore, the time required to transfer the image data at this time is 1/4 compared to the case where all image data is transferred.

As another example, image data 1 in the data memory 107
032 and image data 1 of video frame memory 1012
There is a relationship of 033. In this case as well, the image data 1032 in the data memory 107 is thinned out and transferred as shown in the figure, so that the video frame memory
The image data 1033 of 012 is reduced to 1/2 in both the X and Y directions.

A specific example of the transfer operation at this time will be explained.

<Four division equal size transfer> Starts at address (0,0) of data memory section 107 (
Image data for 1280×1024) pixels is transferred to the area starting at address (0, O) of the video frame memory 1012 at the same size, and K=4 times. In this case, the main CPU 1o1 makes the following initial settings. It should be noted that unless otherwise specified, the explanation will be made in the same manner as in the above-mentioned embodiment.

[Video frame memory] X register 10204 = 0 Y register 10203 = 0
01 = Internal address used [Data memory section X register 10204 = O Y register 10205 = 0 Register 10206 = + The contents of raster 10209.10210 differ for each transfer.

When transferring image data marked O, register 10209=0 Register 10210=0 When transferring image data Δ, register 10209=register 1021020 When transferring image data marked X, register 10209=0 Register 10210=1 Image When transferring the data row mark, register 10209 = register 1021021 <Four division thinning transfer> In this case, both X and Y are 1/2 times, and K = 4 times. In this case, the main CPU 101 performs initial settings as follows.

[Data memory section] Register 10206 = +2 Similarly, the contents of registers 10209 and 10210 are transfer 1
Different each time.

When transferring image data marked with ○, register 10209 = 0. Register 1021020. When transferring image data marked with Δ, register 10209 = 2. Register 10210 = 0. When transferring image data marked with X, register 10209 = 0. Register 10210 = 2. When transferring the data log mark, register 10209 = 2 register 10210 = 2 In this embodiment, the data memory 107 of the parallel operation unit 103
Although we have explained the image data transfer between the video memory 110 and the video memory 110, it is easy to infer that it can also be used to transfer image data between the data memory sections when a plurality of parallel processing sections 103 exist in the same system. can.

Furthermore, in this embodiment, the size of the image data to be transferred is 1
Although the explanation has been made using 280x1024 pixels, it can be inferred that the size is not limited to this. Furthermore, the number of divisions and the thinning rate during divided transfer and thinned-out transfer are not limited to these.

As in the system of this embodiment, by distributing the data memory unit 107 and the video memory 110 and waiting, the image size of the data memory 107 of the parallel processing unit 103 can be adjusted to the resolution of the monitor display 111, Regardless of the data size of the memory 110, a data memory of any size, for example 1024×1024 pixels, 2048×
It is possible to connect 2048 pixels, 4096x4096 pixels, etc.

[Transfer of image data from large-capacity external storage device to data memory] Here, the process of transferring image data stored in the large-capacity external storage device 102 to the data memory unit for parallel calculation will be explained as shown in FIG. , and FIG. 19.

First, the operator specifies the information necessary for this processing, such as the image data file name 1 to be processed, the number of pixels in the main scanning and sub-scanning directions of the image data, and the address in the data memory section of the transfer destination, using a keyboard or the like (not shown). . As a result, the main CPU 101 accesses the corresponding image data file in the large-capacity external storage device 102, reads out the image data, and transfers the image data to the data memory section 10 via the system bus 116.
Image data is written to the corresponding address in 7 according to the image data in the data memory section 107.

To explain in detail, it is assumed that image data is stored in the large-capacity external storage device 102 as one-dimensional image data. To simplify the explanation, it is assumed that the image data is composed of 8 bits each of R, G, and B, and is stored in the external storage device 102 in pixel order. It is also assumed that the data structure of the data memory section 107 is one pixel of 24 bits, with R, G, and B in the order of every 8 bits.

In order to store the one-dimensional image data stored in the large-capacity external storage device 102 as two-dimensional image data in the data memory unit 107, the main CPU 101 performs processing according to the flowchart shown in FIG.

First, the CPU 101 opens the file specified in step S41, and calculates the starting address in the data memory specified in step S42. Thereafter, in step S45, one line of image data, in the case of this embodiment, the number of pixels in the main scanning direction (the number of bytes of R, G, B = 3 bytes) is read from the system bus 116, and in step S46, the data memory 107 One line of image data is written above.Next, in step S47, the start address of the line is calculated. After this process is repeated for the number of lines in the sub-scanning direction, in step S44, the process is repeated the number of times corresponding to the scanning lines of one screen, and then the process proceeds to step S49, where the image data file being opened is closed and the process ends. .

In this embodiment, the case where image data is loaded has been described, but it can be easily inferred that image data can also be stored. Furthermore, it can be easily inferred that the data structure of the image data stored in the external storage device 102 and the image data structure on the data memory 107 are not limited to the data structure described above.

Other Embodiments Here, processors 212a to 212a in the calculation unit 104
The operation when d is connected in series and connected in a pipeline manner will be explained using FIGS. 2 and 23. Figure 23 shows
It is a conceptual diagram of this example.

In FIG. 23, parts that perform the same operations as in FIG. 2 are given the same numbers.

In the figure, 10400.10401 indicates access between the processor and block memory, and 10402° and 10403 indicate access between the processor and block memory.
It shows the serial communication path between processors. In this example, each processor is made to perform separate processing, the calculation result of one processor is used as input data to another processor, and each processing is performed continuously.

As an application of this example, in this embodiment, each of 8 bits of R (red), G (green), B (blue), and W (additional information) stored in the data memory unit 107, that is, 1 pixel and 4 bytes, is used. When sequentially processing the above three types of processing, consisting of "color conversion processing" of image data, and "conversion processing from rRGB data to YMC data for outputting to a color printer" after "enlargement processing" of the image data, think of. Each processing flow is shown as a flowchart of program memories 213a-c in FIG. 23.

To simplify the explanation, the size of the image data to be processed is 1024 x 1024 pixels, with 4 bytes per pixel, and the size of one block memory in the data memory section 107 is 1 Mbyte (512 x 512 pixels x 4 hides). shall be. The image data to be processed is transferred in advance to the block memory MB○ (210a) in the data memory section 1.7, for example, through a system bus or a high-speed image data transfer bus.
M B 1 (210b), M B 4 (210e
), M B 5 (210f). Further, it is assumed that each processing program has already been stored in the external storage device 102.

First, the operator performs the above three types of image processing, for example, the processor 212a or the "color conversion process", using the processor 21
2b performs "enlargement processing", processor 212C performs rRGB
1 to the effect that the conversion process from data to YMC data will be performed.
It is assumed that the designation is made using a keyboard (not shown) or the like. In addition, in this embodiment, the processor 212a uses MB
The image data is read from O, 1, 4, and 5, and the processor 2
12c or, for example, the four blocks MB2, 3, and 6.7, are designated to be allocated to output the calculation results.

Further, setting the serial communication path of the processor, in this embodiment, the serial communication path on the output side of the processor 212a is connected to the serial communication path on the input side of the processor 212b, and the serial communication path on the output side of the processor 212b is connected to the serial communication path on the input side of the processor 212b.
Specify to connect to the serial communication path on the input side of 2C.

With this designation, the main CPU 101 downloads each program stored in the external storage device 102 to the designated processor using the means described in the section [Downloading programs to each processor] above. do. Furthermore, the serial communication path of each processor is set by using the means described in the above-mentioned section ``Method of Setting Connection Status of Processor Communication Path''.

After these initial settings, each processor starts its own processing. First, the processor 212a uses the block memory 1
The image data stored in 07 is accessed based on the method described in the section of [Block access method] and the image data is sold. Then, a predetermined process according to the program code stored in the program memory 213a, for example, in the case of this embodiment, 2 in FIG.
Color conversion processing is performed in accordance with the flowchart shown at 138.

Thereafter, the image data of the calculation result is outputted to the serial communication path on the output side of the processor 212a at any time. On the other hand, the processor 212b reads the image data processed by the processor 212a, that is, the image data that is input from the serial communication path on the input side, and stores it in the program memory 212.
The processor 21 performs predetermined processing according to the program code stored in
Similarly to 2a, the image data of the calculation result is outputted to the serial communication path on the output side at any time. Furthermore, like the processor 212b, the processor 212c also reads image data that is input from the serial communication path from time to time, and stores it in the program memory 2.
13c, a predetermined process according to the program code stored in the program memory 2
The RGB-YMC conversion stored in 13c is performed, and the image data is written to the pixel position in the corresponding block memory based on the method described in the above-mentioned [Block access method] section.

As shown in this embodiment, by using the serial communication path that each processor has, it is possible to perform processing in which a plurality of processors are connected in a pipeline manner.

In this embodiment, an example has been described in which the intermediate processor 212b does not use the image memory, but it can be easily inferred that the present invention can also be applied to a case where the intermediate processor 212b uses the image memory.

Also, in this example, there were three processors, but
It can be easily inferred that this number is not limited to this number. Furthermore, although the block memory on the input side and the block memory on the output side have been explained as separate areas, if they are the same area, it is possible to do so by using the means described in the section [Bus controller operation]. Become. It can be easily inferred that the memory access method of the processor that accesses the block memory is not limited to "block access", but may also be the method described in the section [Pixel Access Method].

Note that although this embodiment has been described in the case of an image processing device, the present invention is not limited thereto, and can be applied to various arithmetic devices.

As explained above, according to this embodiment, there is a bus connection/exchange unit and a bus connection/exchange unit between the arithmetic processing unit and the data memory unit.
By providing an exchange control section, a parallel operation section with high flexibility for parallelizing image operations can be configured. Furthermore, by having a video frame memory separate from the parallel processing section, it is possible to configure a configuration in which the image size handled by the system does not depend on the display device. Furthermore, by transferring image data using a high-speed image transfer bus, it has become possible to save the time required to transfer images.

[Effects of the Invention] As described above, according to the present invention, there is an effect that there is flexibility in various data operations, and that memory can be effectively utilized to perform parallel operations at high speed.

[Brief explanation of drawings]

Figure 1 is a block diagram showing the schematic configuration of the image processing system of this embodiment, Figure 2 is a diagram explaining the configuration of the parallel processing unit in more detail, and Figure 3 is the exchange and control of serial communication paths between processors. FIG. 4 is a diagram for explaining the 7-Dremasetting of the data memory section. FIG. 5 is a conceptual diagram of the memory block. FIG. 6 is a diagram showing the structure of address data generated by the processor. Figure 7 is a diagram showing details of the data signal line of the bus selector, Figure 8 is a diagram showing details of the address signal line of the bus selector, Figure 9 is a detailed diagram of the 1-16 selector, and Figure 10 is a diagram showing details of the 1-4 selector. A detailed diagram of the selector. Figure 11 is a detailed diagram of the 4-1 selector. Figure 12 is a detailed diagram of the bus controller. Figure 13 is a diagram for explaining the principle of the ray tracing method. Figure 14 is a diagram of the memory block. Conceptual diagram. Figure 15 is a diagram for explaining the connection state of the serial communication path of the processor. Figure 16 is a flowchart for explaining parallel calculation processing using block access. Figure 17 is a diagram for searching for an empty area and calculating the empty area number. FIG. 18 is a flowchart showing the process of searching for empty space in other processors, FIG. 19 is a flowchart showing image data transfer from a large-capacity external storage device to data memory, and FIG. 21 is a detailed diagram of the address generator, 22 is a conceptual diagram illustrating thinning transfer, and 23 is a conceptual diagram illustrating transfer of image data from data memory to video frame memory. FIG. 2 is a conceptual diagram illustrating pipeline processing in an embodiment. In the figure, 101... Main CPU, 102... Large capacity external storage device, 103... Parallel processing unit, 104...
Parallel calculation unit, 105... Lotus connection/exchange control unit (bus controller), 106... Lotus connection/exchange unit (path selector), 107... Data memory unit, 108...
・System Has I/F section, 109...highway bus I
/F section, 110... Video memory section, 111... Video display, 115... Image scanner, 1
16...System Has, 117...Highway bus, 20
0...Register, 212a-212d...Processor, 601a-601d...Buffer, 602...
Delay circuit, 604...decoder, 605...collision detector, 607...controller. Patent applicant: Canon Co., Ltd. Figure 4 rSlo Figure 11 Figure 14 Figure 19 r Figure 20 Figure 22

Claims (6)

[Claims] (1) A plurality of programmable computing elements, communication means for connecting the computing elements, memory means independently accessible from each of the computing elements, and operating each of the computing elements independently. A parallel arithmetic device comprising: a control means for controlling access to the memory means by the arithmetic element; (2) The control means sets a priority order for each of the calculation elements, and determines an accessible calculation element according to the priority order when access requests from the calculation elements to the memory means conflict. 2. The parallel computing device according to claim 1, characterized in that: (3) The parallel computing device according to claim 1, further comprising program loading means capable of downloading a control program to each of the computing elements. (4) The memory means is divided into a plurality of memory blocks, and the control means allocates one or more memory blocks to each of the calculation elements and determines the priority order for each memory block. 3. The parallel computing device according to claim 2, wherein the parallel computing device is configured as follows. (5) A claim further comprising access means capable of setting a mode in which the arithmetic means accesses each memory block unit of the memory means and a mode in which it accesses each minimum storage unit element of the memory means. Parallel computing device according to item 1. (6) Claim 1, characterized in that the number of calculation elements and the capacity of the memory means can be changed independently.
Parallel arithmetic device as described in section.