JP5165081B2 - Game machine - Google Patents

Description

  The present invention is a gaming machine equipped with an image display device, specifically a “pachinko gaming machine” (generally also referred to as “pachinko machine”), a “rotating gaming machine” (generally also referred to as “pachislot machine”). Etc.) related to gaming machines installed in the gaming hall.

  Conventionally, in a gaming machine equipped with an image display device, a plurality of types of image data displayed on the image display device are stored in the image data storage means, and when performing image display, the image data is read from the image data storage means. It was displayed after image processing. (For example, see Patent Document 1)

JP 2001-252432 A

  By the way, in recent gaming machines, the contents of display on the image display are becoming increasingly diversified and complicated in order to enhance the gaming interest of the player, and accordingly, the images stored in the image data storage means The capacity of data is steadily increasing, and the need for a large-capacity storage medium is increasing.

  A flash memory is known as a large-capacity storage medium. Among flash memories, a NAND flash memory has recently been promoted especially in a large capacity, and is very suitable for use as a storage medium for image storage in gaming machines. It is.

  However, due to the nature of the NAND flash memory, the occurrence of a defective data block into which data cannot be written is unavoidable, and there is a problem in dealing with the data reading process due to the presence of the defective data block.

  An object of the present invention is to provide an effective data storage method and data read method when a NAND flash memory is used as image data storage means of a gaming machine.

  In order to solve the above-described problems, a gaming machine according to claim 1 of the present invention is a game machine having an image display device, wherein the gaming machine includes a main control device that controls a gaming state of the gaming machine; A sub-control device that controls a game effect based on an effect control command signal output from the main control device; and a display control that controls the image display device based on a display control command signal output from the sub-control device. A first arithmetic processing means for performing the effect control command processing, a game control program storage means for storing a game control program, and game control data are temporarily stored in the main control device. Game control data temporary storage means, and the game control program storage means and the game control data temporary storage means are connected to the first arithmetic processing means, and the display control device includes: Second calculation processing means for executing a display control program, display control program storage means for storing the display control program, display control data temporary storage means for temporarily storing display control data, and the image display Image processing means for controlling an image displayed on the apparatus, image data storage means for storing image data for displaying the image, and display data for the image displayed on the image display apparatus are temporarily stored The display control program storage means, the display control data temporary storage means and the image processing means are connected to the second arithmetic processing means, and the image A data storage means and the image display data temporary storage means are connected to the image processing means, and the image data storage means includes a NAND type flash memory. The NAND flash memory includes a plurality of data blocks, and when a defective data block exists in the plurality of data blocks, the NAND flash memory includes a data block immediately before the defective data block. The next image data of the stored image data is stored in the data block immediately after the defective data block in a state avoiding the defective data block, and the arbitration circuit responds to the image data read request from the image processing means. Converting the start address of the image data stored in the data block after the defective data block into an address next to the final address of the image data stored in the data block before the defective data block, and outputting the converted data. It is configured as a featured gaming machine.

  The gaming machine according to claim 2 of the present invention is “when the image processing means includes a NAND flash memory control circuit that performs a data read command control from the NAND flash memory and reads image data from the image data storage means”. The game machine according to claim 1, wherein data relating to a plurality of types of images is read in a batch, and the plurality of types of image data read in a batch are temporarily stored to perform image processing. Configured as

  In the gaming machine according to claim 1 of the present invention, the image storage means includes a NAND flash memory and an arbitration circuit, and when a defective data block exists in a plurality of data blocks of the NAND flash memory, The image data next to the image data stored in the data block immediately before the defective data block is stored in the data block immediately after the defective data block in a state avoiding the defective data block, and the arbitration circuit receives the image from the image processing means. In response to a data read request, the start address of the image data stored in the data block after the defective data block is converted to an address next to the final address of the image data stored in the data block before the defective data block and output. To do.

  Since the data that should have been originally written in the defective data block is written in the data block immediately after the defective data block, the arbitration circuit simply skips the address of the defective data block when performing the data reading process. Data can be read continuously in the process, and the data that should have been written to the defective data block is stored in another storage area prepared in advance, and the original data is A so-called swap processing mode in which data that should have been written to a block is read after jumping to the address of the storage area where the data is stored, and then returning to the address of the next data stored in the regular storage area again Compared to the above, it is possible to reduce the processing load and to prevent the reading speed from being lowered.

In the gaming machine according to the second aspect of the present invention, since the image processing means includes a NAND flash memory control circuit that performs a data read command control from the NAND flash memory, image data is stored from the image data storage means. When reading, data related to a plurality of types of images can be read at once. In addition, since the plurality of types of image data read in a batch are temporarily stored and image processing is performed, the number of times the arbitration circuit performs data address conversion processing can be reduced, and the processing load can be reduced.

It is a block diagram of the control apparatus of the gaming machine of the present invention. It is a conceptual diagram of the internal configuration of the image processing means and image data storage means of the present invention. It is a data storage system conceptual diagram in the case of a swap system. It is a data storage system conceptual diagram of the present invention. It is a conceptual diagram of the data storage system in the built-in RAM area of the image processing means in the present invention.

  Hereinafter, an embodiment of the present invention will be described with reference to the drawings. Note that the basic configurations of the “pachinko gaming machine” and the “rotary gaming machine” are well known, so that the description thereof will be omitted and only the essential points of the present invention will be described.

  FIG. 1 is a block diagram of a control device for a gaming machine according to the present invention. The main control device 1 is a control device that controls the entire game of the gaming machine, and includes a CPU 1 (corresponding to “first arithmetic processing means” of the present invention) and a ROM 3 (“game control program storage means” of the present invention). And a RAM 4 (corresponding to “game control data temporary storage means” of the present invention).

  In the gaming machine of the present invention, when a predetermined gaming condition occurs (for example, in the case of a “pachinko gaming machine”, a pachinko ball has been won at a starting winning opening arranged on a well-known gaming board surface), so-called jackpot A lottery is performed as to whether or not a game is to be generated, and an image display effect is provided on the image display device 30 in accordance with the lottery result.

  When the predetermined game condition occurs, the main control device 1 transmits an effect control command signal (command) to the sub-control device 10 via a communication circuit (not shown).

  The sub-control device 10 that has received the effect control command signal transmits a display control command signal (command) to the display control device 20 via a communication circuit (not shown) based on the received effect control command signal. At the same time, an illumination device and a speaker (not shown) mounted on the gaming machine are controlled to produce an effect by light and sound.

  The display control device 20 includes a CPU 21 (corresponding to “second arithmetic processing means” of the present invention), a ROM 22 (corresponding to display control program storage means of the present invention), a RAM 23 (“display control data” of the present invention). (Corresponding to “temporary storage means”), VDP 24 (corresponding to “image processing means” of the present invention), character ROM 25 (corresponding to “image data storage means” of the present invention), and RAM 26 (“image display means” of the present invention). Equivalent to “temporary data storage means”.

  When the CPU 21 receives the display control command signal, the CPU 21 reads the display control program from the ROM 22 and starts display control, and instructs the VDP 24 to execute image processing. The RAM 23 is storage means for temporarily storing display control data for display control processing.

  The VDP 24 instructed to perform image processing starts image processing based on a program stored in an internal storage area (not shown), and an image to be displayed on the screen of the image display device 30 is read from the character ROM 25. The read image is subjected to image processing such as synthesis processing on the read image, and image display data is temporarily stored in the RAM 26, and the image display data is stored in the image display device 30 via a D / A converter (not shown). Send and display the image.

  FIG. 2 shows the internal configuration of the VDP 24 and the character ROM 25. The VDP 24 includes a NAND flash memory control circuit 27 therein. The NAND flash memory control circuit 27 is a circuit for controlling data reading from the NAND flash memory 29 provided in the character ROM 25. When data is read from the NAND flash memory 29, a process for collectively reading display data for a plurality of types of images is performed according to instructions from the NAND flash memory control circuit. The display data for a plurality of types of images read in a batch is stored in a built-in RAM area (not shown) provided in the VDP 24, and the VDP 24 performs image processing using the image display data stored in the built-in RAM area. As described above, the VDP 24 collectively reads display data for a plurality of types of images from the NAND flash memory 29, stores the read image display data in the built-in RAM area, and stores an image based on the stored image display data. Even when there is a defective data block in the NAND flash memory 29 for processing, the arbitration circuit 28 can reduce the frequency of executing data address conversion by the method described later, and the processing load can be reduced.

  A data storage system in the NAND flash memory 29 of the present invention will be described with reference to FIGS. FIG. 3 schematically shows a so-called “swap type” storage method, and FIG. 4 also schematically shows a data storage method of the NAND flash memory according to the present invention.

  In FIG. 3, the data storage area 50 is composed of a plurality of data blocks as represented by data blocks 51 to 57. Here, it is assumed that the image display data includes one image data composed of four data blocks A to D. Furthermore, it is assumed that a plurality of image data is constituted by a plurality of subsequent data blocks. In FIG. 3, data A is stored in the data block 51, data B is stored in the data block 52, and data block 53 is a defective block, so no data is stored. Data C that should have been stored is stored. The data E stored in the data block 55 and the data Z stored in the data block 56 are data for displaying images different from the images formed by the data A to D, respectively.

  In the storage method of FIG. 3, data cannot be written because the data block 53 is a bad block, and data C that should originally be stored in the data block 53 is stored in the data block 57 that is a separate address. . In such a case, when the VDP 24 tries to read an image composed of the data A to D via the arbitration circuit 28, the data A is first read from the data block 51, and the data B is then read from the data block 52. One image cannot be displayed unless the data C is read out to the address and the data D is read again after returning to the address of the data block 54.

  On the other hand, in the data storage method of the present invention shown in FIG. 4, data A is stored in the data block 41 of the storage area 40, data B is stored in the data block 42, and the data block 43 is a defective block. Data C is stored in the data block 44, and data D is stored in the data block 45. Similarly to the case of FIG. 3, the data block 46 stores data Z which is data of another image.

  In the data storage system of the present invention shown in FIG. 4, the image data are arranged in order in order except for the data block 43 which is a defective block. In particular, since the data C that should originally be stored in the data block 53 is stored in the data block 44 next to the data block 43 that is a defective block, the data is read when the VDP 24 reads the data via the arbitration circuit 28. Data A to D for displaying one image can be read simply by skipping the block 43, and it is not necessary to perform a process of reciprocating the data address as in the case of FIG. 3, thus reducing the processing load. be able to.

  FIG. 5 shows a data storage system in the built-in ROM area of the VDP 24. By the processing of the arbitration circuit 28, data is arranged in an orderly manner between the data blocks 61 to 66 in the built-in RAM area of the VDP 24 as shown in the figure. As described above, when the VDP 24 reads a plurality of image data at once, the frequency at which the arbitration circuit 28 converts the data address can be reduced, and the processing efficiency can be improved.

  In this embodiment, the “pachinko gaming machine” has been described as an example. However, the present invention is a variation of the “pachinko gaming machine” such as the “arrange ball” in addition to the “rotating game machine”. However, the present invention can be applied to any gaming machine installed in the gaming hall and equipped with an image display device.

The ROM 3 and RAM 4 may be built in the CPU 2. Similarly, the ROM 22 and RAM 23 may be built in the CPU 21. The term “connect” as used in the present invention includes not only those connected from the outside by wiring but also those in which the CPU, ROM, and RAM are connected inside the element, such as a one-chip microcomputer.

DESCRIPTION OF SYMBOLS 1 Main controller 20 Display controller 24 Image processing means 25 Image data storage means

Claims (2)

A gaming state of the gaming machine is controlled, and when a predetermined gaming condition occurs, a lottery is performed to determine whether or not a big hit game is generated, a lottery result is obtained, and an effect control command process is performed in accordance with the lottery result Main control means having arithmetic processing means, game control program storage means for storing game control programs, and game control data storage means for temporarily storing game control data, and display control means according to the lottery result An image display means controlled by display, and a game machine that produces an image display effect by the image display means.
The display control means includes
Second arithmetic processing means for executing display control processing in accordance with the lottery result;
Display control program storage means storing a display control program for executing the display control processing;
Display control data temporary storage means for temporarily storing display control data;
Image data storage means for storing image data;
In accordance with an instruction from the second arithmetic processing means, images of a plurality of types displayed on the image display means for performing image processing of a plurality of types of images for performing the image display effect according to the lottery result Processing means;
A RAM for temporarily storing the image data used by the image processing means for image processing;
The image data storage means integrally includes a NAND flash memory and an arbitration circuit, and functions as a character ROM.
The NAND flash memory is composed of a plurality of data blocks each storing the image data, and when there is a defective data block in the plurality of data blocks, the NAND flash memory is adjacent to the defective data block. The second image data related to the first image data stored in one data block is adjacent to the defective data block in a state avoiding the defective block data which is a block that should be stored originally, and the first image data Stored in a second data block different from the data block,
The image processing means outputs an image data read request to the arbitration circuit of the image data storage means based on an instruction from the second arithmetic processing means, and is image data stored in the NAND flash memory. Image data batch reading means for collectively reading a plurality of data blocks of the image data of the plurality of types of images displayed in the image display effect according to the lottery result, and storing them in the RAM;
In response to an image data read request by the image data batch reading means, the arbitration circuit skips the defective data block after the first image data stored in the first data block of the NAND flash memory. Then, a plurality of data blocks of the image data of the plurality of types of images are read out so as to read out the second image data stored in the second data block, and the image data of the plurality of data blocks is read into the RAM. Is remembered again so that
The image processing means includes
The image data for the image display effect according to the lottery result is obtained by reading the image data of the plurality of types of images re-installed in the RAM in advance by the image data batch reading means and performing the image processing. Create and display on the image display means ,
A gaming machine characterized in that the arbitration circuit can reduce the frequency of converting a data address for reading a data block from the NAND flash memory . The gaming machine according to claim 1, wherein the gaming machine is either a pachinko gaming machine or a rotating gaming machine.

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