JP5568778B2 - Image processing apparatus and image processing method - Google Patents

Description

  The present invention relates to an image processing apparatus and an image processing method used for image display in gaming machines and the like, and more particularly, to an image processing apparatus and an image processing method that can reduce the burden on the user and efficiently process image data. .

  Game machines such as pachinko machines, pachislot machines, game machines, etc., as the game progresses, image display devices (typically liquid crystal displays (LCDs)) have fine still images and high speed. It is now common knowledge to display moving videos.

  Here, the still image and the moving image as described above are compressed and stored in a memory in advance, and read out from the memory as the game progresses, and after performing necessary processing and processing, The data is expanded on a RAM (Random Access Memory) and displayed on a display device. Such image output processing is performed by a dedicated image processing apparatus. However, in many cases, the processing device also serves as an output processing device for other information (for example, voice, light, etc.).

  FIG. 4 is a block diagram showing a schematic configuration of a conventional image processing apparatus for displaying still images and moving images used in gaming machines. The conventional image processing apparatus shown in FIG. 1 includes an image display processor 100, a central processing unit (hereinafter referred to as “CPU (Central Processing Unit)”) 2, a data ROM (Read Only Memory) 3, and a video RAM 4. The display device 5 and the work RAM 6 are provided. Here, the CPU 2, the data ROM 3, the video RAM 4, and the display device 5 are each connected to the image display processor 100. The work RAM 6 is connected to the CPU 2.

  The image display processor 100 includes at least a command analyzer 101, a ring buffer 102, a still picture decoder 103, a moving picture decoder 105, a drawing circuit 106, a display circuit 107, and a video RAM interface 108. Here, regarding the line segment connecting the above-described components in the image display processor 100, the solid line indicates the flow of data such as an image, and the broken line indicates the flow of commands and accompanying parameters.

Next, an outline of the operation of the conventional image processing apparatus shown in FIG. 4 will be described.
In the case of this apparatus, it is assumed that the data ROM 3 stores still image data and moving image data that have been compression-encoded. Therefore, the CPU 2 sequentially executes a program that is set in advance so as to display an image in accordance with the progress of a game such as a gaming machine, and issues commands and parameters to the command analyzer 101 in the image display processor 100. .

  The command analyzer 101 analyzes the input command, and in the case of a command related to still image display, activates a processing device related to the still image. Note that still image data is generally data in the form of an intra-frame encoded image (I (Intra) picture) encoded for each predetermined processing unit using only the intra-frame encoding method. Stored in the ROM 3.

  Therefore, in accordance with a command relating to still image display, the compression-encoded still image data read from the data ROM 3 is decoded and expanded by the still image decoder 103, and is stored in the video RAM 4 via the ring buffer 102. In the address space, it is automatically expanded in a still image automatic expansion area (see FIG. 2B) that is secured in advance in association with the address space. The still image data is displayed on the display device 5 through the drawing circuit 106 and the display circuit 107.

  On the other hand, with regard to the display processing of moving image data, since the data on the video RAM 4 is reused across frames, automatic development by a hardware configuration such as processing for still image data is not performed. This was performed according to detailed instructions from the CPU 2.

  Note that in many cases, moving image data generally includes an encoded image by an intra-frame encoding method and an encoded image by an inter-frame encoding method (forward predictive encoding (P (Predictive) picture, etc.)). It is formed and stored in the data ROM 3.

  Therefore, conventionally, the CPU 2 develops the address of the image data to be loaded in the data ROM 3, the address in the video RAM 4 where the previous frame is developed, and in some cases, the current frame, along with the load command of the moving image data. Parameters such as an address in the video RAM 4 to be performed are given to the image display processor 100. These data are given to the moving picture decoder 105 via the command analyzer 101, and the moving picture decoder 105 reads out the compressed moving picture data from the data ROM 3 based on the information and expands it to an arbitrary area AR of the video RAM 4. It expands to the area of the designated address (see FIG. 2B). That is, the CPU 2 as the host device always knows and manages which decoded moving image data is stored in which position in the video RAM 4.

  An example of a document disclosing such a moving image data decoding process is Patent Document 1. In the patent document 1, the first work area and the second work area are secured in the work memory in which the decoded moving image data is to be stored, and the reference image and the inter-frame prediction encoded image are expanded. To obtain the original decoded image.

JP 2008-136124 A JP-A-2005-102144

  However, in the above-described conventional image processing apparatus, it is necessary to designate the address of the moving image development area from the CPU 2 every time moving image data is loaded, and the burden on the CPU 2 is large.

  The video data written in the video RAM 4 is discarded when it is no longer needed, and the area becomes a new empty area. However, as the processing progresses, the free area is changed to a free area by writing or discarding it. If repeated, so-called fragmentation occurs.

  Conventionally, the CPU 2 has to perform a recovery process for the fragmentation, that is, a so-called de-fragmentation process. Specifically, the CPU 2 designates the address before moving and the address after moving of the moving image data to be moved to delete the empty area together with the defragmentation command. Accordingly, the burden on the CPU 2 is large even in this respect. In particular, there are various types of moving images displayed on a gaming machine such as a pachinko machine, the amount of data is uneven, and irregular fragmentation is likely to occur in a short time.

  From the above, the CPU 2 must always keep track of the development status of moving image data on the video RAM 4, and there is a problem that the burden on the user (specifically, a programmer) who uses the device is large.

  On the other hand, as described above, still image data is automatically developed on the video RAM 4 by managing it using a ring buffer by nature. However, separate automatic development suitable for moving image data is also possible. This method was desired.

  The present invention has been made for the above-described circumstances, and an object of the present invention is to provide an image processing apparatus and an image processing method capable of efficiently processing image data while reducing the burden on the user. It is in.

  Patent Document 2 discloses a technique in which a cache device is provided between a processor and a main storage device, and data stored in the cache device is managed by a TLB (Translation Look-aside Buffer). It is intended only for moving image data and also for the entire address space.

In order to achieve the above object, an image processing apparatus according to the present invention includes a first memory in which a plurality of moving image data encoded by an encoding method including at least an inter-frame encoding method is stored in advance, and a plurality of physical pages A first table in which a correspondence relationship between the second memory in which a moving image automatic expansion area is defined, the plurality of physical pages, and identification information of each moving image data stored in each of the plurality of physical pages, the a first video decoder for decoding a plurality of moving image data encoded and stored in the memory, when externally input moving image display command including the identification information of at least the video data, the identification information based on, to the video decoder, the reading moving image data instructed to decode according to the identification information from the first memory, the first table Zui, the decoded image data to the empty physical page of the plurality of physical pages, and stores automatically expand away recognition by the external, the first in response to the storage table And a page area management unit for updating the content.

Here, it is preferable that the identification information is a storage address of the moving image data in the first memory .

Furthermore, the first memory further stores a plurality of encoded still image data in advance, and the second memory defines a still image automatic expansion area corresponding to a ring buffer, and the first memory When a still image decoder for decoding a plurality of encoded still image data stored in a memory and a still image display command including at least the identification information of the still image data are input from the outside, the identification information Based on this, the still picture decoder is instructed to read and decode the still picture data related to the identification information from the first memory, and the read still picture data is stored in the ring buffer. Accordingly, it is preferable to further include a ring area management unit that manages to cyclically store in the still image automatic expansion area of the second memory.

At this time, it is preferable that the identification information is a storage address of the still image data in the first memory .

  Further, when the page area management unit inputs a command related to a defragmentation process for the moving image automatic expansion area, the first table is configured such that each moving image data is continuously stored in the plurality of physical pages. Is preferably updated.

Further, when the moving image data stored in the moving image automatic expansion area is accessed, the identification information and a second table that stores the correspondence relationship between the identification information and the physical pages in which the identification information is stored are accessed. It is preferred that the second table is referenced.

  Each moving image data is preferably data with various capacities for display on a gaming machine. Here, the gaming machine is preferably an amusement machine including at least a pachinko machine and a pachislot machine.

On the other hand, in order to achieve the above object, an image processing method of the present invention is an image processing method in an image processing apparatus including at least a first memory, a second memory, and an image display processor, and at least between frames. A plurality of moving image data encoded by an encoding method including an encoding method is stored in the first memory in advance, and an automatic moving image expansion area composed of a plurality of physical pages is stored in the second memory. The image display processor inputs a moving image display command including at least identification information of the moving image data from the outside, and the image display processor receives the identification from the first memory based on the identification information. The moving image data relating to the information is read and decoded, and the image display processor includes the plurality of physical pages and the moving image data stored in each of the physical pages. Based on a table in which the correspondence relationship with the identification information is stored, the decoded image data is automatically expanded and stored in an empty physical page of the plurality of physical pages apart from recognition by the outside. while, the gist updating the previous Kite Buru depending on its storage.

According to the image processing device and the image processing method of the present invention, when loading image data from the first memory for display, the instructing host control device only specifies the identification information of the moving image, Does not require the address of the storage location in the memory. In other words, the page area management unit performs page management based on the first table with a predetermined area of the second memory as a plurality of physical blocks. Therefore, the host control device does not need to be aware of the storage location on the second memory and does not need to consider the fragmented area. In addition, since it is left to the hardware in this way, time can be afforded, and processing such as moving a large amount of moving image data and switching of moving images can be performed relatively easily as in a gaming machine.

  In short, it is possible to reduce the load on the host control device, in other words, the load on the programmer who creates the program to be processed by the control device, and it can be expected to improve the processing speed at the time of switching the moving image.

  In addition, according to the image processing apparatus including still image data processing as in the present invention, automatic expansion for moving image data is performed separately by a method suitable for moving image data, which is different from the method for managing automatic expansion for still image data. Therefore, the image data can be processed efficiently. In particular, each piece of moving image data processed by the gaming machine is different from still image data and has a variety of capacities, so such independent processing is effective. In addition, the cost required for the hardware can be reduced accordingly.

  Further, when performing the defragmentation process in the image processing apparatus of the present invention, the host control apparatus does not need to specify addresses before and after the movement, and only issues a command. In addition, since the processing is left to the page area management unit, the control device does not need to spend much time on the defragmentation process. In particular, when the image processing apparatus of the present invention is applied to a gaming machine such as a pachinko machine, the effect of hardware defragmentation is significant from the viewpoint of the variety of moving image sizes.

FIG. 1 is a block diagram showing a schematic configuration of an embodiment based on the image processing apparatus of the present invention. 2A and 2B are diagrams showing an address space representing video RAM area allocation. FIG. 2A shows an address space in the present invention, and FIG. 2B shows a conventional address space. FIG. 3 is a diagram for explaining the arrangement of moving image data defined by a virtual address in an area defined by a physical address in the video RAM. FIG. 4 is a block diagram showing a schematic configuration of a conventional image processing apparatus.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
FIG. 1 is a block diagram showing a schematic configuration of an embodiment based on the image processing apparatus of the present invention. Therefore, the image processing apparatus shown in FIG. 1 includes an image display processor 1, a CPU 2, a data ROM 3, a video RAM 4, a display device 5, and a work RAM 6. Here, the CPU 2, the data ROM 3, the video RAM 4, and the display device 5 are each connected to the image display processor 1. The work RAM 6 is connected to the CPU 2.

  The image display processor 1 includes a command analyzer 101, a ring area management unit 112, a still picture decoder 103, a ring area management table 113, a moving picture decoder 105, a drawing circuit 106, a display circuit 107, and a video RAM interface 108. A page area management unit 109, a page area management table 110, and a reverse lookup table 111. Here, regarding the line segment connecting the above-described components in the image display processor 100, the solid line indicates the flow of data such as an image, and the broken line indicates the flow of commands and accompanying parameters.

  As an actual physical configuration, the CPU 2, the video RAM 4, and the work RAM 6 may be built in the image display processor chip. If they are built in, the performance is generally improved, but on the other hand, the cost of the image display processor chip alone is increased due to the addition of functions, but by making the whole into one chip, the cost of the entire system is increased. It can be reduced. However, the gist of the present invention does not depend on the physical configuration.

  The page area management table 110 is a table showing the correspondence between each physical page of a moving image automatic expansion area (to be described later) in the video RAM 4 and each moving picture data stored therein. Specifically, each page of the physical page The number is associated with a virtual address (such as a head address) that identifies each piece of divided data of each piece of image data that is divided and stored in each physical page. The page area management table 110 is preferably composed of a hardware translation look-aside buffer (TLB) for high speed.

  Further, the reverse lookup table 111 is a table that represents a correspondence between virtual pages logically corresponding to the respective divided data of each image data and the corresponding physical pages, and specifically, for example, virtual Each page number is associated with each physical page number.

Next, the operation of the image processing apparatus shown in FIG. 1 will be described in detail.
In the case of this apparatus, it is assumed that the data ROM 3 stores still image data and moving image data that have been compression-encoded. Therefore, the CPU 2 sequentially executes a program that is pre-configured to display an image in accordance with the progress of a game such as a gaming machine, and issues commands and parameters to the command analyzer 101 in the image display processor 1. .

  The command analyzer 101 analyzes the input command, and in the case of a command related to still image display, activates a processing device related to the still image. Note that still image data is generally stored in the data ROM 3 in the form of an intra-frame encoded image (I picture) encoded for each predetermined processing unit using only the intra-frame encoding method in many cases. Has been.

  Therefore, in accordance with a command relating to still image display, the compression-encoded still image data read from the data ROM 3 is decoded and expanded by the still image decoder 103, and the ring region management unit 112 performs ring region management. Under the management using the table 113, a still image automatic expansion area secured in advance in association with the address space of the video RAM 4 via a ring buffer (not shown) (see FIG. 2A). Automatically deployed.

  In this embodiment, the case where the ring area management table 113 is provided and cache management is performed also in the case of still image processing is shown. However, the drawing circuit 106 does not need to use the table management again. A configuration may be adopted in which the displayed object is always deleted after being displayed.

  In the image processing apparatus of the present embodiment, the automatic development by the hardware configuration is realized as follows for the display processing of the moving image data as well. Note that moving image data is generally formed by a coded image by an intra-frame coding method and a coded image (forward prediction coding (P picture), etc.) by an inter-frame coding method. It is stored in the data ROM 3.

  Here, FIG. 2 will be described again. FIG. 2A is a diagram showing an address space representing area allocation of the video RAM 4 in the image output control apparatus of the present invention. As shown in the figure, the address space of the video RAM 4 in the present invention is composed of a frame buffer FB, a Z buffer ZB, a still picture automatic development area SP, a moving picture automatic development area MP, and an arbitrary area AR. That is, as compared with the conventional address space shown in FIG. 2B, an area for automatically developing a moving image in the same manner as a still image is secured as the moving image automatic expansion region MP.

  The frame buffer FB is an image after processing by the drawing circuit 106 and is an area for temporarily storing an image to be displayed by the display circuit 107, and the Z buffer ZB is an entire three-dimensional image. This is an area for storing depth information together.

  Therefore, the CPU 2 according to the embodiment of the present invention instructs the image display processor 1 to load the moving image data to be loaded in the data ROM 3 and, depending on the case, the moving image number (frame number) as parameters. Issue.

  The page area management unit 109 that has received the load command instructs the moving picture decoder 105 to read and decode it based on the address of the image data in the data ROM 3, while referring to the page area management table 110. Then, it is determined how to store the decoded image data in each physical block of the moving image automatic expansion area MP in the video RAM 4.

  FIG. 3 is a diagram illustrating an example of temporal transition of processing in which moving image data is stored or discarded in each physical block of the moving image automatic expansion area MP in the video RAM 4. In the figure, the physical address and virtual address are written in place of block numbers. Therefore, first, the moving image data A is divided into three and stored in the physical blocks 0 to 2 in the free area. Next, the moving image data C is divided into two and stored in the physical blocks 3 and 4 in the empty area. Next, the moving image data D is divided into two and stored in the physical blocks 5 and 6 in the free space. Next, the moving image data C stored in the physical blocks 3 and 4 is discarded, and the physical blocks 3 and 4 are released. Next, the moving image data B is divided into three and stored in the physical blocks 3, 4 and 7 in the free area.

  On the other hand, when the requested moving image data already exists in the video RAM 4, it is not necessary to load it again. When the moving image data already stored in the video RAM 4 is accessed as in that case, that is, when it is desired to know the physical page based on the virtual page, the reverse lookup table 111 is referred to.

  As described above, each image data decoded by the still picture decoder 103 and the moving picture decoder 105 and developed into the video RAM 4 via the video RAM interface 108 is rectangular data before processing. In response to an instruction from the command analyzer 101, these images are read out from the video RAM 4 via the video RAM interface 108, subjected to the requested processing, and temporarily stored in the frame buffer FB (see FIG. 2) of the video RAM 4. Store again.

  The display circuit 107 reads the processed image data stored in the frame buffer FB via the video RAM interface 108 and controls the display device 5 to display the processed image data.

  Further, when performing the defragmentation process, only the command needs to be issued from the CPU 2. The issued defragmentation command is recognized by the page area management unit 109, and the defragmentation process is automatically performed by reorganizing the page area management table 110 and the reverse lookup table 111.

  As described above, according to the image processing apparatus and the image processing method of the embodiment of the present invention, when loading image data from the data ROM 3 for display, the CPU 2 simply designates the number of the moving image. The storage location address in the RAM 4 is not required. That is, the page area management unit 109 performs page management based on the page area management table, with a predetermined area of the video RAM 4 as a plurality of physical blocks. More specifically, the page area management unit 109 searches for unused areas in the plurality of physical blocks, assigns virtual blocks related to moving image data to unused physical blocks, and releases used physical blocks. Unuse it. Therefore, the CPU 2 does not need to be aware of the storage location on the video RAM 4 and does not need to consider the fragmented area. Further, as described above, it is possible to afford time because it is left to the hardware, and it is relatively easy to perform critical processing such as processing of moving a large amount of moving image data and switching of moving images as in a gaming machine.

  Further, when performing the defragmentation process, the CPU 2 does not need to designate addresses before and after the movement, but only issues a command. Further, since the processing is left to the page area management unit 109, the CPU 2 does not need to spend much time on the defragmentation processing. In particular, when the present invention is applied to a gaming machine such as a pachinko machine, the effect of hardware defragmentation is great from the viewpoint of the variety of moving image sizes.

  From the above, it is possible to reduce the load on the CPU 2, in other words, the load on the programmer who creates the program to be processed by the CPU 2, and it can be expected to improve the processing speed at the time of moving image switching.

  In addition, according to the image processing apparatus of an embodiment of the present invention, automatic expansion of moving image data is performed separately by a method suitable for moving image data, which is different from the method of managing automatic expansion for still image data. Therefore, the image data can be processed efficiently. In particular, each piece of moving image data processed by the gaming machine is different from still image data and has a variety of capacities, so such independent processing is effective. In addition, the cost required for the hardware can be reduced accordingly.

  Furthermore, the work RAM 6 conventionally stores data for managing writing and discarding of image data in the video RAM 4, but according to the image processing apparatus of the embodiment of the present invention, Since these data are unnecessary, the capacity of the work ROM 6 can be reduced.

  In the above-described embodiment, the still image data and the moving image data are compressed and stored, and are expanded when displayed. However, the concept of the present invention is independent of compression and expansion. This can also be realized in a configuration in which image data is stored in the data ROM 3 without compression and no decoder is provided. However, if compressed data is used, the memory capacity can be reduced.

  Further, in order to store image data in advance, a ROM is general and suitable as in the above embodiment, but it is not necessarily read-only and may be rewritable.

  The present invention can be applied to an image processing apparatus mounted on a gaming machine such as a pachinko machine or a pachislot machine.

DESCRIPTION OF SYMBOLS 1,100 Image display processor 101 Command analyzer 102 Ring buffer 103 Still image decoder 105 Movie decoder 106 Drawing circuit 107 Display circuit 108 Video RAM interface 109 Page area management unit 110 Page area management table 111 Reverse lookup table 112 Ring area management unit 113 Ring Area management table 2 CPU
3 Data ROM
4 Video RAM
5 Display device 6 Work RAM

Claims (9)

A first memory in which a plurality of moving image data encoded by an encoding method including at least an inter-frame encoding method is stored in advance;
A second memory in which an automatic video expansion area composed of a plurality of physical pages is defined;
A first table in which a correspondence relationship between the plurality of physical pages and identification information of each moving image data stored in each of the physical pages is stored;
A video decoder for decoding a plurality of encoded video data stored in the first memory;
If you enter a video display command including the identification information of at least the video data from the outside, based on the identification information, decoding on the video decoder, it reads the moving image data according to the identification information from the first memory And based on the first table, the decoded image data is automatically expanded and stored in an empty physical page of the plurality of physical pages, away from recognition by the outside. And a page area management unit that updates the first table according to the storage ;
An image processing apparatus comprising: The image processing apparatus according to claim 1 , wherein the identification information is a storage address of the moving image data in the first memory . The first memory further stores a plurality of encoded still image data in advance,
In the second memory, a still image automatic expansion area corresponding to the ring buffer is defined,
A still picture decoder for decoding a plurality of encoded still picture data stored in the first memory;
When a still image display command including at least the identification information of the still image data is input from the outside, the still image data related to the identification information from the first memory to the still image decoder based on the identification information A ring that manages to store the read still image data cyclically in the still image automatic expansion area of the second memory by storing the read still image data in the ring buffer. The image processing apparatus according to claim 1, further comprising an area management unit. The image processing apparatus according to claim 3 , wherein the identification information is a storage address of the still image data in the first memory .   When the page area management unit inputs a command related to the defragmentation process for the moving image automatic expansion area, the page area management unit updates the first table so that each moving image data is continuously stored in the plurality of physical pages. The image processing apparatus according to claim 1. A second table that stores the correspondence between the identification information and each physical page in which the identification information is stored;
The image processing apparatus according to claim 1, wherein the second table is referred to when accessing each moving image data stored in the moving image automatic expansion area.   7. The image processing apparatus according to claim 1, wherein each moving image data is data having various capacities for being displayed on a gaming machine.   The image processing apparatus according to claim 7, wherein the gaming machine is an amusement machine including a pachinko machine and a pachislot machine. An image processing method in an image processing apparatus comprising at least a first memory, a second memory, and an image display processor,
A plurality of moving image data encoded by an encoding method including at least an inter-frame encoding method is stored in the first memory in advance,
In the second memory, an automatic video expansion area composed of a plurality of physical pages is defined,
The image display processor inputs a moving image display command including at least identification information of the moving image data from the outside,
The image display processor reads and decodes the moving image data related to the identification information from the first memory based on the identification information,
The image display processor converts the decoded image data into the plurality of physical pages based on a table storing a correspondence relationship between the plurality of physical pages and the identification information of each moving image data stored in each of the physical pages. the empty physical page of the page, and stores it automatically expand away recognition by the external image processing method characterized by updating the previous Kite Buru depending on its storage.

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