JPH10210484A - Frame buffer management system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a system that realizes a high-speed MPEG video decoder software in a microcomputer system, in which a conventional memory such as a dynamic RAM and a high speed memory such as a static RAM are used in parallel. SOLUTION: A frame buffer secured on a high speed memory 12 is registered to a head entry of a frame buffer management area 10 managing assignment of the frame buffer, and a frame buffer secured on a conventional memory 13 is registered to an entry of the back. The frame buffer storing an I picture (in-frame coded picture) or a P picture (inter-frame forward prediction coded picture) is retrieved in an ascending order from the head entry and the frame buffer which stores a B picture (bi-directional prediction coded picture) is retrieved in a descending order from the end entry.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to an image decompression device, and more particularly to a technique for realizing a high-speed image decompression device.

[0002]

2. Description of the Related Art In recent years, so-called multimedia applications that handle not only conventional character information but also various data such as voice, audio, still image, and moving image have been becoming popular. These multimedia
Because the data is huge, once the data amount is compressed to a few tenths to a few hundredths using the characteristics of the data, it is stored in an external storage device such as a hard disk,
Transfer over the network.

As a compression method, for example, when a moving image is to be processed, MPEG-1 (ISO / IEC 11172,
“Information Technology-C
odding of Moving Pictures
and Associated Audio for
Digital Storage Media upt
o 1.5 Mbits / s, “International
al Standards Organization
/ International Electrotec
hnical Commission, Geneva,
1991) and a higher quality M than MPEG-1
PEG-2 (ISO / IEC 13818, "Gene
ric Coding of Moving Pict
ures and Associated Audio
o, “International Standard
s Organization / International
nal Electrotechnical Comm
issue, Geneva, 1995).

[0004] Moving image data compressed in accordance with these MPEG standards is hereinafter referred to as "MPEG bit stream" or simply "bit stream". MPE
After the G bit stream is stored or transferred, it is expanded (decoded) as necessary, and the decoded image is displayed.

Conventionally, decoding of an MPEG bit stream has been performed using a dedicated LSI. However, with the advancement of the performance of general-purpose microprocessors, the processing of microcomputer products such as personal computers and home-use televisions and game machines has become increasingly difficult. Thus, it is possible to decompress (decode) a moving image compressed according to the MPEG standard using software.

FIG. 13 is a block diagram schematically showing an example of an internal configuration of a microcomputer product for decoding an MPEG bit stream. Referring to FIG. 13, a microprocessor 41 for performing a decoding process, a main memory 42 for storing decoding software and data, and an input / output device 40 for inputting a bit stream 46 and outputting a decoded image 47 include: Internal bus 45
Connected by

FIG. 14 shows the configuration of the decoding process of an MPEG bit stream. The MPEG bit stream has a hierarchical structure. A series of moving images is called a “sequence”. The sequence is “GOP (Group
of Pictures). GOP
Is a group of a plurality of (for example, 15) still images called “pictures”. One picture is composed of a plurality of “slices”, and one slice is 16 pixels × 16
It consists of a "macroblock" of pixels. A macro block is composed of four “blocks” of 8 × 8 pixels. The decoding process is performed according to this hierarchy.

Referring to FIG. 14, after initialization 120,
The decoding process 121 of the sequence layer is started, and the decoding process 121 of the sequence layer internally calls the decoding process 122 of the GOP layer, and the decoding process 122 of the GOP layer.
Internally calls the picture layer decoding process 123, the picture layer decoding process 123 internally calls the slice layer decoding process 124, and the slice layer decoding process 124 internally calls the macroblock layer decoding process 12.
5, and the decoding process 125 of the macroblock layer internally calls the decoding process 126 of the block layer.

[0009] The decoding process of the MPEG bit stream requires a work area for storing the decoded image. This work area is referred to below as the “frame buffer
Pool ".

[0010] The frame buffer pool is MPEG
Reserved as part of the initialization 120 of the decoding software.

When the decoding process 123 of the picture layer is started, the picture header portion is first decoded, then one unused frame buffer is secured from the frame buffer pool, and the decoding of the picture layer and lower is performed. use. When the decoded picture is no longer needed after being used for display or motion compensation, the frame containing the picture
The buffer is released.

FIG. 15 shows an example of the configuration of the frame buffer pool. The frame buffer pool includes a plurality of (N) frame buffers (frame buffer 1, frame buffer 2,..., Frame buffer N, N is, for example, 8) 132, 133, and 134; And a management area 130. The plurality of frame buffers 132, 133, and 134 are
It is placed on the memory 131. The frame buffer management area 130 is also often located on the main memory 131.

One frame buffer holds one picture. The frame buffer management area 130 has N entries corresponding to each frame buffer.
Each entry is a flag 135 indicating whether the corresponding frame buffer is "unused" or "busy".
And the start address 136 of the corresponding frame buffer
And hold.

The initialization of the frame buffer pool is as follows:
Initialization of MPEG decoding software (1 in FIG. 14)
20) It is assumed that it has been completed at times. That is, MP
At the start of decoding the EG bit stream, N frame buffers 132, 133, and 134 are secured in the main memory 131, and the flags 135 of all entries in the frame buffer management area 130 are set to "unused". And the start address 136 of all entries
Holds a valid frame buffer start address.

FIG. 15 shows a processing flow of frame buffer pool management whose configuration example is shown in FIG. 16 as a flowchart.

The picture layer decoding process 123 (FIG. 14)
(See Reference), when allocating a frame buffer, the entry numbers 1 to N of the frame buffer management area 130 are searched in ascending order, and the first unused frame buffer found is allocated. That is, assuming that the entry number to be searched is i, first, i = 1 is set (FIG. 1
6 step 141).

The frame buffer management area 13
The flag 135 of the entry i of 0 is checked (step 14).
2) If not "in use", frame buffer i is used (step 146), and flag 13 is used.
5 is updated to "in use", and if it is "in use",
The variable i is updated by adding 1 (step 143), and the next entry is searched.

After updating the variable i, it is checked whether or not its value has exceeded N (step 144). If the value of i has exceeded N, there is no usable frame buffer, and an error occurs. The process ends (step 145).

In the configuration example shown in FIG. 15, the search order of the entries in the frame buffer management area 130 is ascending from the first entry, but may be searched in descending order from the last entry.

[0020]

FIG. 13 shows an example of the internal structure of the microcomputer system. The main memory 42 has a different structure, so that the processing speed can be increased. . For reference, FIG. 4 shows an example of a configuration for speeding up.

Referring to FIG. 4, high-speed but small-capacity static RAM is used as a component of main memory 42.
(Shown by a high-speed memory 43 in the figure) and a large-capacity but low-speed dynamic RAM (shown by a normal memory 44 in the figure).

Here, focusing only on the performance aspect, it is better to construct the main memory 42 using the high-speed memory 43, but the cost is high. On the other hand, focusing only on the cost aspect, the normal memory 44 having a low cost per capacity is all
Although it is better to construct the main memory 42 by using, the speed becomes slow.

In the example shown in FIG. 4, a high speed memory 43 and a normal memory 44 are combined to realize a relatively high speed main memory 42 at a relatively low cost.

In the system configuration shown in FIG. 4, frequently executed programs and frequently accessed data are stored in the high-speed memory 43, and other programs and data are stored in the normal memory 44. Relatively high-speed processing can be performed on the low-cost main memory 42 system.

However, in the processing flow of the frame buffer pool management method shown in FIG. 16, no consideration is given to the main memory combining such different types of memories, and the microcomputer shown in FIG. -There is a problem that the performance of the system cannot be maximized.

Accordingly, the present invention has been made in view of the above problems, and has as its object
An object of the present invention is to provide an apparatus for realizing high-speed MPEG video decoder software on a microcomputer system using both a normal memory such as an AM and a high-speed memory such as a static RAM.

[0027]

According to the present invention, there is provided an apparatus for expanding a bit stream compressed according to the MPEG standard, comprising a memory system in which a high-speed memory and a normal memory are mixed, MPE
A frame buffer for storing an I picture and a P picture defined by G is preferentially secured in the high-speed memory.

[Summary of the Invention] In addition to the frame buffer on the normal type memory, one or more (preferably two or more) frame buffers are secured on the high-speed type memory to store I-pictures or P-pictures. Assign priority.

According to the present invention, the average time of frame buffer access is reduced by increasing the probability that I and P pictures, which are referred to at the time of motion compensation processing and are accessed many times, are arranged on a high-speed memory. This improves the average execution performance of the MPEG decoder software.

[0030]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below. In the preferred embodiment of the present invention, the allocation of the frame buffer is managed by a single frame buffer management area (10 in FIG. 1), and the high-speed entry is added to the head of the entry of the frame buffer management area. The frame buffers (14 and 15 in FIG. 1) on the memory (12 in FIG. 1) are registered, and the entries after them are stored in the frame buffer on the normal memory (13 in FIG. 1) which is slower than the high-speed memory. Buffers (16, 1 in FIG. 1)
7) is registered, and (a) when allocating a frame buffer for storing an I picture and a P picture, a search is performed in ascending order from the first entry in the frame buffer management area, and (b) a frame for storing a B picture is stored. When allocating a buffer, the search is performed in descending order from the last entry of the frame buffer management area.

As a result, the I and P pictures that are frequently accessed are preferentially allocated to the frame buffer secured on the high-speed memory, so that the performance of the MPEG video decoder software is improved.

In a preferred embodiment of the present invention, the frame buffer is allocated to a frame buffer management area (50 in FIG. 5) for managing the allocation of the frame buffer on the high-speed memory, and to the normal memory. The frame that manages the allocation of the upper frame buffer
It is managed by the buffer management area (51 in FIG. 5), and (a)
To secure a frame buffer for storing I and P pictures, a frame buffer management area (5 in FIG. 5) for managing the allocation of the frame buffer on the high-speed memory is used.
0) first, a frame buffer management area (5 in FIG. 5) for managing the allocation of the frame buffer on the normal memory.
In order to search for 1) later and (b) secure a frame buffer for storing B pictures, the frame buffer management area (51 in FIG. 5) for managing the allocation of the frame buffer in the normal memory must first be set. Then, the frame buffer management area (50 in FIG. 5) for managing the allocation of the frame buffer on the high-speed memory is searched later.

In a preferred embodiment of the present invention, in the preferred embodiment, the allocation of the frame buffer is allocated to a frame buffer management area (9 in FIG. 9) for managing the allocation of the frame buffer allocated to the I or P picture.
0) and a frame buffer management area (FIG. 9) for managing the allocation of the frame buffer to be allocated to the B picture.
91), and at least one frame buffer secured on the high-speed memory is registered at the head of the entry of both frame buffer management areas, and (a) a frame buffer for storing an I picture or a P picture When allocating a buffer, a frame for managing the allocation of a frame buffer to be allocated to an I picture or a P picture
Search the buffer management area in ascending order from the entry head,
(B) The frame buffer storing the B picture searches the frame buffer management area for managing the allocation of the frame buffer assigned to the B picture in ascending order from the entry head.

[0034]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In order to explain the above-mentioned embodiment in more detail, an embodiment of the present invention will be described below with reference to the drawings.

In the following, first, the types of pictures defined by MPEG and the interdependency will be described. Next, the frame buffer on a memory system that mixes high-speed small-capacity memory and large-capacity low-speed memory
Three types of pool configuration and its management flowchart will be described.

First, the types of pictures defined by the MPEG and the interdependencies will be described. Pictures defined by MPEG include I, P, B depending on the type of motion compensation.
There are three types.

Since no motion compensation is used for decoding an I-picture (Intra-coded picture; intra-coded picture), there is no need to refer to another frame buffer when decoding an I-picture.

In decoding a P picture (Predictive coded image; inter-frame forward prediction coded image), forward prediction is sometimes used in motion compensation. Therefore, when decoding a P picture, one frame of the previously decoded I picture or P picture may be referred to.

B picture (Bidirectionally predicti
Decoding of a ve coded image (bi-predicted coded image) may use bidirectional prediction among motion compensation. Therefore, when decoding a B picture, the previously decoded I
It may refer to two frames of a picture or a P picture.

FIG. 3 shows an example of the dependency for each picture type. Frame 1 (I picture, 30), Frame 2
(B picture, 31), frame 3 (B picture, 3
2), if frame 4 (P picture, 33) is displayed in this order, the frame order on the bit stream is frame 1 (30), frame 4 (33), frame 2
(31), frame 3 (32), and decoding is performed in this order.

First, frame 1 (30) is decoded.
Since the frame 1 (30) is an I picture, the frame 1 (30) is completed by itself and does not refer to another frame for motion compensation.

Next, frame 4 (33) is decoded.
Frame 4 (33) is a P picture, and frame 1 (3) stored in the frame buffer during decoding processing.
Motion compensation 36 by forward motion prediction while referring to 0)
Is performed.

Third, frame 2 (31) is decoded. Frame 2 (31) is a B picture, and frame 1 stored in a frame buffer during decoding processing
The motion compensation 34 based on bidirectional motion prediction is performed with reference to (30) and frame 4 (33).

Finally, the frame 3 (32) is decoded. Frame 3 (32) is a B picture, and frame 1 stored in a frame buffer during decoding processing
The motion compensation 35 based on bidirectional motion prediction is performed with reference to (30) and frame 4 (33).

Next, the configuration of the frame buffer pool on the main memory in which different types of memories are mixed will be described.

An example of a configuration in which a high-speed but small-capacity memory (hereinafter referred to as “static RAM 43”, for example, a static RAM 43) and a large-capacity but low-speed memory (hereinafter “normal memory”, eg, a dynamic RAM 44) are combined as the main memory. This will be described below with reference to FIG.

As the capacity of each memory, the high-speed memory 43
Has hundreds of kilobytes (e.g., 256-512 kilobytes)
Normally, a few megabytes of memory 44 or more (eg, 8 megabytes to 64 megabytes) is considered standard. MPEG-
Resolution 354, which is the standard picture format in
Pixel, 240 pixels vertically, 8 bits of luminance signal per pixel,
In the format of 8 bits and 2 planes of color difference signal for every 4 pixels, a capacity of about 127 kilobytes per picture is required. Therefore, when securing eight frame buffers, for example, it is not possible to secure all eight frames on the high-speed memory 43 due to the limitation of the capacity of the high-speed memory 43. Therefore, at most one or two frames
Buffers are secured on the high-speed memory 43, and the remaining seven or six buffers are secured on the low-speed but inexpensive normal memory 44.

As described above, when both the frame buffer secured on the high-speed memory 43 and the frame buffer secured on the low-speed memory 44 exist, the frame buffer described below as the first to third embodiments will be described. Depending on the pool management control method, these two types of frame buffers can be used properly, and the execution performance of the MPEG decoding software can be improved. That is, of the three types of pictures included in the MPEG bit stream, the I and P frames accessed at the time of decoding the subsequent frame are prioritized over the B frame that is not used for decoding the subsequent frame. By controlling the allocation to the frame buffer secured in the above, the picture with a large number of accesses can be preferentially allocated to the high-speed frame buffer, and the execution speed of the decoding software is increased.

A method for managing a frame buffer pool according to the first embodiment of the present invention will be described below in detail with reference to FIGS.

First, the frame buffer pool is changed from the conventional system shown in FIG. 15 to the configuration shown in FIG. That is, referring to FIG. 1, the frame buffers (14, 15) secured on the high-speed memory 12 in ascending order from the entry number 1 of the frame buffer management area 10
Are registered, and the frame buffers (16, 17) secured on the normal memory 13 are registered in the entries after them (in the example shown in FIG. 1, the entry 3 and thereafter).

The frame buffer management area 10 stores entries of a number equal to the total number of frame buffers N (the sum of the number of frame buffers secured on the high-speed memory and the number of frame buffers secured on the normal memory). Have. Each entry includes a flag 18 indicating whether the corresponding frame buffer is unused or in use, and a frame buffer.
Holds the start address 19 of the buffer.

The initialization of the frame buffer pool shown in FIG.
(See FIG. 14). That is, at the start of decoding the MPEG bit stream,
A total of N frame buffers are secured on the high-speed memory 12 and the normal memory 13, and the flags 18 of all entries in the frame buffer management area 10 are set to "unused". It is assumed that the start addresses 19 of all ten entries hold the start addresses of valid frame buffers.

The speed of the frame buffer pool shown in FIG. 1 can be increased by managing it in the following manner.

That is, the picture layer decoding process 12
3 (see FIG. 14), when reserving a frame buffer, the frame buffer
The search order of the entries in the pool management area 10 is changed.

To secure a frame buffer for storing I or P pictures, search from entry numbers 1 to N in ascending order. To secure a frame buffer for storing B pictures, use entry number N. From 1 to 1 in descending order. The picture type is
It can be known that the picture header is decoded at the beginning of the picture layer decoding process 123 (see FIG. 14).

Next, the method of managing the frame buffer pool shown in FIG. 1 will be described in detail with reference to the flowchart of FIG. Hereinafter, the entry number to be searched is defined as i.

Picture to be stored in the frame buffer
The type is determined (step 21), and the I picture or P
The procedure for a picture is as follows. First,
"1" is set as the initial value of i (step 22).

Frame buffer pool management area 10
The flag of the entry i is checked (step 23). If the flag is not "in use", the frame buffer i is used and the flag is updated to "in use" (step 2).
7) If "in use", update by adding "1" to i (step 24), and search for the next entry. Then, after updating i, it is checked whether or not the value has exceeded N (step 25). If i exceeds N, there is no usable frame buffer, so that error termination is performed (step 2).
6).

Picture to be stored in the frame buffer
The type is determined (step 21), and the procedure when the picture is a B picture is as follows.

First, "N" is set as an initial value of i (step 29). The flag of the entry i of the frame buffer pool management area is checked (step 30). If the flag is not "in use", the frame buffer i is used and the flag is updated to "in use" (step 2).
7) If "in use", update "1" by subtracting "1" from i (step 31), and search for the next entry. After updating i, the value is checked (step 32). If i is smaller than "1", there is no usable frame buffer, and the process ends with an error (step 33).

As described above, according to the processing procedure shown in FIG. 2, when securing a frame buffer for accommodating I and P pictures with a large number of accesses, the frame buffer secured on the high-speed memory is used. Is searched first, and when allocating a frame buffer for accommodating a B picture with a small number of accesses, the frame buffer allocated on the low-speed memory is first placed, and then the frame buffer allocated on the high-speed memory is placed later. Search for. Therefore, according to the present embodiment, the execution speed of the decoder software can be increased as compared with the conventional method of securing a frame buffer regardless of the picture type.

The first frame buffer described above
In the pool management method, the frame buffer on the high-speed memory is registered in the first entry, the I and P picture frame buffers are searched in ascending order from the first entry, and the B picture frame buffers are searched in descending order from the last entry. The same effect can be obtained by registering the frame buffer on the high-speed memory in the last entry and searching the I and P picture frame buffers in descending order from the last entry, and searching the B picture frame buffer in descending order from the first entry.

Further, in the example shown in FIG.
Although the number of frame buffers secured above 2 is two, the same discussion as above can be applied to any number of one or more.

Next, a second embodiment of the present invention will be described. FIG. 5 is a diagram showing the configuration of the second embodiment of the present invention, and shows the configuration of a frame buffer pool that preferentially allocates a high-speed frame buffer to I and P pictures. 6 to 8 are flowcharts for explaining a method of managing the frame buffer pool shown in FIG.

Referring to FIG. 5, in this embodiment,
Frame buffer (5
5, 56) and the frame secured on the normal memory 54
Buffers (57, 58) and separate frames
It is managed in the buffer management area (50, 51).

It is assumed that N1 frame buffers are secured in the high-speed memory 53 and N2 frame buffers are secured in the normal memory 54. The frame buffer management area includes a frame buffer management area 1 (50) having N1 entries for managing the frame buffer on the high-speed memory 53, and N2 entries for managing the frame buffer on the normal memory 54. Are divided into a frame buffer management area 2 (51) having Each entry of the two frame buffer management areas holds a flag (501, 511) indicating whether the corresponding frame buffer is unused or in use and a start address (502, 512) of the frame buffer.

It is assumed that the initialization of the frame buffer shown in FIG. 5 has been completed at the time of initialization 120 of the decoding software (see FIG. 14). That is, MPEG
At the start of decoding the bit stream, the high-speed memory 5
3 frames and N2 frames on the normal memory 54.
Buffer is secured and frame buffer management area 1
(50), the flags (501, 511) of all entries in the frame buffer management area 2 (51) are set to unused, and the start addresses (50) of all entries are set.
2, 512) hold a valid frame buffer start address.

FIG. 6 is a flowchart showing a method for managing the frame buffer pool configuration shown in FIG. FIG.
Refer to the picture to be stored in the frame buffer.
If the type is determined (step 61) and a frame buffer for I and P pictures is to be reserved, first, an attempt is made to reserve a frame buffer on the high-speed memory 53 (step 62).

At step 62, if the attempt to secure the frame buffer on the high-speed memory 53 fails, the normal memory 5
4. Attempt to secure a frame buffer on
3). If any of them succeeds, the process ends normally (step 65). If any of them fails, the process ends in an error (step 64).

When securing a frame buffer for a B picture, an attempt is first made to secure a frame buffer on the normal memory 54 (step 66). If that fails, an attempt is made to secure a frame buffer on the high-speed memory 53 (step 67). If any of them succeeds, the process ends normally (step 65). If any of them fails, the process ends in an error (step 68).

FIG. 7 is a flowchart for explaining a procedure for trying to secure a frame buffer on the high-speed memory 53. Referring to FIG. 7, first, the entry number i to be searched is initialized to "1" (step 71). Next, entry i of frame buffer management area 1 (50 in FIG. 5)
Is checked (step 72). If the flag is not "in use", the frame buffer i is secured, and the flag is updated to "in use" (step 76).
If so, "1" is added to i and updated (step 7).
3) Retrieve the next entry. After updating i, its value is checked (step 74). If i exceeds N1, there is no frame buffer on the high-speed memory that can be used.

FIG. 8 is a flowchart for explaining a procedure for attempting to secure a frame buffer on the normal memory 54. Referring to FIG. 8, first, the entry number i to be searched is initialized to "1" (step 81). Next, entry i of frame buffer management area 2 (51 in FIG. 5)
(Step 82), the frame buffer i is secured if it is not "in use", and the flag is updated to "in use" (86). "1" is added and updated (step 83), and the next entry is searched. After updating i, its value is checked (step 84). If i exceeds N2, there is no available frame buffer on the normal memory, so "secure failed" (step 85).

Also in the second embodiment described above, the availability of the frame buffers (55, 56) on the high-speed memory 53 is preferentially secured when securing the frame buffer for frequently accessed I-pictures. At the time of securing the frame buffer for the B picture, the frame buffer (55, 5
Since the search in 6) is performed later, the execution speed of the decoder software can be increased as compared with the conventional method of securing a frame buffer regardless of the picture type.

In the second embodiment, as shown in the flowcharts of FIGS. 7 and 8, the frame buffer management area 1 (50) and the frame buffer management area 2 (51)
In both cases, the search is performed in ascending order from the first entry. However, the same effect can be obtained by searching either one of the frame buffer management areas or both frame buffer management areas in descending order from the last entry.

Next, a third embodiment of the present invention will be described. FIG. 9 is a diagram showing the configuration of the third embodiment of the present invention, and shows the configuration of a frame buffer pool in which a high-speed frame buffer is preferentially allocated to I and P pictures. FIGS. 10 and 11 are flowcharts for explaining a method of managing the frame buffer pool shown in FIG. It should be noted that FIGS. 10 and 11 are merely separated for convenience of drawing.

Referring to FIGS. 10 and 11, a frame buffer for I and P pictures and a frame buffer for B pictures
The buffer is managed in another frame buffer pool management area.

In the configuration shown in FIG. 9, it is assumed that N3 frame buffers are reserved for I and P pictures and N4 frame buffers are reserved for B pictures. However, it is assumed that one or more (preferably two or more) of the I and P picture frame buffers are secured in a high-speed memory, and the rest are secured in a normal memory. Similarly, it is assumed that one or more of the B picture frame buffers are secured in a high-speed memory, and the rest are secured in a normal memory.

The frame buffer management area includes a frame buffer management area 3 (90) having N3 entries for managing I and P picture frame buffers, and B
It comprises a frame buffer management area 4 (91) having N4 entries for managing the picture frame buffer. Each entry in both management areas has a flag (901, 91) indicating whether the corresponding frame buffer is unused or in use.
1) and the start address of the frame buffer (90
2, 912).

The initialization of the frame buffer pool shown in FIG.
(See FIG. 14). That is, at the start of decoding the MPEG bit stream,
Necessary frame buffers are secured on the high-speed memory 93 and the normal memory 94, and the flags (901, 901) of all entries in the frame buffer management area (90, 91) are reserved.
911) is set to be unused, and the start addresses (902, 912) of all entries hold valid frame buffer start addresses. Also,
The addresses of the frame buffers (95, 96) secured on the high-speed memory 93 for the I and P pictures are all registered in the frame buffer management area 3 (90) in ascending order from entry 1. Similarly, the addresses of the frame buffer (97) secured on the high-speed memory 93 for B pictures are all assigned to the frame buffer management area 4 (9).
1) are registered in ascending order from entry 1.

FIGS. 10 and 11 are flowcharts showing a procedure for managing the frame buffer pool shown in FIG. Referring to FIG. 10, the picture type to be stored in the frame buffer is determined (step 111). When a frame buffer for storing an I or P picture is to be reserved, the frame buffer management area 3 (9
0) are searched in ascending order from entry numbers 1 to N3.

First, the entry number i to be searched is set to “1”.
(Step 112). Next, the flag of the entry i is checked (step 113). If the flag is not "in use", the frame buffer i is used and the flag is updated to "in use" (step 117).
Then, add “1” to i and update (step 114),
Search for the next entry. After updating i, the value is checked (step 115). If i exceeds "N3", there is no usable frame buffer, so that an error is terminated (step 116).

Referring to FIG. 11, when securing a frame buffer for storing B pictures, entry numbers 1 to N in frame buffer management area 4 (91) are used.
Search up to 4 in ascending order. First, the entry number i to be searched is initialized to "1" (step 119). Next, the flag of the entry i is checked (step 120). If the flag is not "in use", the frame buffer i is used and the flag is updated to "in use" (step 12).
4) If "in use", i is updated by adding "1" to i (step 121), and the next entry is searched. After updating i, the value is checked (step 122). If i exceeds "N4", there is no usable frame buffer, so that an error is terminated (step 123).

According to the method shown in FIGS. 10 and 11,
The frame buffer secured in high-speed memory 93 is
Alternatively, one, preferably two or more, are registered in the frame buffer pool for P pictures, and the search is performed prior to the frame buffer in the normal memory 94, so that I and P pictures with a large number of accesses can be processed at high speed. The probability that the frame buffer on the memory 93 is allocated is increased, and the execution speed of the decoder software is increased. At the same time, at least one frame secured in the high-speed memory 93 is stored in the frame buffer pool for B pictures.
By registering a buffer and performing a search prior to the frame buffer in the normal memory 94, the probability of speeding up the decoding process of the B picture is increased.

In the structure of the third embodiment of the frame buffer pool described above, a relatively large number (for example, three or more) of frame buffers can be secured in the high-speed memory 93, and normal processing is performed at high speed. Although it can be performed on the memory 93, it is suitable for a system in which a large amount of a frame buffer is normally reserved on the memory 94 in the worst case in consideration of fluctuations in bit rate and load fluctuations of tasks other than the MPEG software decoder. .

In the configuration of the third embodiment of the present invention shown in FIG. 9, the number of frame buffers secured in the high-speed memory 93 is three, two of which are in the frame buffer management area 3 (90). , One frame / buffer management area 4
Although registered in (91), two or more frame buffers are secured in the high-speed memory 93, and one or more are stored in the frame buffer management area 3 (90) and one is stored in the frame buffer management area 4 (91). The same discussion applies if you have registered above.

However, in the motion compensation for generating a B picture, three or more frame buffers are secured in the high-speed memory 93 in terms of performance because bidirectional prediction is performed with reference to two previously generated pictures. Preferably, two or more frames are registered in the frame buffer management area 3 (90).

The structure of the frame buffer pool described in the first to third embodiments is, as shown in FIG.
A high-speed memory 43 and a normal memory 44 are connected in parallel to an internal bus 45.
Is assumed to be connected to the address space of the microprocessor 41 and accessed equally.

However, the configuration of the frame buffer pool described in the first to third embodiments may be applicable to the microcomputer system having the configuration shown in FIG.

In the configuration shown in FIG.
M is located between the microprocessor and the normal memory, and operates as the cache memory 48. That is,
A static RAM usually holds a copy of a small portion of the contents of memory that has recently been used.

However, if the microprocessor has a cache block locking mechanism, the cache
Replacement of a part of the memory 48 is prohibited, and the memory 48 can be used like the high-speed memory 43 shown in FIG. That is,
The configurations of the first to third frame buffer pools described above are also applicable to the microcomputer system shown in FIG.

The processing described with reference to the flowchart in the above embodiment is controlled by execution of a program instruction of the microcomputer.

[0092]

As described above, according to the present invention,
Using a system that combines a small-capacity high-speed memory and a large-capacity normal memory, a relatively low cost and relatively high-speed M
This has the effect of providing PEG decoder software.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a configuration of a first exemplary embodiment of the present invention.

FIG. 2 is a flowchart illustrating a first embodiment of the present invention.

FIG. 3 is a diagram illustrating an example of a picture dependency relationship.

FIG. 4 is a diagram illustrating a configuration example of a microcomputer system having a high-speed memory.

FIG. 5 is a diagram illustrating a configuration of a second exemplary embodiment of the present invention.

FIG. 6 is a flowchart illustrating the operation of the second exemplary embodiment of the present invention.

FIG. 7 is a flowchart showing a procedure for searching a frame buffer on a high-speed memory in the second embodiment of the present invention.

FIG. 8 is a flowchart showing a procedure for searching for a frame buffer in a normal memory in the second embodiment of the present invention.

FIG. 9 is a diagram for explaining a configuration of a third exemplary embodiment of the present invention.

FIG. 10 is a flowchart illustrating the operation of the third embodiment of the present invention.

FIG. 11 is a flowchart illustrating the operation of the third embodiment of the present invention.

FIG. 12 is a diagram for explaining a method of using a cache instead of a high-speed memory as a fourth embodiment of the present invention.

FIG. 13 is a diagram illustrating a configuration example of a microcomputer system.

FIG. 14 is a flowchart showing a procedure for decoding an MPEG bit stream.

FIG. 15 is a diagram showing an example of a conventional frame buffer pool configuration.

FIG. 16 is a flow chart for explaining a conventional frame buffer pool management method.

[Explanation of symbols]

10 Frame buffer management area 11 Main memory 12 High-speed memory 13 Normal memory 14 Frame buffer allocated on high-speed memory 15 Frame buffer allocated on high-speed memory 16 Frame buffer allocated on normal memory 17 Normal memory 40 I / O device 41 Microprocessor 42 Main memory 43 High speed memory 44 Normal memory 45 Internal bus 46 Bit stream 47 Decoded image 48 Cache memory 50 Frame buffer management area 1 51 Frame buffer management area 2 52 Main memory 53 High-speed memory 54 Normal memory 55 Frame buffer allocated on high-speed memory 56 Frame buffer allocated on high-speed memory 57 Frame allocated on normal memory Frame buffer 58 Frame buffer secured on normal memory 90 Frame buffer management area 3 91 Frame buffer management area 4 92 Main memory 93 High speed memory 94 Normal memory 95 Frame buffer secured on high speed memory 96 High speed memory Frame buffer secured above 97 Frame buffer reserved above normal memory 98 Frame buffer reserved above normal memory 99 Frame buffer reserved above normal memory 100 Frame buffer reserved above normal memory 101 Normal memory Frame buffer secured above 130 Frame buffer management area 131 Main memory 132 Frame buffer secured on main memory 133 Frame buffer secured on main memory 134 Main Frame buffer secured on the memory 135 flag 136 start address 501 flags 502 the start address 511 flags 512 the start address 901 flags 902 the start address 911 flags 912 the start address

Claims (11)

[Claims] An apparatus for expanding a bit stream compressed according to the MPEG standard, comprising a memory system in which a high-speed type memory and a normal type memory are mixed, and a frame system for storing I-pictures and P-pictures specified by MPEG. An apparatus, wherein a buffer is preferentially allocated on the high-speed memory. 2. The apparatus according to claim 1, wherein frame buffer allocation is managed by a single frame buffer management area, and a head portion of said frame buffer management area entry is stored in said high-speed memory. When a frame buffer on the normal type memory is registered in an entry subsequent thereto, a frame buffer for storing I-pictures and P-pictures is secured. An apparatus which searches in ascending order from the head entry of the first area, and searches in descending order from the last entry in the frame buffer management area when allocating a frame buffer for storing a B picture. 3. The apparatus according to claim 1, wherein the allocation of the frame buffer is performed by a frame buffer for managing the allocation of the frame buffer on the high-speed memory.
A buffer management area, and a frame
In order to manage the buffer allocation by a frame buffer management area and secure a frame buffer for storing I-pictures and P-pictures, a frame buffer on the high-speed memory is required.
The frame buffer management area for managing the allocation of the frame buffer on the normal type memory is searched first after the frame buffer management area for managing the allocation of the buffer, and the frame buffer for storing the B picture is secured. Searching for a frame buffer management area that manages the allocation of frame buffers on the high-speed memory first and a frame buffer management area that manages the allocation of frame buffers on the high-speed memory; An apparatus characterized in that: 4. The apparatus according to claim 1, wherein the allocation of the frame buffer is performed using an I picture or a P picture.
A frame buffer management area for managing the allocation of frame buffers to be allocated to pictures and a frame buffer management area for managing the allocation of frame buffers to be allocated to B-pictures. In addition, at least one frame is allocated on the high-speed memory
When registering a buffer and reserving a frame buffer for storing an I picture or a P picture, a frame buffer management area for managing the allocation of the frame buffer to be allocated to the I picture or the P picture is searched in ascending order from the head of the entry. A frame buffer for storing a B picture, wherein a frame buffer management area for managing the allocation of the frame buffer to be allocated to the B picture is searched in ascending order from the entry head. 5. The apparatus according to claim 2, wherein a part of the cache memory is locked so as not to be replaced, and is used instead of the high-speed memory. Characteristic device. 6. A memory system in which a relatively small-capacity high-speed memory and a large-capacity normal memory are mixed.
What is claimed is: 1. A method for managing a frame buffer in an apparatus for expanding a bit stream compressed according to the EG standard, comprising: managing frame buffer allocation by a single frame buffer management area; A frame buffer for registering a frame buffer on the high-speed memory at a head portion, registering a frame buffer on the normal memory for an entry subsequent to the frame buffer, and storing an I picture and a P picture. When securing a frame buffer for storing B pictures, search in ascending order from the last entry of the frame buffer management area. A method for managing a frame buffer. 7. A memory system in which a high-speed memory having a relatively small capacity and a normal memory having a large capacity are mixed.
What is claimed is: 1. A method for managing a frame buffer in an apparatus for expanding a bit stream compressed according to the EG standard, comprising: a frame buffer that manages the allocation of a frame buffer on the high-speed memory.
A buffer management area, and a frame
In order to manage the buffer allocation by a frame buffer management area and secure a frame buffer for storing I-pictures and P-pictures, a frame buffer on the high-speed memory is required.
The frame buffer management area for managing the allocation of the frame buffer on the normal type memory is searched first after the frame buffer management area for managing the allocation of the buffer, and the frame buffer for storing the B picture is secured. Searching for a frame buffer management area that manages the allocation of frame buffers on the high-speed memory first and a frame buffer management area that manages the allocation of frame buffers on the high-speed memory; A method for managing a frame buffer. 8. A memory system in which a high-speed memory having a relatively small capacity and a normal memory having a large capacity are mixed.
A method of managing a frame buffer in a device for expanding a bit stream compressed according to the EG standard, wherein the allocation of the frame buffer is performed using an I picture or a P picture
A frame buffer management area for managing the allocation of frame buffers to be allocated to pictures and a frame buffer management area for managing the allocation of frame buffers to be allocated to B-pictures. In addition, at least one frame is allocated on the high-speed memory
When registering a buffer and reserving a frame buffer for storing an I picture or a P picture, a frame buffer management area for managing the allocation of the frame buffer to be allocated to the I picture or the P picture is searched in ascending order from the head of the entry. A frame buffer storing a B picture, wherein a frame buffer management area for managing the allocation of the frame buffer allocated to the B picture is searched in ascending order from the entry head. 9. A memory system in which a high-speed memory having a relatively small capacity and a normal memory having a large capacity are mixed.
A program executed on a processing device for decompressing a bit stream compressed according to the EG standard to manage a frame buffer, wherein the frame buffer allocation is managed by a single frame buffer management area, and Registering a frame buffer on the high-speed memory at the head of the entries in the buffer management area, and registering a frame buffer on the normal memory at entries subsequent to the I-picture and P-picture When reserving a frame buffer for storing a picture, the search is performed in ascending order from the first entry in the frame buffer management area. When reserving a frame buffer for storing a B picture, the search is performed at the last entry in the frame buffer management area. Searching for each entry in descending order; Recording medium on which a program to be executed is recorded. 10. A memory system in which a high-speed memory having a relatively small capacity and a normal memory having a large capacity are mixed.
A program executed on a processor for expanding a bit stream compressed according to the PEG standard to manage a frame buffer. Frame
A buffer management area, and a frame
In order to manage the buffer allocation by the frame buffer management area and secure the frame buffer for storing the I picture and the P picture,
The frame buffer management area for managing the allocation of the frame buffer on the normal type memory is searched first before the frame buffer management area for managing the allocation of the buffer, and the frame buffer for storing the B picture is secured. Searching for a frame buffer management area for managing the allocation of frame buffers on the high-speed memory first and a frame buffer management area for managing the allocation of frame buffers on the high-speed memory later; A recording medium storing a program for causing the processing device to execute each of the processes. 11. A memory system in which a high-speed memory having a relatively small capacity and a normal memory having a large capacity are mixed.
A program which is executed on a processing device for expanding a bit stream compressed according to the PEG standard and manages a frame buffer.
A frame buffer management area for managing the allocation of frame buffers to be allocated to pictures and a frame buffer management area for managing the allocation of frame buffers to be allocated to B-pictures. In addition, at least one frame is allocated on the high-speed memory
When registering a buffer and reserving a frame buffer for storing an I picture or a P picture, a frame buffer management area for managing the allocation of the frame buffer to be allocated to the I picture or the P picture is searched in ascending order from the head of the entry. The frame buffer for storing the B picture searches for a frame buffer management area for managing the allocation of the frame buffer to be allocated to the B picture in ascending order from the entry head, and stores a program for causing the processing device to execute the above-described processes. recoding media.