JP2011152413A - Signal processor, signal processing system, and game machine - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a signal processor capable of controlling comprehensively image development, sound reproduction, timing thereto with respect to an operation of functional object, or the like, in an interactive game machine or the like. <P>SOLUTION: A graphic logic 6 and a sound logic 7 are mounted on the same unified LSI 5 to cooperate a command system. The graphic logic 6 includes a command decoding part 20 for decoding a command of a CPU 10, and an image decoding part 22, and a sound decoding part 21 in the sound logic 7 is operated by the command via the command decoding part 20. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a signal processing apparatus capable of efficiently and comprehensively controlling image development, sound reproduction, operation of an accessory, lighting of a light emitting element, and the like particularly in an interactive game machine or game machine.

  In the field of gaming machines such as pachinko machines, the control unit is configured by a large number of LSIs so that they can be enjoyed while enhancing image effects and sound effects. Generally, LSIs that perform image processing and LSIs that perform sound processing. Are separately prepared, and the system configuration is such that a cooperative operation is performed by sending a predetermined command to these LSIs from the host CPU. In particular, image information has a large amount of information, and an image processing system that is devised based on an image compression technique and its expansion (decompression) technique is described in Patent Documents 1 and 2, for example.

  On the other hand, Patent Document 3 proposes a system that increases the use efficiency of the host CPU by linking the image LSI and the sound LSI while separately holding the image LSI and the sound LSI in order to reproduce the image and sound in cooperation. . Further, in the cited document 4, one CPU sends an effect pattern selection command to the tone generator circuit while controlling the image control unit, and the tone generator circuit reads out, decodes and outputs the tone generator data based on this command. Is described.

Japanese Patent No. 3970291 JP 2009-294990 A JP 2007-156519 A JP 2008-142102 A

  However, in recent gaming machines, the game effect is not limited to images and sounds, but the so-called actor motor control, such as opening / closing an attacker or changing the movement of a character object, is a role that already exists on the board. Control of whether an object changes its movement or suddenly appears, and the lighting state of many LEDs arranged around the board surface is changed. It is designed to increase the expectation for playability.

  Even in such a system, individual LSIs are usually used to control images, sound, motors, and LEDs for commands from the host CPU, and each LSI is individually controlled depending on the commands from the host CPU. Therefore, there is a problem that the burden on the program of the host CPU becomes large in order to perform such cooperative operation. Furthermore, in order to enhance the play effect, it is necessary to synchronize the image information and the audio information so that each is output at an appropriate timing. There is no configuration for comprehensively controlling the timing of voice playback, the operation of an accessory, etc., and there is a problem that a complicated configuration or processing procedure is required for such adjustment. .

  In order to solve such a problem, the invention according to claim 1 of the present invention is a signal processing device configured as an LSI chip whose operation is controlled by a command from a higher-level CPU, and for image data displayed on a display means. A graphics logic for controlling the output and an audio logic for controlling the output of the audio data output from the audio output means, wherein the graphics logic includes an instruction decoding unit for decoding an instruction of the upper CPU; And an image decoding unit, wherein the audio decoding unit in the audio logic operates according to a command via the command decoding unit.

  According to a second aspect of the present invention, in addition to the configuration of the first aspect, a display list in which a series of transfer commands issued by the display list issuing means to be executed by the signal processing device is described in a substantially time-series manner. The graphics logic and the audio logic are controlled approximately in time series by being supplied to the instruction decoding unit.

  According to a third aspect of the present invention, in addition to the configuration of the second aspect, a plurality of graphics lists and a plurality of audio lists are described as the series of transfer instructions in the display list, and the instructions The decoding unit decodes the display list, the image decoding unit performs various image processing based on the decoding result of the graphics list in the instruction decoding unit, and the audio decoding unit in the instruction decoding unit Various voice processes are performed based on the decoding result of the voice list.

  Invention of Claim 4 is a signal processing system, Comprising: The signal processing apparatus in any one of Claim 1 thru | or 3, The display means connected to the said image decoding part, and performing a graphics display, The said And an audio output unit connected to the audio decoding unit for outputting audio.

  According to a fifth aspect of the present invention, in addition to the configuration according to the fourth aspect, there is provided a display list issuing means for issuing a display list in which a series of transfer instructions to be executed by the signal processing device are described in a substantially time-series manner. The display logic that is issued by the display list issuing means and described in a substantially time-series manner as a series of transfer instructions to be executed by the signal processing device is supplied to the instruction decoding unit, whereby the graphics logic, The sound logic is controlled substantially in a time series manner, and an image is displayed on the display means and sound is output from the sound output means.

  According to a sixth aspect of the invention, in addition to the configuration of the fifth aspect, the display list includes a plurality of graphics lists and a plurality of audio lists as the series of transfer instructions, and the instructions The decoding unit decodes the display list, the image decoding unit performs various image processing based on the decoding result of the graphics list in the instruction decoding unit, and the audio decoding unit in the instruction decoding unit Various voice processes are performed based on the decoding result of the voice list.

  A seventh aspect of the present invention is a gaming machine, comprising the signal processing device according to any one of the first to third aspects.

  The invention described in claim 8 is a gaming machine and is characterized by including the signal processing system according to any one of claims 4 to 6.

  According to the first and fourth aspects of the present invention, the audio decoding unit in the audio logic operates in accordance with an instruction via the instruction decoding unit included in the graphics logic, so that the image decoding unit, the audio decoding unit, Operates on instructions through the same instruction decoding unit. This makes it possible to easily and accurately adjust the timing of graphics development and audio logic operations for image development, audio playback, and accessory operations, especially in interactive game machines and game machines. It is possible to efficiently and comprehensively control image development, sound reproduction, operation of an accessory, lighting of a light emitting element, and the like.

  According to the second and fifth aspects of the present invention, the graphic logic and the audio logic are controlled in a substantially time-series manner by the display list, thereby comprehensively controlling the graphics processing and the audio processing. Can be easily performed. As a result, it is possible to adjust the timing of image development, sound reproduction, and operation of the accessory more easily and accurately.

  According to the third and sixth aspects of the present invention, the graphics processing and the sound processing are performed depending on the description order of the graphics list and the sound list in the display list. Comprehensive control of processing and voice processing can be easily performed. As a result, it is possible to adjust the timing of image development, sound reproduction, and operation of the accessory more easily and accurately.

  According to the seventh and eighth aspects of the invention, it is possible to efficiently and comprehensively control image development, sound reproduction, and action of an accessory in an interactive gaming machine.

1 is an overall block diagram illustrating a signal processing device according to an embodiment of the present invention. It is a block diagram which shows the internal structure of the logic for graphics of this invention roughly, and shows the relationship with external memory. It is a block diagram explaining the detail of the decoder part of the logic for graphics of this invention. It is a flowchart which shows the decoding operation | movement of this invention. It is the figure which compared the sector structure and arrangement | positioning state of audio | voice data of the NAND memory based on this invention with the prior art example. It is a flowchart which illustrates the conventional decoding operation | movement. It is a timing chart explaining the conventional decoding operation.

  1 to 5 show an embodiment of the present invention, and FIGS. 6 and 7 show conventional examples. Hereinafter, an embodiment of the present invention will be described with reference to these drawings.

  FIG. 1 is an overall block diagram showing a signal processing apparatus and a signal processing system according to an embodiment of the present invention. This signal processing system 1A is visually and audibly output to an output device such as an LCD 1 as a “display means”, a speaker 2 as a “sound output means”, a motor 3 and an LED 4 arranged on the board surface of the gaming machine. It is constituted by an integrated LSI 5 as a “signal processing device” for controlling the operation of peripheral devices for appealing and enhancing playability.

  The LCD 1 is connected to a later-described graphics logic 6 to display various graphics. The speaker 2 is connected to a later-described sound logic 17 and outputs various sounds.

  The integrated LSI 5 is configured as a single LSI chip, and in this embodiment includes a graphics logic 6, audio logic 7, motor control logic 8, and LED control logic 9.

  The CPU 10 is a processor corresponding to the upper CPU of the integrated LSI 5 and generates an instruction group 11 (command list) to be executed by the integrated LSI 5. In this embodiment, the CPU 10 is provided separately from the integrated LSI 5, but the CPU 10 may be built in the integrated LSI 5.

  In particular, the CPU 10 functions as “display list issuing means” for issuing a display list 12 in which a series of transfer instructions to be executed by the integrated LSI 5 are described in a substantially time-series manner. In this display list 12, the image processing procedure is defined by a series of commands described in a substantially time-series manner, and in terms of image units, the transfer procedure of a material necessary for drawing an image of one frame is defined. . Here, the material refers to a unit of a predetermined size defined in advance in image data stored in a CGROM (actually, a NOR or NAND flash memory) that is an external memory. . Furthermore, the signal processing apparatus of this embodiment is characterized in that it also includes a motor control transfer procedure and an LED lighting control procedure. G00 to G05 displayed on the display list 12 are graphics lists, S00 to 02 are audio lists, M00 to 02 are motor control lists, and L00 to L02 are LED control lists. Elements of these lists are mixedly stored in the display list 12, and are configured so that each output device can be controlled in cooperation.

  The motor 3 and the LED 4 are arranged in large numbers on the board surface of the gaming machine, but the control signal for operating each of them is sent from the integrated LSI 5 to the two control drivers 13 having the same configuration as “motor driver circuit”. ”And“ LED driver circuit ”, it is possible to share an external circuit for motor control and LED control. This is because the function for serial / parallel conversion is the same, and in order to actually operate the motor 3, a motor driver 14 necessary for driving the motor may be disposed after the signal converter. In this way, the control driver 13 can be used for serial / parallel conversion of the motor control signal, so that it is not necessary to design an individual drive circuit. Further, a stepping motor is normally used as the motor 3, and its rotational state is detected by the sensor 15 and fed back to the motor control logic via the parallel / serial inverse converter 16 so that abnormal rotation does not occur. Stable position control.

  Although the clock OSC 17 for the CPU 10 and the clock OSC 18 for the integrated LSI 5 are separately shown in the drawing, of course, the latter clock can also be created by dividing from the former.

  Here, usually, LED control and motor control are often operated at a low speed because the response speed of the controlled object is slow, while fine and fast logic is used for graphics.

  In the present embodiment, since the clock frequency is increased and data can be multiplexed, a large number of LEDs 4 and motors 3 can be controlled simultaneously. Furthermore, graphic control and motor / LED control are created in separate environments, but at this time, it is difficult to synchronize with the playback of the movie, so it was necessary to make fine adjustments at the combined stage, By adding LED and motor processing to the video display list, it is possible to create a video (sound) and LED / motor synchronized in the display list generation stage.

  FIG. 2 is a block diagram schematically showing the internal configuration of the graphics logic 6 and the relationship with the external memory 19. The graphics logic 6 includes an image decoding unit 22, a VRAM 23, and a display circuit 24 in addition to the instruction decoding unit 20 and the audio decoding unit 21 related to the cooperation between image output and audio reproduction. . The instruction decoding unit 20 decodes the display list 12, transmits the decoding results of the graphic lists G00 to G05 among the decoding results to the image decoding unit 22, and the decoding results of the audio lists S00 to 02 to the audio decoding unit 21. Send to. The image decoding unit 22 performs various graphics processing based on the decoding results of the graphics list G00 to G05 in the instruction decoding unit 20. The result of the various graphics processing is supplied to the LCD 1 and the LCD 1 displays the graphics.

  As the external memory 25, in addition to a plurality of NOR memories 26 connected by an SRAM bus, a plurality of NAND memories 27 capable of batch access of a large amount of information and suitable for storing image information are included in the SRAM logic system ( It is connected to a common memory bus 29 via an expansion RAM controller 28 having an interface circuit so that it can be connected by an SRAM + α bus). As the information stored in the NAND memory 27 and the NOR memory 26, it is possible to store both the image and the sound in the same memory. However, in this embodiment, the image information is stored in the NAND memory 27 and the sound information is NOR. It is stored in the memory 26. As a result, it is possible to give priority to audio playback due to the difference in memory access speed, and use it as a “big hit” acoustic foreplay function, and then meet recent demands to improve playability by developing images. it can. Note that a predetermined interface circuit may be included between the functional blocks for data consistency or the like, but these are omitted in the drawing.

  When storing images and sound in the NAND memory 27, the sound data is much smaller than the image data compared to the unit having the sector 280 structure shown in FIG. When small audio playback is performed, random access is frequently performed as illustrated in FIG. In the NAND memory 27, since frequent READ occurs, the entire NAND memory 27 or blocks are erased and programmed frequently, and the audio reproduction control sometimes fails. As shown in FIG. 5 (c), when generating voice data, it is possible to avoid such a problem by leaving the data empty state 290 "empty" until the start of the sector. Become.

  In drawing, a plurality of source image data are read out, image synthesis is performed, and synthesized image data obtained as a result of the image synthesis is written into the VRAM 23. At this time, the display circuit 24 reads the already synthesized image data from the display area and outputs it to the LCD 1 in units of pixel data.

  However, here, in the gaming machine, as a result of performing predetermined image processing (for example, flip, scaling, gamma correction, etc.) in the display circuit 24, a malfunction on the display screen occurs and the screen freezes. However, the conventional apparatus cannot check whether the cause is the output of the display circuit. Further, since the CPU has not been able to understand the cause, it cannot even be rebooted, and sometimes the display stays in a malfunctioning state. A normal CPU uses a watchdog timer, for example, as a function to monitor the system status and check normal operation. On the other hand, an obvious malfunction such as freeze can be confirmed to the player. However, since the CPU cannot detect such a situation, an appropriate process cannot be automatically performed. However, in this embodiment, since the output of the display circuit 24 is returned to the VRAM 23, the CPU 10 executes the drawing circuit (not shown) and the program procedure to be processed by the display circuit 24 from the original image data as it is. Will be able to trace. As a result, malfunction during program execution can be detected. The detected CPU 10 performs control to redraw the screen, for example.

  Further, in the present embodiment, the size information after decompression of the compressed data is issued on the CPU 10 side, and the size information is included in the compressed data stored in the external memory 25. As a result, when the size information is included only in the external memory 25 side, if the compressed data itself is broken, the size information held by the compressed data itself is also broken. Data may be destroyed, and as a result, there is a visual problem that an image already displayed on the image is destroyed. On the other hand, when the size information is issued only on the CPU 10 side, the broken data is written, but it was not automatically detected that it was broken. However, in this embodiment, both have size information. Can be detected automatically.

  That is, the size information is included in both the transfer command and the compressed data, and the size from the transfer command is prioritized so that the data is not destroyed even when the compressed data is broken. Further, when the size information of both does not match, it is configured to automatically detect that the compressed data is broken.

Further, as shown in FIG. 2, the audio logic 17 includes an audio decoding unit 21. The audio decoding unit 21 performs various types of audio processing based on the decoding results of the audio lists S00 to S02 in the instruction decoding unit 20. The results of the various audio processes are supplied to the speaker 2, and the speaker 2 performs audio output.
In this embodiment, the audio decoding unit 21 of the audio logic 17 is controlled via the instruction decoding unit 20 of the graphics logic 6. Conventionally, a voice generation command for performing voice processing has a command system different from that of a drawing command, or a different LSI chip is used, so that the instructions are not linked to each other. Therefore, while it was necessary to create a program while calculating the timing for each audio and drawing program unit, in the field of gaming machines, the collaboration effect of video and audio is becoming more and more recent. At the same time, since the output control of drawing and sound reproduction can be integrated in one command system, it is possible to perform finer control that exhibits the synergistic effect of video and sound more finely. In addition, since the sound effect and the video effect can be programmed, the LSI chip is easy to use for the program creator.

  That is, for example, outputting a certain piece of music at the same time as the generation of an image of a certain material as image information, or uttering a sound a predetermined time prior to image output, aiming at the appearance effect of an accessory on a gaming machine, Or, it becomes easy to reproduce music from one material with a predetermined time delay after image output.

  FIG. 3 is a block diagram illustrating details of the decoder portion of the graphics logic 6, and FIG. 4 is a flowchart showing the decoding operation. 6 and 7 are a flowchart illustrating the conventional decoding operation and a timing chart showing the timing of starting and completing decoding in comparison with the decoder operation of this embodiment.

  The image decoding unit 22 includes a plurality (two in the present embodiment) of pixel decoders 30 and 30 and a plurality (two in the present embodiment) of α decoders 31 and 31. The bus control unit 32 detects an empty decoder in the image decoding unit 22, and stores the decompressed data in the buffer unit 33 when there is a decoder 30, 30, 31, 31 that has completed decoding processing. At this time, the bus control unit 32 performs independent control without depending on the CPU 10. In this embodiment, the buffer unit 33 has the same number of distinct regions as the number of decodes of the image decoding unit 22, and the data A, B, C, and D obtained as a result of completing the pixel expansion are respectively The data is stored in the data area of the corresponding buffer unit 33. At the same time, since the decoder is in an empty state, that is, from the operating state to the standby state, the compressed data to be newly decoded is fetched from the NAND memory 27 as the external memory 25. Meanwhile, the CPU 10 that processes the drawing command only needs to be secured for a drawing command that does not depend on the data transfer operation between the image decoding unit 22 and the buffer unit 33. The instruction decoding unit 20 receives a drawing command from the CPU 10 and refers to the expansion (decompression) area table, and specifies the address of the compressed data stored in the NAND memory 27 and the expansion data size after expansion. Check the size. The development area table serves as an index for preventing inconvenience in the development of file data by performing batch reading and writing when the file data is large in size. Transfer control of file data from the NAND memory 27 is performed via the bus control unit 32.

  The bus control unit 32 detects whether each of the two pixel decoders 30 and 30 and the two α decoders 31 and 31 is in an operating state or in a standby state. It is determined to determine whether or not to operate the decoder, and the operation of each decoder 30, 30, 31, 31 is controlled. Here, the operation state is status information indicating whether each of the decoders 30, 30, 31, and 31 of the image decoding unit 22 is in a standby state or during an expansion operation. The CPU 10 controls other peripheral devices other than the present decoding device connected to the CPU bus 34, and reads the development information for one frame once in the idle time of the control. The decompression information includes a plurality of compressed data to be decompressed per frame and a header portion that defines attributes of the compressed data. The header part analysis is performed with reference to the development area table, and the pixel start value for starting the pixel expansion operation and the information of the α start value for starting the α expansion operation are expanded. This is a signal for operating the decoders 30 and 30 and the free α decoders 31 and 31. That is, until the next frame development information is confirmed from the CPU 10, the operation is independent of the CPU 10, and processing such as acceptance of drawing commands and pre-processing is performed in advance independently of the decoder and can be decoded. In this state, the decoding process is performed. The decoding process is performed when the operations of the empty pixel decoders 30 and 30 and the empty α decoders 31 and 31 become possible. The buffer unit 33 temporarily holds the result of the completed decoding process, so that the free state of the image decoding unit 22 can be secured.

  For the material stored in the VRAM 23, a status flag indicating whether or not each material is ready for drawing has one status flag corresponding to “1”, “0”, etc. as shown in the figure, for example. It is held like a management table. Thereby, the timing of drawing control and decoding control can be matched. In other words, it is possible to start the decoding control after confirming the decodable state, or to wait for the decoding process until the status flag changes. In particular, when there are a plurality of decoders, such timing is essential.

  In the conventional example shown in FIGS. 6 and 7, first, the blending operation of the conventional pixel decoding and α decoding is confirmed. Here, α blending is a method of blending two pieces of image data using an α value as a value indicating transparency in order to display an image including transparent or translucent pixels. Since the image data is compressed (encoded) by an appropriate compression method, it is decompressed (decoded). However, in conventional α blending, (1) the upper CPU always checks the completion of decoding, There is a problem that the load on the CPU increases. In addition, (2) since the operation of the pixel decoder and the operation of the α decoder are integrated in time series, the next decoding process is started only after the operations of the continuous pixel decoder and α decoder are completed.

  On the other hand, the image decoding unit 22 of the present embodiment shown in FIGS. 3 and 4 includes a plurality of pixel decoders 30 for pixel expansion and a plurality of α decoders 31 for α expansion. In the flowchart of this embodiment shown in FIG. 4, the determination of data acquisition and decoder completion confirmation has the same function, but conventionally it can be controlled only in a serial relationship, and the decoding of pixels and α is completed. However, the load on the CPU 10 is required and the timing span 35 of the decoding process is long (see FIG. 7). 31 can be operated individually, and these controls are performed by bus control, so the load on the CPU can be reduced. In the present embodiment, the pixel data and α data obtained as a result of the expansion are stored continuously in the same pixel and have the same frame area, so that the reading process in units of pixels can be efficiently performed. It can be carried out.

  In addition, the said embodiment is an illustration of this invention, and it cannot be overemphasized that this invention is not meant to be limited only to the said embodiment.

1A Signal processing system 1 LCD
2 Speaker 3 Motor 4 LED
5 Integrated LSI (signal processing equipment)
6 Graphics logic 7 Audio logic 8 Motor control logic 9 LED control logic 10 CPU
11 Instruction Group 12 Display List 13 Control Driver 22 Image Decoding Unit 25 External Memory 26 NOR Memory 27 NAND Memory

Claims (8)

A signal processing device configured as an LSI chip whose operation is controlled by a command from a host CPU,
Graphics logic for controlling the output of the image data displayed on the display means, and audio logic for controlling the output of the audio data output from the audio output means,
The graphics logic includes an instruction decoding unit that decodes an instruction of the host CPU and an image decoding unit, and the audio decoding unit in the audio logic operates according to an instruction via the instruction decoding unit. A signal processing device.   A display list that is issued by the display list issuing means and that describes a series of transfer commands to be executed by the signal processing device in a substantially time-series manner is supplied to the command decoding unit, so that the graphics logic, the audio The signal processing apparatus according to claim 1, wherein each of the logics is controlled in a substantially time-series manner. In the display list, a plurality of graphics lists and a plurality of audio lists are described as the series of transfer instructions,
The instruction decoding unit decodes the display list,
The image decoding unit performs various graphics processing based on the decoding result of each of the graphics lists in the instruction decoding unit,
The signal processing apparatus according to claim 2, wherein the voice decoding unit performs various types of voice processing based on a decoding result of each of the voice lists in the instruction decoding unit. A signal processing device according to any one of claims 1 to 3,
Display means connected to the image decoding unit for displaying graphics;
A signal processing system comprising: audio output means connected to the audio decoding unit for outputting audio. A display list issuing means for issuing a display list in which a series of transfer commands to be executed by the signal processing device is described in a substantially time-series manner;
A display list that is issued by the display list issuing means and that describes a series of transfer instructions to be executed by the signal processing device in a substantially time-series manner is supplied to the instruction decoding unit, so that the graphics logic, 5. The signal processing system according to claim 4, wherein each of the audio logics is controlled in a substantially time-series manner so that an image is displayed on the display unit and a sound is output from the audio output unit. In the display list, a plurality of graphics lists and a plurality of audio lists are described as the series of transfer instructions,
The instruction decoding unit decodes the display list,
The image decoding unit performs various graphics processing based on the decoding result of each of the graphics lists in the instruction decoding unit,
The signal processing system according to claim 5, wherein the voice decoding unit performs various types of voice processing based on a decoding result of each of the voice lists in the instruction decoding unit.   A gaming machine comprising the signal processing device according to any one of claims 1 to 3.   A gaming machine comprising the signal processing system according to any one of claims 4 to 6.

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