JP4946041B2 - Surface emitting semiconductor laser device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a surface emitting semiconductor laser device used as a light source for optical information processing or high-speed optical communication, and a method for manufacturing the same.

  In recent years, interest in a surface-emitting semiconductor laser (Vertical-Cavity Surface-Emitting Laser diode: hereinafter referred to as VCSEL) has increased in technical fields such as optical communication and optical recording. VCSELs are not available in edge-emitting semiconductor lasers that have low threshold currents, low power consumption, can easily obtain a circular light spot, and can be evaluated in a wafer state or a two-dimensional array of light sources. Has excellent features. Taking advantage of these features, demand as a light source in the communication field is particularly expected.

  In order to improve the reliability of the VCSEL and improve the operating life, several techniques for protecting the VCSEL from external moisture and moisture have been disclosed. For example, in Patent Document 1, as shown in FIG. 17, mesa etching is performed on a substrate, two LEDs (43, 43 ′) are kept connected, and confinement with a high Al content exposed by etching is performed. The layers (30, 34) are oxidized at 600 ° C. for 5 minutes to form natural oxide film passivation films (46, 46A), and then singulation is performed on the surfaces (45, 45 ′).

  In Patent Document 2, a hole that has been etched from the surface of the VCSEL to the oxidized region is covered with a moisture permeation protection wall, thereby preventing moisture from entering the hole. The protective wall preferably uses a silicon nitride layer having a thickness of 300 nm or more.

  In Patent Document 3, dry etching using nitrogen-chlorine mixed gas plasma is performed when forming a mesa, and a nitride-based layer is formed on a semiconductor surface layer simultaneously with the etching, and nitride film passivation treatment is performed. It is carried out. Thereby, since a natural oxide film is not formed on the base of the nitride film, the adhesion and moisture resistance of the nitride film can be improved.

JP 2000-208811 A JP 2003-204117 A JP 2004-22618 A

  FIG. 18 is a diagram showing a cross section of a VCSEL having a conventional post structure. On an n-type GaAs substrate 1, a lower DBR 2 including an n-type AlGaAs semiconductor layer, an active region 3, a p-type current confinement layer (AlAs oxide layer) 4, an upper DBR 5 including a p-type AlGaAs semiconductor layer, a p-type The GaAs contact layer 6 is formed. An annular trench or groove 7 reaching from the contact layer 6 to a part of the lower DBR 2 is formed, and a cylindrical post P is formed. An interlayer insulating film 8 is formed on the substrate surface including the trench 7. A contact hole is formed in the interlayer insulating film 8 at the top of the post, and the p-side upper electrode 9 is ohmically connected to the contact layer 6 through the contact hole. The upper electrode 9 has an opening 9a for emitting laser light. An n-side lower electrode 10 is formed on the back surface of the substrate.

  When such a VCSEL is driven under high temperature and high humidity (85 ° C., 85%, etc.) in a bare chip state, the lifetime tends to be shorter than when it is driven under room temperature and low humidity. One of the causes is a failure mode that leads to disconnection of the upper electrode due to the transformation of the p-type GaAs contact layer 6. When the individual VCSEL chip or the VCSEL array chip is divided, the interlayer insulating film 8 is patterned so as to expose the region 11 to be diced. For this reason, the GaAs contact layer 6 which is the uppermost layer of the semiconductor layer is exposed. Regardless of before and after dicing, a part of the surface of the GaAs contact layer 6 exposed by the interlayer insulating film 8 is exposed to the outside, so that moisture and moisture are easily absorbed. In particular, when the VCSEL is energized under high temperature and high humidity, the GaAs contact layer 6 is transformed, and the lower portion of the interlayer insulating film 8 is eroded, whereby the interlayer insulating film 8 is lifted and the upper electrode 9 may be disconnected. . This is considered to be due to the fact that a current path passing through the chip side surface (dicing surface) from the upper electrode 9 to the lower electrode 10 is formed due to high humidity.

  In order to use the VCSEL in the bare chip state, it is necessary to adopt a structure in which such a failure does not occur. In Patent Document 1, a layer having a high Al content is oxidized at a high temperature of 600 ° C. and does not effectively protect the GaAs contact layer 6 on the surface. Further, neither of Patent Documents 2 and 3 suggests a configuration and action for protecting the GaAs contact layer from the outside and preventing the contact layer from being altered.

  The present invention has been made to solve the above-described conventional problems, and provides a surface-emitting type semiconductor laser device that suppresses the occurrence of a failure in a high-temperature and high-humidity environment and has a long lifetime, and a method for manufacturing the same. Objective.

  The surface-emitting type semiconductor laser device according to the present invention includes a second conductivity type second semiconductor that forms a resonator together with at least a first semiconductor multilayer film of the first conductivity type, an active region, and a first semiconductor multilayer film on a substrate. The semiconductor multilayer film and the semiconductor layer including the contact layer are laminated, and the light emitting portion that emits laser light and the pad formation region are separated by a groove formed in the semiconductor layer. An outer peripheral groove having a depth reaching the substrate by etching the semiconductor layer is formed at the outer edge of the pad forming area, and the side surface of the pad forming area exposed by the outer peripheral groove and the surface of the pad forming area are covered with an insulating film. ing.

  Since the contact layer on the surface of the semiconductor layer in the pad forming region is covered with the insulating film, the contact layer is not exposed to external moisture or moisture. Thereby, it is possible to prevent the contact layer from being deformed or corroding with the modification. Further, the side surface of the pad forming region exposed by the outer peripheral groove is also protected from external moisture and moisture.

  Preferably, the insulating film is formed so as to cover the groove and the light emitting portion simultaneously with the pad forming region. A contact hole for exposing the contact layer is formed in the insulating film of the light emitting portion. Further, the insulating film is patterned so as to expose the substrate in the outer peripheral groove. A metal layer that is ohmically connected to the contact layer through a contact hole is formed in the light emitting portion, and an opening for emitting laser light is formed in the metal layer. For example, a silicon oxide film or a silicon nitride film is used as the insulating film.

  The outer peripheral groove defines a dicing area when the substrate is cut. The substrate is cut by a dicer along the outer peripheral groove and separated into individual chips. The outer peripheral groove has a depth that contacts the surface of the substrate or a depth obtained by partially etching the surface of the substrate. Since the substrate is very thick compared to the stacked semiconductor layers, there is no effect even if the semiconductor layers are somewhat over-etched. Further, since the substrate has moisture resistance as compared with the semiconductor layer stacked on the substrate, it is not always necessary to protect the side surface of the substrate cut by dicing with an insulating film.

  Preferably, the first and second semiconductor multilayer films are made of a group III-V semiconductor layer containing Al, and the contact layer is made of a GaAs layer. Furthermore, the light emitting unit includes a current confinement layer in which a part of the semiconductor layer containing Al is selectively oxidized between the first and second semiconductor multilayer films.

  The metal layer formed in the light emitting part is connected to the electrode pad formed on the pad formation region via the wiring metal. The metal layer is made of gold or a laminate of gold and titanium. The opening of the metal layer is aligned with the opening of the conductive region surrounded by the oxidized region of the current confinement layer. The size of the opening in the metal layer and the current confinement layer determines the mode of the emitted laser light.

  The method for manufacturing a surface-emitting type semiconductor laser device according to the present invention includes a second conductive material that constitutes a resonator together with at least a first conductive type first semiconductor multilayer film, an active region, and a first semiconductor multilayer film on a substrate. Laminating a semiconductor layer including a second semiconductor multilayer film of a mold and a contact layer, forming a first mask pattern on the semiconductor layer, and etching the semiconductor layer using the first mask pattern Forming a first groove defining a light emitting portion, forming a second mask pattern on the semiconductor layer, etching the semiconductor using the second mask pattern, and defining a dicing region Forming a second groove, forming an insulating film on the semiconductor layer including at least the first groove and the second groove, patterning the insulating film, and Forming a contact hole in the edge film; forming an upper electrode pattern connected to the contact layer through the contact hole; and cutting the substrate along a second groove. ing.

  Preferably, the second groove has a depth from the contact layer to the substrate. Further, when patterning the insulating film, a part of the insulating film in the second groove may be removed to expose a part of the substrate. In this case, the region of the substrate exposed by the insulating film is cut.

  According to the present invention, the side surface and the entire surface of the pad forming region exposed by the outer peripheral groove are covered with the insulating film, so that the contact layer on the surface of the pad forming region is affected by moisture and moisture from the outside. You will not receive it. Thereby, the contact layer is denatured or corroded, and accordingly, the insulating layer on the contact layer is prevented from peeling off or the electrode wiring is prevented from being disconnected. When the surface-emitting type semiconductor laser device according to the present invention is used in a high-temperature and high-humidity environment, it is not always necessary to seal the surface-emitting type semiconductor laser device with a resin or a can. It is possible.

  The best mode for carrying out the present invention will be described below with reference to the drawings.

  FIG. 1 is a plan view of a wafer on which a plurality of VCSELs are formed, FIG. 2 is a plan view of the VCSEL according to the first embodiment of the present invention, and FIG. 3 is a cross-sectional view taken along line AA of FIG. . As shown in FIG. 1, a plurality of VCSELs 100 are formed on the wafer W, and each VCSEL 100 is cut along a scribe line (or dicing surface) S into a rectangular shape by a scribe device or a dicing device.

  As shown in FIGS. 2 and 3, the VCSEL 100 includes an n-side electrode 150 on the back surface of an n-type GaAs substrate 102, and an n-type GaAs buffer layer 104 and an n-type AlGaAs semiconductor multilayer on the substrate 102. Lower DBR (Distributed Bragg Reflector) 106 made of film, active region 108, current confinement layer 110 made of p-type AlAs, upper DBR 112 made of p-type AlGaAs semiconductor multilayer film, p-type GaAs A semiconductor layer including the contact layer 114 is stacked.

  In the substrate 102, a ring-shaped groove 116 formed by etching the semiconductor layer is formed. The groove 116 has a depth that reaches a part of the lower DBR 106 from the contact layer 114, and the groove 116 defines a cylindrical post P that is a laser light emitting part. The post P forms a resonator structure with the lower DBR 106 and the upper DBR 112, and the active region 108 and the current confinement layer 110 are interposed therebetween. The current confinement layer 110 includes an oxidized region obtained by selectively oxidizing AlAs exposed on the side surface of the post P and a conductive region surrounded by the oxidized region, and confines current and light in the conductive region.

A pad forming region 118 separated from the post P by a groove 116 is further formed on the substrate. The pad forming region 118 includes the same semiconductor layer as the post P, and an outer peripheral groove 140 corresponding to the dicing region is formed on the outer edge of the pad forming region 118. The outer peripheral groove 140 has a depth that reaches the surface of the substrate 102 or a part of the substrate 102 from the contact layer 114. The outer circumferential groove 140 has a certain width, which is larger than the kerf width of the dicing apparatus, and the substrate 102 is cut at the dicing surface S.

  An interlayer insulating film 120 is formed on the entire surface of the substrate covering the groove 116 and the outer peripheral groove 140. That is, the interlayer insulating film 120 includes the surface of the post P, the side surface of the post P exposed by the groove 116, the groove 116, the side surface of the pad forming region 118 exposed by the groove 116, the surface of the pad forming region 118, and the outer peripheral groove. The side surface of the pad forming region 118 exposed by 140 is covered. The interlayer insulating film 120 is patterned using a predetermined mask, and a ring-shaped contact hole is formed in the interlayer insulating film 120 at the top of the post P to expose the contact layer 114. Further, the interlayer insulating film 120 is patterned so as to expose the substrate 102 at the bottom of the outer peripheral groove 140. The exposed region of the substrate becomes a region 102a to be diced.

  A p-side upper electrode 130 is formed on the top of the post P via an interlayer insulating film 120, and the upper electrode 130 is ohmically connected to the contact layer 114 via a contact hole. In the center of the upper electrode 130, a circular opening 132 that defines a laser light emission region is formed. The opening 132 defines a laser light emission window, which is blocked by the interlayer insulating film 120 and protected so that the GaAs contact layer 114 is not exposed to the outside. A circular electrode pad 134 is formed in the pad forming region 118 with an interlayer insulating film 120 interposed therebetween. The electrode pad 134 is connected to the p-side upper electrode 130 through an electrode wiring 136 extending through the groove 116.

  When the VCSEL 100 is driven, a forward bias voltage is applied to the p-side upper electrode 130 and the n-side lower electrode 150, and the laser light generated in the active region 108 is emitted from the opening 132 in a direction substantially perpendicular to the substrate 102. The

  In the VCSEL 100 of this embodiment, the side surface and the surface of the pad formation region 118 exposed by the outer peripheral groove 140 are covered with the interlayer insulating film 120, and the epitaxially grown GaAs and AlGaAs are not exposed, thereby realizing a highly reliable operation. can do. In particular, when driving in a high temperature and high humidity environment, the contact layer 114 is shielded from external moisture and moisture, and no current path is formed on the side surface of the pad formation region 118. In other words, the corrosion of the interlayer insulating film 120 is prevented, the interlayer insulating film 120 is prevented from being peeled off, the interlayer insulating film 120 is prevented from being peeled off, and the electrode wiring 136 is prevented from being disconnected. Although the substrate 102 is exposed by the dicing surface S, the substrate 102 is not necessarily necessarily covered with a protective film because the substrate 102 has higher moisture resistance than an epitaxially grown semiconductor layer. However, the present invention does not prevent the dicing surface S from being covered with the protective film.

  Next, a second embodiment of the present invention will be described with reference to FIG. The VCSEL according to the second embodiment is a 1 × 4 multi-spot type VCSEL array. As shown in the figure, the VCSEL 100a has four posts P arranged in a straight line on the substrate 102. Each post P is surrounded by a groove 116. A wiring electrode 136 and an electrode pad 134 connected to the upper electrode 130 of the post P are formed in the pad forming region 118 separated from the groove 116. A rectangular outer peripheral groove 140 is formed on the outer edge of the pad forming region 118 so as to surround the four posts P, the wiring electrode 136, and the electrode pad 134. Also in the second embodiment, the side surface and the surface of the pad forming region 118 exposed by the outer peripheral groove 140 are covered with the interlayer insulating film 120, thereby completely preventing the contact layer 114 from being exposed, and the current path on the side surface of the chip. Generation is prevented. The number of posts formed on the array is not limited to four, and may be an array in which the posts are arranged in a secondary shape.

Next, a VCSEL manufacturing method according to the first embodiment will be described with reference to FIGS. First, as shown in FIG. 5A, an n-type n-type substrate having a carrier concentration of 1 × 10 ¹⁸ cm ⁻³ and a film thickness of about 0.2 μm is formed on the GaAs substrate 102 by metal organic chemical vapor deposition (MOCVD). A type GaAs buffer layer 104 is laminated, and Al _0.9 Ga _0.1 As and Al _0.3 Ga _0.7 As are alternately laminated thereon for 40.5 periods so that each film thickness becomes 1/4 of the wavelength in the medium. Lower n-type DBR 106 having a carrier concentration of 1 × 10 ¹⁸ cm ⁻³ and a total film thickness of about 4 μm, an undoped lower Al _0.5 Ga _0.5 As spacer layer and an undoped quantum well active layer (thickness 90 nm, Al _0.11 Ga _0.89 As 3 layers of quantum well layers and a film thickness of 50 nm, 4 layers of Al _0.3 Ga _0.7 As barrier layer) and a film thickness of undoped upper Al _0.5 Ga _0.5 As spacer layer An active region 108, Type AlAs layer 110, a carrier concentration of 1 × 10 ¹⁸ to on the respective film thicknesses and Al _0.9 Ga _0.1 As and Al _0.3 Ga _0.7 As thereon were alternately 30 periodically laminated so that 1/4 of the wavelength in the medium An upper p-type DBR 112 having a cm ⁻³ and a total film thickness of about 2 μm and a p-type GaAs contact layer 114 having a thickness of about 10 nm and a carrier concentration of 1 × 10 ¹⁹ cm ⁻³ are sequentially stacked. The source gas is trimethylgallium, trimethylaluminum, arsine, the dopant material is cyclopentadinium magnesium for p-type, and silane for n-type. The substrate temperature during growth is 750 ° C. without breaking the vacuum. Then, the source gas was changed sequentially, and the film was formed continuously. Although not described in detail, in order to reduce the electrical resistance of the DBR, the film thickness obtained by gradually changing the Al composition from 90% to 30% at the interface between Al _0.9 Ga _0.1 As and Al _0.3 Ga _0.7 As is shown. It is also possible to provide a region of about 9 nm.

  Next, as shown in FIG. 5B, a resist mask R is formed on the crystal growth layer by a photolithography process, and a reactive ion etching using chlorine or chlorine and boron trichloride as an etching gas is performed in the middle of the lower DBR 106. Etching is performed until an annular groove 116 is formed as shown in FIG. As a result, a cylindrical or prismatic semiconductor pillar (post) P having a diameter of about 10 to 30 μm and a pad forming region 118 are formed around the semiconductor pillar (post) P.

  After removing the resist R, as shown in FIG. 6D, a resist mask R1 is formed by a photolithography process, and reactive ion etching using chlorine or chlorine and boron trichloride as an etching gas, or sulfuric acid and peroxide. An outer peripheral groove 140 is formed on the outer edge of the pad forming region 118 using hydrogen water as an etchant. The outer peripheral groove 140 reaches the substrate 102, and a part of the substrate 102 is exposed as a dicing region 102a.

Next, as shown in FIG. 6E, after removing the resist mask R1, the substrate is exposed to a steam atmosphere at, for example, 340 ° C. for a certain period of time to perform an oxidation treatment. Since the AlAs layer constituting the current confinement layer 110 has a significantly faster oxidation rate than the Al _0.9 Ga _0.1 As layer and Al _0.3 Ga _0.7 As layer that also constitute a part thereof, the post shape is reflected from the side surface of the post P. The oxidized region 110a is formed, and the non-oxidized region remaining without being oxidized becomes a current injection region or a conductive region.

  Next, as shown in FIG. 6F, an interlayer insulating film 120 made of SiN is deposited on the entire surface of the substrate including the groove 116 and the outer peripheral groove 140 using a plasma CVD apparatus. After that, as shown in FIG. 7G, the interlayer insulating film is etched using a normal photolithography process and sulfur hexafluoride etching gas to form a ring-shaped contact hole 120a in the interlayer insulating film 120 at the top of the post P. The contact layer 114 is exposed, and at the same time, the interlayer insulating film 120 covering the substrate 102 in the outer peripheral groove 140 is removed to expose the dicing region 102a.

  Next, a resist pattern is formed on the top of the post P and the pad formation region 118 using a photolithography process, and Au is used as the p-side electrode material from 100 to 1000 nm on the entire surface of the substrate by using an EB vapor deposition device from above. Evaporate 600 nm. Next, the resist pattern is peeled off. At this time, Au on the resist pattern is removed, and the upper electrode 130, the electrode pad 134, and the wiring electrode 136 are completed. In the center of the upper electrode 130, an opening 132 that matches the opening of the current confinement layer 110 is formed. Laser light is emitted from the portion without the p-side electrode, that is, the central portion of the post, and the exit diameter is preferably about 3 to 20 μm. Au / Ge is deposited on the back surface of the substrate as an n-side electrode.

  Thereafter, annealing is performed at an annealing temperature of 250 ° C. to 500 ° C., desirably 300 ° C. to 400 ° C. for 10 minutes. The annealing time is not limited to 10 minutes, and may be between 0 and 30 minutes. Further, the deposition method is not limited to the EB deposition machine, and a resistance heating method, a sputtering method, a magnetron sputtering method, and a CVD method may be used. Also, the annealing method is not limited to thermal annealing using a normal electric furnace, and the same effect can be obtained by flash annealing using infrared rays, laser annealing, high-frequency heating, electron beam annealing, and lamp heating annealing. Is also possible.

  Finally, the substrate is cut along the dicing surface S of the substrate, that is, the exposed region 102a, and individual VCSEL chips 100 can be obtained.

  In addition, the said manufacturing method is a preferable example, Comprising: It is not necessarily limited to this. Although the current confining layer oxidation step is performed after the outer peripheral groove 140 is formed, the present invention is not limited thereto, and may be performed after the formation of the groove 116 and before the outer peripheral groove 140 is formed.

  FIG. 8 is a schematic cross-sectional view showing an example of a package (module) of a semiconductor laser device on which a chip of a VCSEL array is mounted. In the package 300, a chip 310 on which a VCSEL array is formed is fixed on a submount 320 on a metal stem 330. The conductive leads 340 and 342 are inserted into through holes (not shown) of the stem 330, and one lead 340 is electrically connected to the n-side lower electrode 150 formed on the back surface of the chip 310, The other lead 342 is electrically connected to an electrode pad 134 formed on the upper surface of the chip 310 via a bonding wire or the like.

  A ball lens 360 is fixed in the exit window 352 of the cap 350. The optical axis of the ball lens 360 is positioned so as to coincide with the approximate center of the opening 132 of the upper electrode 130. Further, the distance between the chip 310 and the ball lens 360 is adjusted so that the ball lens 360 is included within the radiation angle θ of the laser beam from the chip 310. When a forward voltage is applied between the leads 340 and 342, laser light is emitted from the chip 310 and output to the outside through the ball lens 360. Note that a light receiving element for monitoring the light emission state of the VCSEL may be included in the cap.

  FIG. 9 is a diagram showing the configuration of still another package, and is preferably used in a spatial transmission system described later. In the package 302 shown in the drawing, a flat glass 362 is fixed in an emission window 352 at the center of the cap 350 instead of using the ball lens 360. The center of the flat glass 362 is positioned so as to substantially coincide with the center of the chip 310. The distance between the chip 310 and the flat glass 362 is adjusted so that the opening diameter of the flat glass 362 is not less than the radiation angle θ of the laser beam from the chip 310.

  FIG. 10 is a cross-sectional view showing a configuration when the package or module shown in FIG. 8 is applied to an optical transmitter. The optical transmission device 400 includes a cylindrical housing 410 fixed to the stem 330, a sleeve 420 integrally formed on an end surface of the housing 410, a ferrule 430 held in the opening 422 of the sleeve 420, a ferrule And an optical fiber 440 held by 430.

  An end of the housing 410 is fixed to a flange 332 formed in the circumferential direction of the stem 330. The ferrule 430 is accurately positioned in the opening 422 of the sleeve 420 and the optical axis of the optical fiber 440 is aligned with the optical axis of the ball lens 360. The core wire of the optical fiber 440 is held in the through hole 432 of the ferrule 430.

  The laser light emitted from the surface of the chip 310 is collected by the ball lens 360, and the collected light is incident on the core wire of the optical fiber 440 and transmitted. Although the ball lens 360 is used in the above example, other lenses such as a biconvex lens and a plano-convex lens can be used. Further, the optical transmission device 400 may include a drive circuit for applying an electrical signal to the leads 340 and 342. Furthermore, the optical transmission device 400 may include a reception function for receiving an optical signal via the optical fiber 440.

  FIG. 11 is a diagram showing a configuration when the package shown in FIG. 9 is used in a spatial transmission system. The spatial transmission system 500 includes a package 300, a condenser lens 510, a diffusion plate 520, and a reflection mirror 530. In the spatial transmission system 500, instead of using the ball lens 360 used in the package 300, a condensing lens 510 is used. The light condensed by the condenser lens 510 is reflected by the diffusion plate 520 through the opening 532 of the reflection mirror 530, and the reflected light is reflected toward the reflection mirror 530. The reflection mirror 530 reflects the reflected light in a predetermined direction and performs optical transmission. In the case of a spatial transmission light source, a multi-spot type VCSEL may be used to obtain a high output.

  FIG. 12 is a diagram illustrating a configuration example of an optical transmission system using a VCSEL as a light source. The optical transmission system 600 receives a light source 610 including a chip 310 on which a VCSEL is formed, an optical system 620 that collects laser light emitted from the light source 610, and the laser light output from the optical system 620. A light receiving unit 630 and a control unit 640 that controls driving of the light source 610 are included. The control unit 640 supplies a drive pulse signal for driving the VCSEL to the light source 610. Light emitted from the light source 610 is transmitted to the light receiving unit 630 via an optical system 620 by an optical fiber, a reflection mirror for spatial transmission, or the like. The light receiving unit 630 detects the received light with a photodetector or the like. The light receiving unit 630 can control the operation of the control unit 640 (for example, the start timing of optical transmission) by the control signal 650.

  Next, the configuration of an optical transmission device used in the optical transmission system will be described. FIG. 13 shows an external configuration of the optical transmission apparatus, and FIG. 14 schematically shows an internal configuration thereof. The optical transmission device 700 includes a case 710, an optical signal transmission / reception connector joint 720, a light emitting / receiving element 730, an electric signal cable joint 740, a power input unit 750, an LED 760 indicating that an operation is in progress, an LED 770 indicating occurrence of an abnormality, and a DVI. A connector 780 and a transmission circuit board / reception circuit board 790 are provided.

  A video transmission system using the optical transmission apparatus 700 is shown in FIGS. In these drawings, the video transmission system 800 uses the optical transmission device shown in FIG. 15 to transmit the video signal generated by the video signal generation device 810 to the image display device 820 such as a liquid crystal display. That is, the video transmission system 800 includes a video signal generation device 810, an image display device 820, a DVI electric cable 830, a transmission module 840, a reception module 850, a video signal transmission optical signal connector 860, an optical fiber 870, and a control signal cable. A connector 880, a power adapter 890, and an electric cable 900 for DVI are included.

  In the video transmission system described above, electrical signals are transmitted between the video signal generation device 810 and the transmission module 840, and between the reception module 850 and the image display device 820 using the electrical cables 830 and 900. Transmission between these signals is an optical signal. It is also possible to do this. For example, a signal transmission cable including an electrical / optical conversion circuit and an optical / electrical conversion circuit in a connector may be used instead of the electrical cables 830 and 900.

  The surface-emitting type semiconductor laser device according to the present invention can be used in the fields of optical information processing and optical high-speed data communication.

It is a figure which shows the wafer in which VCSEL was formed. It is a top view of VCSEL concerning the 1st example of the present invention. It is the sectional view on the AA line of FIG. It is a figure which shows VCSEL which concerns on the 2nd Example of this invention. It is process sectional drawing explaining the manufacturing method of VCSEL which concerns on the 1st Example of this invention. It is process sectional drawing explaining the manufacturing method of VCSEL which concerns on the 1st Example of this invention. It is process sectional drawing explaining the manufacturing method of VCSEL which concerns on the 1st Example of this invention. It is a schematic sectional drawing which shows the structure of the package which mounted the semiconductor chip in which VCSEL was formed. It is a schematic sectional drawing which shows the structure of another package. It is a schematic sectional drawing which shows the structure of the optical transmitter using the package shown in FIG. It is a figure which shows a structure when the package shown in FIG. 9 is used for a spatial transmission system. It is a block diagram which shows the structure of an optical transmission system. It is a figure which shows the external appearance structure of an optical transmission apparatus. 14A shows the internal structure of the optical transmission device, FIG. 14A shows the internal structure when the top surface is cut off, and FIG. 14B shows the internal structure when the side surface is cut off. It is a figure which shows the video transmission system using the optical transmission apparatus of FIG. It is the figure which showed the video transmission system of FIG. 15 from the back side. It is sectional drawing which shows the conventional VCSEL. It is sectional drawing which shows the conventional VCSEL.

Explanation of symbols

100: VCSEL 102: Substrate 104: Buffer layer 106: Lower DBR
108: Active region 110: Current confinement layer 112: Upper DBR 114: Contact layer 116: Groove 118: Pad formation basin 120: Interlayer insulating film 130: P-side upper electrode 132: Opening 134: Electrode pad 136: Wiring electrode 140: Outer periphery Groove 150: n-side lower electrode P: post S: dicing surface

Claims (18)

A semiconductor including at least a first semiconductor multilayer film of a first conductivity type, an active region, a second semiconductor multilayer film of a second conductivity type constituting a resonator together with the first semiconductor multilayer film, and a contact layer on a substrate A surface-emitting type semiconductor laser device in which layers are stacked, and a light emitting part that emits laser light and a pad forming region are separated by a groove formed in the semiconductor layer,
An outer peripheral groove having a depth reaching the substrate by etching the semiconductor layer is formed at the outer edge of the pad forming area, and the side surface of the pad forming area exposed by the outer peripheral groove and the surface of the pad forming area are covered with an insulating film. The surface emitting semiconductor laser device , wherein the insulating film is patterned to expose the substrate at the bottom surface of the outer peripheral groove . 2. The surface-emitting type semiconductor laser device according to claim 1, wherein the outer circumferential groove has continuous side and bottom depths from the contact layer to the substrate by etching the semiconductor layer . The surface-emitting type semiconductor laser device according to claim 1, wherein the contact layer is formed so as to cover the entire surface of the second semiconductor multilayer film . 4. The surface emitting semiconductor laser device according to claim 1, wherein the outer circumferential groove is a dicing region when the substrate is cut. 5. The insulating layer, the pad formation region and at the same time, the light emitting portion and covers the grooves, the insulating film of the light emitting portion is formed a contact hole, a surface according to 4 any one claims 1 Light emitting semiconductor laser device. 6. The surface-emitting type according to claim 5 , wherein a metal layer having an opening for emitting laser light is formed in the light emitting part, and the metal layer is connected to the contact layer through the contact hole. Semiconductor laser device. The surface light emission according to any one of claims 1 to 6, wherein the first and second semiconductor multilayer films are made of a group III-V semiconductor layer containing Al, and the contact layer is made of a GaAs layer. Type semiconductor laser device. The surface emitting semiconductor laser device according to claim 7 , wherein the light emitting unit includes a current confinement layer in which a part of a semiconductor layer containing Al is selectively oxidized. The surface according to any one of claims 1 to 8 , wherein an electrode pad is formed in the pad formation region via the insulating film, and the electrode pad is connected to a metal layer of the light emitting unit by a metal wiring. Light emitting semiconductor laser device. Module mounted with a surface-emitting type semiconductor laser device and the optical member according to 9 any one claims 1. An optical transmission device comprising: the module according to claim 10; and a transmission unit configured to transmit a laser beam emitted from the module via an optical medium. An optical space transmission device comprising: the module according to claim 10; and a transmission unit that spatially transmits light emitted from the module. An optical transmission system comprising: the module according to claim 10; and a transmission unit that transmits a laser beam emitted from the module. An optical space transmission system comprising the module according to claim 10 and a transmission means for spatially transmitting light emitted from the module. A semiconductor including at least a first semiconductor multilayer film of a first conductivity type, an active region, a second semiconductor multilayer film of a second conductivity type constituting a resonator together with the first semiconductor multilayer film, and a contact layer on a substrate Laminating layers;
Forming a first mask pattern on the semiconductor layer, etching the semiconductor layer using the first mask pattern, and forming a first groove separating a light emitting portion and a pad formation region ;
Forming a second mask pattern on the semiconductor layer , etching the semiconductor layer using the second mask pattern, and forming a second groove defining a dicing region having a depth reaching the substrate ; ,
Forming an insulating film on the semiconductor layer including at least the first groove and the second groove, and covering the side surface of the pad forming region exposed by the second groove and the surface of the pad forming region with the insulating film ;
Patterning the insulating film, forming a contact hole in the insulating film of the light emitting unit and exposing the substrate at the bottom surface of the second groove ;
Forming an upper electrode pattern connected to the contact layer through the contact hole;
Cutting the substrate exposed from the insulating film at the bottom surface of the second groove;
Manufacturing method of surface emitting semiconductor laser device having The manufacturing method according to claim 15, wherein the second groove has continuous side and bottom depths from the contact layer to the substrate by etching the semiconductor layer . The manufacturing method according to claim 15, wherein the contact layer is formed so as to cover the entire surface of the second semiconductor multilayer film . The semiconductor layer includes a current confining layer between the first and second semiconductor multilayer film, the manufacturing method includes the step of oxidizing the current confining layer after forming the first grooves, according to claim 15 Manufacturing method.

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