JP5087874B2 - Surface emitting semiconductor laser and manufacturing method thereof - Google Patents

Description

  The present invention relates to a surface-emitting type semiconductor laser used as a light source for optical information processing or high-speed optical communication, and a method for manufacturing the same, and more particularly to a technique for suppressing high-order transverse mode oscillation.

  In the technical fields such as optical communication and optical recording, interest in a surface-emitting semiconductor laser (Vertical-Cavity Surface-Emitting Laser diode: hereinafter referred to as VCSEL) is increasing. VCSELs are not available in edge-emitting semiconductor lasers that have low threshold currents, low power consumption, can easily obtain a circular light spot, and can be evaluated in a wafer state or a two-dimensional array of light sources. Has excellent features. Taking advantage of these features, demand as a light source in the communication field is particularly expected.

In order to stabilize the operating characteristics of the element and obtain a long operating life, it is necessary to improve the moisture resistance and pressure resistance of an insulating film used under a metal layer such as an electrode pad. Several proposals for such techniques have been made. For example, in the semiconductor device of Patent Document 1, a surface protective film is formed by sequentially laminating a first SiN layer, a SiO ₂ layer, and a _second SiN layer on an insulating film including an upper layer wiring on a substrate. . Thus, moisture that permeates and penetrates pinholes that are slightly present in the second SiN layer that forms the upper layer of the surface protective film is absorbed by the water-absorbing SiO ₂ layer.

  Patent Document 2 discloses that in an LED array, an interlayer insulating film between a wiring layer and a substrate is composed of a laminated film of an alumina film and a second insulating film, and pinholes are generated when the alumina film and the second insulating film are formed. The probability that the pinholes of both films overlap is very low, and as a result, an insulating film with few pinholes is obtained.

  In Patent Document 3, in a resonant diode, a moisture-resistant protective film made of an insulating material is formed, and the film thickness of the moisture-resistant protective film is an integral multiple of 1/2 of the wavelength. Preferably, the moisture resistant protective film is composed of silicon oxide and silicon nitride.

  In Patent Document 4, an oxide cavity partially penetrating the VCSEL structure is formed, silicon nitride (SiN) is formed as a first passivation on the surface of the oxide cavity, and silicon oxynitride is formed thereon as a second passivation. A nitride (SiON) is formed, and a pinhole that may exist in one of the passivations is covered with the other passivation.

In Patent Document 5, a polyimide protective film having a thermal linear expansion coefficient of 50 × 10 ⁻⁶ ° C. ⁻¹ or less is formed on the surface of the VCSEL laser structure, and in Patent Document 6, the total stress is 2. A polyimide protective film of 5 × 10 ² Pa · m or less is formed to prevent cracking and peeling of the polyimide protective film.

Japanese Patent Laid-Open No. 5-218015 JP 7-122781 A JP 2004-281929 A JP 2004-241777 A JP 2002-335045 A JP 2004-31633 A

  FIG. 19 is a plan view of a conventional VCSEL and a sectional view taken along line AA of FIG. The VCSEL has an n-type lower DBR (Distributed Bragg Reflector) 12, an active layer 14, a current confinement layer 16, a p-type upper DBR 18, a p-type GaAs on an n-type GaAs semiconductor substrate 10. The semiconductor layer of the contact layer 20 is laminated. The semiconductor layer stacked on the semiconductor substrate 10 is etched until a part of the lower DBR 12 is exposed, whereby a cylindrical post P is formed on the substrate. The top, side and bottom of the post P are covered with an interlayer insulating film or a protective film 22. A contact hole 24 is formed in the protective film 22 at the top of the post, and a p-side electrode 26 is formed there. An opening for emitting laser light is formed in the center of the p-side electrode 26. A circular electrode pad 28 for external connection is formed on the bottom of the post via an interlayer insulating film 22, and the electrode pad 28 is connected to the p-side electrode 26 by a lead wiring 30. An n-side electrode 32 is formed on the back surface of the semiconductor substrate 10.

  In such a VCSEL, when a single protective film is used as the insulating film 22 on the n-type DBR 12 and the metal electrode pad 28 is disposed on the protective film, there are the following problems.

  If the protective film 22 sandwiched between the n-type DBR 12 and the electrode pad 28 has a low resistance portion due to contamination, pinholes, or microcracks during deposition, for example, the probe pin is brought into contact with the electrode pad 28 and reversed. When an abnormal leakage current measurement is performed in which a current is applied in the direction or when a forward current is applied in a burn-in test, excess current flows to the n-type lower DBR 12 or the n-type substrate 10 through the abnormal current path, and the VCSEL element is destroyed. Will be. For this reason, the manufacturing yield of the VCSEL is deteriorated and the element reliability is adversely affected.

  Further, when the alignment electrode 34 formed for the purpose other than the electrode pad 28 is formed on the n-type DBR 12, an abnormality such as a pinhole as described above is formed in the protective film below the alignment electrode 34. If the probe pin is accidentally contacted with the alignment electrode 34 and burn-in is performed, excess current flows through the abnormal current path, and the VCSEL is destroyed. Further, although different from the configuration shown in FIG. 19, even in a VCSEL of the type in which the electrode pad 28 is formed on the p-type DBR 18 through an insulating film, if the insulating film has a defect such as a pinhole, the withstand voltage decreases. However, similar problems occur when a voltage is applied to the electrode pads.

  The present invention solves the above-described conventional problems, increases the withstand voltage in a region where a metal layer such as an electrode pad for external connection is formed, and improves the yield and reduces the cost, and the surface emitting semiconductor laser An object is to provide a manufacturing method.

  The surface-emitting type semiconductor laser according to the present invention improves the insulating properties of the protective film in order to suppress contamination of the protective film under the metal part such as the electrode pad and the abnormal current path due to pinholes and cracks. As a first solution, an insulation treatment (proton implantation) is performed on the surface of the semiconductor layer on which the protective film is formed to improve the withstand voltage. As a second solution, a protective film under the metal part such as an electrode pad is formed in a multilayer structure of two or more layers to improve the withstand voltage.

  The surface-emitting type semiconductor laser according to the present invention includes at least a first conductivity type first semiconductor multilayer reflection film, an active region, and a second conductivity type second semiconductor multilayer reflection film on a substrate. A post is formed by removing the semiconductor film from the semiconductor multilayer reflective film to a part of the first semiconductor multilayer reflective film, and a laser beam is emitted from the top of the post. The second semiconductor at the top of the post An electrode pad electrically connected to the multilayer reflective film; and a multilayer insulating film formed between the electrode pad and the first semiconductor multilayer reflective film at the bottom of the post.

  Preferably, the multilayer insulating film includes at least a first insulating film and a second insulating film, the first insulating film covers the first semiconductor multilayer reflective film at the bottom of the post, and the second insulating film is the first insulating film. Cover the insulating film and the side of the post. Alternatively, the first insulating film may cover the first semiconductor multilayer reflective film and the post side surface at the bottom of the post, and the second insulating film may cover the first insulating film under the electrode pad.

In the case of a surface emitting semiconductor laser that forms a post that emits laser light by forming a groove in a part of a semiconductor film on a substrate and forms a pad formation region separated from the post, the electrode pad is: You may make it form on a pad formation area through a multilayer insulating film. In this case, the multilayer insulating film includes at least a first insulating film and a second insulating film, the first insulating film is formed on the second semiconductor multilayer reflective film, and the second insulating film is the first insulating film. Cover the insulating film and the side of the post. Alternatively, the first insulating film may cover the second semiconductor multilayer reflective film and the side surface of the post, and the second insulating film may cover the first insulating film under the electrode pad. Preferably, the multilayer insulating film comprises SiO ₂ film or SiN film, the film thickness of the SiO ₂ film or SiN film is at least 0.4 microns.

  The surface-emitting type semiconductor laser according to the present invention further includes at least a first conductivity type first semiconductor multilayer reflection film, an active region, and a second conductivity type second semiconductor multilayer reflection film on a substrate. A post is formed by removing the semiconductor film from the semiconductor multilayer reflective film 2 to a part of the first semiconductor multilayer reflective film, and a laser beam is emitted from the top of the post, and the second semiconductor multilayer reflective at the top of the post An electrode pad electrically connected to the film; and an insulating film formed between the first semiconductor multilayer reflective film at the bottom of the post and the electrode pad, and at least a first semiconductor multilayer reflective film at the bottom of the post The surface of is insulated.

  In the case of a surface emitting semiconductor laser that forms a post that emits laser light by forming a groove in a part of a semiconductor film on a substrate and forms a pad formation region separated from the post, the electrode pad is: On the pad forming region, the insulating layer may be formed on the second semiconductor multilayer reflective film that has been insulated.

  Preferably, the insulating process is performed by proton ion implantation. The substrate is a first conductivity type semiconductor substrate, for example, a GaAs substrate, and a lower electrode is formed on the back surface of the substrate. Furthermore, the first semiconductor multilayer reflective film includes an n-type AlGaAs layer, and the second semiconductor multilayer reflective film includes a p-type AlGaAs layer. Preferably, the second semiconductor multilayer reflective film may include a DBR in which a plurality of pairs of semiconductor layers having different refractive indexes are stacked, and a contact layer having a high impurity concentration may be included in the uppermost layer. Further, the second semiconductor multilayer reflective film may include a current confinement layer such as a second conductivity type AlAs. For the semiconductor multilayer reflective film, other compound semiconductors such as GaIn and GaN can be used in addition to AlGaAs.

  In the method of manufacturing the surface emitting semiconductor laser according to the present invention, at least the first conductive type first semiconductor multilayer reflective film, the active region, and the second conductive type second semiconductor multilayer reflective film are stacked on the substrate. Forming a post by removing the semiconductor film from the second semiconductor multilayer reflective film to a part of the first semiconductor multilayer reflective film, and the first semiconductor multilayer reflective exposed at the bottom of the post Forming a first insulating film on the film; forming a second insulating film on the first insulating film; and a second semiconductor multilayer reflective film on the top of the post on the second insulating film Forming electrode pads electrically connected to each other.

  Furthermore, in the method for manufacturing a surface emitting semiconductor laser according to the present invention, at least a first conductivity type first semiconductor multilayer reflection film, an active region, and a second conductivity type second semiconductor multilayer reflection film are formed on a substrate. Laminating, removing the semiconductor film from the second semiconductor multilayer reflective film to a part of the first semiconductor multilayer reflective film, forming a post, and the first semiconductor multilayer exposed at the bottom of the post Proton ion implantation is performed on the reflective film to insulate the surface of the first semiconductor multilayer reflective film, an insulating film is formed on the insulated first semiconductor multilayer reflective film, and a post is formed on the insulating film. Forming an electrode pad electrically connected to the top second semiconductor multilayer reflective film.

  According to the present invention, the withstand voltage can be improved by making the insulating film under the metal part where the electrode pad or other metal layer or the like is formed have a multi-layer structure, or by insulating the lower layer forming the insulating film. . As a result, it is possible to prevent excess current from flowing inside the device due to the abnormal current path during abnormal leakage current measurement or burn-in, thereby improving the yield of the surface emitting semiconductor laser and reducing the manufacturing cost.

  The best mode for carrying out the present invention will be described below with reference to the drawings.

  FIG. 1 is a plan view of a VCSEL according to a first embodiment of the present invention and a sectional view taken along line BB. The same components as those in FIG. 19 used in the conventional description are given the same reference numerals. In the VCSEL according to the first embodiment, the surface of the n-type lower DBR 12 exposed after the formation of the post P is subjected to insulation treatment by uniformly injecting proton ions to form an insulating region 100 on the surface of the DBR 12. ing. Preferably, after the semiconductor layer on the substrate is etched to form the post P, the post P is masked with a photoresist, and then the exposed n-type DBR 12 is uniformly subjected to proton implantation. Thereafter, the resist is peeled off and washed, and then the interlayer insulating film 22 is deposited.

n-type lower DBR12, which has a semiconductor layer of one pair having different refractive index stacking a plurality, for example, an AlGaAs layer of a pair having different content of Al laminating 30 pairs or more. For example, Si is used as the n-type impurity, and the thickness of the lower DBR 12 is about 4 microns. The lower layer of the lower DBR 12 is, for example, an n-type GaAs substrate containing Si impurities. The proton implantation into the lower DBR 12 preferably gives an acceleration voltage of 200 KeV or more so as to reach the GaAs substrate. At this time, the depth of the implantation is 4 microns or more.

  According to the first embodiment, the surface of the lower DBR 12 is insulated, the insulating region 100 is formed thereon, and the interlayer insulating film 22 is formed thereon. Even if holes or microcracks are generated or the interlayer insulating film 22 is contaminated, the insulating region 100 is interposed, so that the withstand voltage between the electrode pad 28 and the alignment electrode 34 and the lower DBR 12 is improved. Therefore, during leakage current measurement or burn-in using the electrode pad 28, it is possible to prevent the VCSEL from being destroyed due to excessive current flowing in the abnormal current path due to the low resistance. Similarly, the VCSEL is prevented from being destroyed when the probe pin is accidentally brought into contact with the alignment electrode 34. The alignment electrode 34 is not necessarily formed as an essential element.

  Next, a second embodiment of the present invention will be described with reference to FIG. In the VCSEL according to the second embodiment, an insulating protective film 110 is formed on the surface of the n-type lower DBR 12 exposed when the post P is formed, and an interlayer insulating film 22 is formed on the insulating protective film 110. Electrode pads 28 and alignment electrodes 34 are formed on the interlayer insulating film 22.

  Preferably, after the semiconductor layer on the substrate is etched to form the post P, the post P is masked with a photoresist, and an Si oxide film or a single layer of Si nitride film is formed on the exposed n-type lower DBR 12. An insulating protective film 110 composed of these multilayers is deposited. Thereafter, the insulating protective film deposited on the post is peeled off together with the resist by peeling off the resist. The thickness of the insulating protective film 110 when deposited is preferably 0.4 microns or more. This is because pinholes are less likely to occur at this thickness.

  According to the second embodiment, since the insulating film between the electrode pad 28 and the alignment electrode 34 and the n-type lower DBR 112 has a multi-layer structure, a pinhole is temporarily formed in the interlayer insulating film 22 and the insulating protective film 110. Even if microcracks occur or they are contaminated, one of the films complements the other film, so that the withstand voltage between the electrode pad 28 and the lower DBR 12 is improved. For this reason, at the time of leak current measurement or burn-in using the electrode pad 28, it is possible to prevent the VCSEL from being destroyed due to excessive current flowing through an abnormal current path due to low resistance. Similarly, the VCSEL is prevented from being destroyed when the probe pin is accidentally brought into contact with the alignment electrode 34.

Next, a third embodiment of the present invention will be described with reference to FIG. The third embodiment is a modification of the VCSEL of the second embodiment. That is, in the second embodiment, the insulating protective film 110 is formed on the entire surface of the lower DBR 12 except for the post P, and the interlayer insulating film 22 is formed so as to cover the insulating protective film 110. In the example, an interlayer insulating film 22 is formed, and an insulating protective film 110 a is formed on the interlayer insulating film 22. The insulating protective film 110a is formed only in the region where the electrode pad 28 and the alignment electrode 34 are formed.

  Next, a fourth embodiment of the present invention will be described with reference to FIG. The fourth embodiment is a modification of the VCSEL of the first embodiment. That is, in the first embodiment, the entire surface of the lower DBR 12 other than the post P is uniformly insulated, but in the fourth embodiment, in the region where the electrode pad 28 and the alignment electrode 34 are formed. Only the surface of the lower DBR 12 is subjected to insulation treatment to form an insulation region 100.

  Next, a fifth embodiment of the present invention will be described with reference to FIG. In the fifth embodiment, a lower DBR 12, an active layer 14, a current confinement layer 18, an upper DBR 20 and a contact layer 22 are stacked on an n-type GaAs substrate, and then reach from the contact layer 22 to a part of the lower DBR 12. An annular or ring-shaped trench 120 having a depth is formed. The trench 120 forms a cylindrical post P that is a light emitting part that emits laser light, and also forms a pad forming region 130 that is separated from the post P. Simultaneously with the formation of the trench 120, the outer edge groove 140 along the outer edge of the pad forming region 130 may be formed. The outer edge groove 140 can be a scribe area when each VCSEL is cut out from the wafer.

  On the surface of the upper DBR 18 in the pad forming region 130, an insulating region 150 is formed which is insulated by proton ion implantation. An interlayer insulating film 22 is formed on the entire surface including the upper DBR 18 and the post P that have been insulated. The p-side electrode 26 is ohmically connected to the contact layer 20 through the contact hole at the top of the post, and is further connected to the electrode pad 28 through the lead wiring 30.

  Preferably, after trench 120 including post P is masked with a photoresist, insulation treatment is performed from the exposed surface of p-type DBR 18 (including contact layer 20) by proton implantation to form insulating region 150 on the surface. . The p-type upper DBR 18 is formed by stacking a plurality of pairs of semiconductor layers having different refractive indexes. For example, 30 or more pairs of AlGaAs layers having different Al contents are stacked. For example, carbon (C) is used as a p-type impurity, and the thickness of the upper DBR 18 is about 3 microns. The uppermost layer of the upper DBR 12 is a p-type GaAs contact layer 20. The proton injection into the upper DBR 18 is preferably an acceleration voltage of 150 KeV or higher. At this time, the depth of proton implantation is 1 micron or more.

  According to the fifth embodiment, even if the interlayer insulating film 22 has a defect such as a pinhole or a crack, an abnormal current path due to a reduction in resistance due to the insulating region 150 can be suppressed, and the electrode pad 28 or positioning can be performed. The withstand voltage between the electrode 34 and the p-type upper DBR 18 can be improved.

  Next, a sixth embodiment of the present invention will be described with reference to FIG. In the sixth embodiment, an insulating protective film 160 is formed on the upper DBR 18 (contact layer 20) in the pad forming region 130, and an interlayer insulating film 22 is formed so as to cover the insulating protective film 160. Preferably, the trench forming portion including the post P is masked with a photoresist, and a Si oxide film or a Si nitride film is deposited on the exposed p-type upper DBR 18 as a single layer or a multilayer, and then on the photoresist. The insulating protective film is peeled off together with the resist. The thickness of the insulating protective film when deposited is preferably 0.4 microns or more. Further, the upper portion of the post may be masked with a photoresist, a second insulating protective film may be deposited, and the insulating protective film on the resist and the resist may be removed together with the resist as described above.

  According to the sixth embodiment, since the insulation between the pad electrode 28 and the positioning electrode 34 and the upper DBR 18 is performed by the interlayer insulating film 22 and the insulating protective film 160, the withstand voltage can be improved.

Next, a manufacturing method of the VCSEL of the first embodiment will be described with reference to FIGS. First, as shown in FIG. 7A, an n-type GaAs substrate 10 having an Si carrier concentration of 1 × 10 ¹⁸ cm ⁻³ and a film thickness of about 0.2 μm is formed on the n-type GaAs substrate 10 by metal organic chemical vapor deposition (MOCVD). A type GaAs buffer layer 11 is laminated, and Al _0.9 Ga _0.1 As and Al _0.12 Ga _0.88 As are alternately laminated for 40.5 periods so that each film thickness becomes 1/4 of the wavelength in the medium. A lower n-type DBR 12 having a carrier concentration of 1 × 10 ¹⁸ cm ⁻³ and a total film thickness of about 4 μm, an undoped lower Al _0.6 Ga _0.4 As spacer layer and an undoped quantum well active layer (thickness 70 nm GaAs quantum well layer 3 layers) active region 14 where the film thickness made of a thickness 50nmAl _0.3 Ga _0.7 is composed of a as barrier layer 4 layer) and an undoped upper Al _0.6 Ga _0.4 as spacer layer is medium wavelength and, p-type AlAs layer 16 of On top of that, Al _0.9 Ga _0.1 As and Al _0.12 Ga _0.88 As are alternately stacked for 30 periods such that the film thickness is 1/4 of the wavelength in the medium, and the carbon carrier concentration is 1 × 10 ¹⁸ cm ^−3. Then, an upper p-type DBR 18 having a total thickness of about 3 μm and a p-type GaAs contact layer 20 having a thickness of about 20 nm and a carrier concentration of 1 × 10 ¹⁹ cm ⁻³ are sequentially stacked. In order to lower the electrical resistance of the DBR, a region having a film thickness of about 20 nm in which the Al composition is gradually changed from 90% to 30% is provided at the interface between Al _0.9 Ga _0.1 As and Al _0.12 Ga _0.88 As. It is also possible.

  Next, as shown in FIG. 7B, a resist mask R is formed on the crystal growth layer by a photolithography process, and etching is performed to the middle of the lower DBR 12 by reactive ion etching using boron trichloride as an etching gas. As shown in FIG. 7C, a columnar post P is formed. The post P has a diameter of about 10 to 30 μm. Needless to say, a prismatic post other than a cylinder may be used.

Next, as shown in FIG. 7D, the substrate is exposed to a steam atmosphere of, for example, 340 ° C. for a certain period of time to perform an oxidation treatment. Since the AlAs layer constituting the current confinement layer 16 has a significantly faster oxidation rate than the Al _0.9 Ga _0.1 As layer and Al _0.12 Ga _0.88 As layer which also constitute a part thereof, the post shape is reflected from the side surface of the post P. The oxidized region 16a is formed, and the non-oxidized region (conductive region) remaining without being oxidized becomes a current injection region or a conductive region.

  Next, as shown in FIG. 8E, after removing the resist R, a resist R1 surrounding the post P is formed. Next, as shown in FIG. 8F, proton ions are implanted from the surface of the n-type lower DBR 12 exposed at the bottom of the post P using the resist R1 as a mask. Preferably, proton injection into the lower DBR 12 is made to reach the GaAs substrate, and an acceleration voltage of 200 KeV or higher is applied. At this time, the depth of the implantation is preferably 4 microns or more. Thus, the insulating region 100 is formed on the surface of the n-type lower DBR 12.

  Next, after removing the resist R1, as shown in FIG. 8G, an interlayer insulating film 22 made of SiN is deposited on the entire surface of the substrate including the post P using a plasma CVD apparatus. Thereafter, as shown in FIG. 8H, the interlayer insulating film 122 is etched using a photolithography process to form a circular contact hole at the top of the post P, and the contact layer 20 is exposed.

  Thereafter, Au is deposited as a p-side electrode material at 100 to 1000 nm, preferably 600 nm, and the p-side electrode 26, the electrode pad 28, the lead-out wiring 30, and the electrode 34 for alignment are formed by a lift-off process. In addition, an opening 26 a for emitting laser light is formed in the center of the p-side electrode 26.

  Then, Au / Ge is vapor-deposited as the n-electrode 32 on the back surface of the substrate. Thereafter, annealing is performed at an annealing temperature of 250 ° C. to 500 ° C., desirably 300 ° C. to 400 ° C. for 10 minutes. In this way, the VCSEL of the first embodiment in which the withstand voltage is improved by proton implantation is obtained.

  Next, a method for manufacturing the VCSEL of the second embodiment will be described. In the VCSEL of the second embodiment, the steps shown in FIGS. 7A to 8E are the same as those of the first embodiment. Next, in the second embodiment, as shown in FIG. 9I, an insulating protective film 110 is formed on the entire surface of the substrate. Next, as shown in FIG. 9J, when the resist R1 is removed, the insulating protective film 110 on the resist R1 is removed together. As a result, the insulating protective film 110 is patterned on the lower DBR 12 exposed at the bottom of the post.

  Next, as shown in FIG. 9 (k), an interlayer insulating film 22 is formed, and as shown in FIG. 9 (l), the interlayer insulating film 22 is patterned. As in the first embodiment, The p-side upper electrode 26, the electrode pad 28, the lead-out wiring 30, and the electrode 34 for alignment are formed.

  When the VCSELs of the third and fourth embodiments are manufactured, the shape of the resist mask when the proton implantation or the insulating protective film is formed may be changed.

  Next, a method for manufacturing a VCSEL according to the fifth embodiment will be described. As in the first embodiment, a semiconductor layer is stacked on a GaAs substrate, a resist mask R is formed as shown in FIG. 10A, and the bottom is formed by reactive ion etching using boron trichloride as an etching gas. Etching is performed halfway through the DBR 12 to form an annular trench 120 as shown in FIG. Thus, a column or prism post P having a diameter of about 10 to 30 μm and a pad formation region 130 are formed around the post P.

  Next, as shown in FIG. 10C, AlAs constituting the current confinement layer 16 is oxidized from the side surface of the post P, and an oxidized region 16a is formed. Next, as shown in FIG. 11D, after removing the resist R, a resist R1 surrounding the post P is formed. Next, as shown in FIG. 11E, proton ions are implanted into the p-type upper DBR from the surface of the p-type contact layer 20 exposed in the pad formation region 130 using the resist R1 as a mask. Preferably, an acceleration voltage of 150 KeV or higher is applied. At this time, the depth of the implantation is preferably 3 microns or more. Thus, the insulating region 150 is formed from the contact layer 20 to a part of the upper DBR 18.

  Next, after removing the resist R1, as shown in FIG. 11F, an interlayer insulating film 22 made of SiN is deposited on the entire surface of the substrate including the post P using a plasma CVD apparatus. The subsequent steps are the same as in the first embodiment.

  FIG. 12 is a schematic cross-sectional view showing an example of a package (module) of a semiconductor laser device on which a VCSEL chip is mounted. In the package 300, a chip 310 on which a VCSEL array is formed is fixed on a submount 320 on a metal stem 330. The conductive leads 340 and 342 are inserted into through holes (not shown) of the stem 330, and one lead 340 is electrically connected to the n-side lower electrode 32 formed on the back surface of the chip 310, The other lead 342 is electrically connected to the p-side electrode 26 (electrode pad 28) formed on the upper surface of the chip 310 via a bonding wire or the like.

  A ball lens 360 is fixed in the exit window 352 of the cap 350. The optical axis of the ball lens 360 is positioned so as to coincide with the approximate center of the opening 132 of the upper electrode 130. Further, the distance between the chip 310 and the ball lens 360 is adjusted so that the ball lens 360 is included within the radiation angle θ of the laser beam from the chip 310. When a forward voltage is applied between the leads 340 and 342, laser light is emitted from the chip 310 and output to the outside through the ball lens 360. Note that a light receiving element for monitoring the light emission state of the VCSEL may be included in the cap.

  FIG. 13 is a diagram showing the configuration of still another package, and is preferably used in a spatial transmission system described later. In the package 302 shown in the drawing, a flat glass 362 is fixed in an emission window 352 at the center of the cap 350 instead of using the ball lens 360. The center of the flat glass 362 is positioned so as to coincide with the optical axis of the chip 310. The distance between the chip 310 and the flat glass 362 is adjusted so that the opening diameter of the flat glass 362 is not less than the radiation angle θ of the laser beam from the chip 310.

  FIG. 14 is a cross-sectional view showing a configuration when the package or module shown in FIG. 12 is applied to an optical transmitter. The optical transmission device 400 includes a cylindrical housing 410 fixed to the stem 330, a sleeve 420 integrally formed on an end surface of the housing 410, a ferrule 430 held in the opening 422 of the sleeve 420, a ferrule And an optical fiber 440 held by 430.

  An end of the housing 410 is fixed to a flange 332 formed in the circumferential direction of the stem 330. The ferrule 430 is accurately positioned in the opening 422 of the sleeve 420 and the optical axis of the optical fiber 440 is aligned with the optical axis of the ball lens 360. The core wire of the optical fiber 440 is held in the through hole 432 of the ferrule 430.

  The laser light emitted from the surface of the chip 310 is collected by the ball lens 360, and the collected light is incident on the core wire of the optical fiber 440 and transmitted. Although the ball lens 360 is used in the above example, other lenses such as a biconvex lens and a plano-convex lens can be used. Further, the optical transmission device 400 may include a drive circuit for applying an electrical signal to the leads 340 and 342. Furthermore, the optical transmission device 400 may include a reception function for receiving an optical signal via the optical fiber 440.

  FIG. 15 is a diagram showing a configuration when the package shown in FIG. 13 is used in a spatial transmission system. The spatial transmission system 500 includes a package 300, a condenser lens 510, a diffusion plate 520, and a reflection mirror 530. In the spatial transmission system 500, instead of using the ball lens 360 used in the package 300, a condensing lens 510 is used. The light condensed by the condenser lens 510 is reflected by the diffusion plate 520 through the opening 532 of the reflection mirror 530, and the reflected light is reflected toward the reflection mirror 530. The reflection mirror 530 reflects the reflected light in a predetermined direction and performs optical transmission. In the case of a spatial transmission light source, a multi-spot type VCSEL may be used to obtain a high output.

  FIG. 16 is a diagram illustrating a configuration example of an optical transmission system using a VCSEL as a light source. The optical transmission system 600 receives a light source 610 including a chip 310 on which a VCSEL is formed, an optical system 620 that collects laser light emitted from the light source 610, and the laser light output from the optical system 620. A light receiving unit 630 and a control unit 640 that controls driving of the light source 610 are included. The control unit 640 supplies a drive pulse signal for driving the VCSEL to the light source 610. Light emitted from the light source 610 is transmitted to the light receiving unit 630 via an optical system 620 by an optical fiber, a reflection mirror for spatial transmission, or the like. The light receiving unit 630 detects the received light with a photodetector or the like. The light receiving unit 630 can control the operation of the control unit 640 (for example, the start timing of optical transmission) by the control signal 650.

  Next, the configuration of an optical transmission device used in the optical transmission system will be described. FIG. 17 shows an external configuration of the optical transmission apparatus. The optical transmission device 700 includes a case 710, an optical signal transmission / reception connector joint 720, a light emitting / receiving element 730, an electric signal cable joint 740, a power input unit 750, an LED 760 indicating that an operation is in progress, an LED 770 indicating occurrence of an abnormality, and a DVI. A connector 780 and a transmission circuit board / reception circuit board 790 are provided.

  A video transmission system using the optical transmission apparatus 700 is shown in FIG. The video transmission system 800 includes a video signal generation device 810, an image display device 820, a DVI electric cable 830, a transmission module 840, a reception module 850, a video signal transmission optical signal connector 860, an optical fiber 870, and a control signal cable connector 880. , A power adapter 890, and an electric cable 900 for DVI. In order to transmit the video signal generated by the video signal generator 810 to the image display device 820 such as a liquid crystal display, the optical transmission device shown in FIG. 17 is used.

  The surface emitting semiconductor laser according to the present invention can be used in the fields of optical information processing and optical high-speed data communication.

It is the top view of VCSEL which concerns on 1st Example of this invention, and its BB sectional drawing. It is the top view of VCSEL which concerns on 2nd Example of this invention, and its CC sectional view taken on the line. It is the top view of VCSEL which concerns on the 3rd Example of this invention, and its DD sectional view. It is the top view of VCSEL which concerns on the 4th Example of this invention, and its EE sectional view taken on the line. It is the top view of VCSEL which concerns on the 5th Example of this invention, and its FF sectional view taken on the line. It is the top view of VCSEL which concerns on the 6th Example of this invention, and its GG sectional view taken on the line. It is process sectional drawing explaining the manufacturing method of VCSEL which concerns on the 1st Example of this invention. It is process sectional drawing explaining the manufacturing method of VCSEL which concerns on the 1st Example of this invention. It is process sectional drawing explaining the manufacturing method of VCSEL based on 2nd Example of this invention. It is process sectional drawing explaining the manufacturing method of VCSEL which concerns on the 5th Example of this invention. It is process sectional drawing explaining the manufacturing method of VCSEL which concerns on the 5th Example of this invention. It is a schematic sectional drawing which shows the structure of the package which mounted the semiconductor chip in which VCSEL was formed. It is a schematic sectional drawing which shows the structure of another package. It is a schematic sectional drawing which shows the structure of the optical transmitter using the package shown in FIG. It is a figure which shows a structure when the package shown in FIG. 13 is used for a spatial transmission system. It is a block diagram which shows the structure of an optical transmission system. It is a figure which shows the external appearance structure of an optical transmission apparatus. It is a figure which shows the video transmission system using the optical transmission apparatus of FIG. It is sectional drawing which shows the conventional VCSEL.

Explanation of symbols

10: GaAs semiconductor substrate 12: Lower lower DBR
14: active layer 16: current confinement layer 18: upper DBR 20: contact layer 22: interlayer insulating film 24: contact hole 26: p-side electrode 28: electrode pad 30: lead-out wiring 32: n-side electrode 34: alignment electrode 100: Insulating region 110: Insulating protective film 120: Trench 130: Pad forming region 140: Outer edge groove 150: Insulating region P: Post

Claims (14)

The substrate includes at least a first semiconductor multilayer reflective film of a first conductivity type, an active region, and a second semiconductor multilayer reflective film of a second conductivity type, and the first semiconductor multilayer reflective film is formed from the second semiconductor multilayer reflective film. A surface emitting semiconductor laser in which a post is formed by removing a semiconductor film reaching a part of a reflective film, and laser light is emitted from the top of the post.
An electrode pad electrically connected to the second semiconductor multilayer reflective film at the top of the post and formed on the bottom of the post away from the top of the post ;
An insulating film formed between the first semiconductor multilayer reflective film on the bottom of the post and the electrode pad , and covering a part of the side of the post and the top of the post, and a lower first layer on which the insulating film is formed A surface-emitting type semiconductor laser in which the surface of the semiconductor multilayer reflective film is insulated. The surface emitting semiconductor laser according to claim 1, wherein the insulation treatment is performed by proton ion implantation. 3. The surface emitting semiconductor laser according to claim 2, wherein the proton ions are implanted into a first semiconductor multilayer reflecting mirror that is selectively exposed by masking. 4. The surface emitting semiconductor laser according to claim 2, wherein the proton ions are implanted with energy reaching the substrate. The substrate is a semiconductor substrate of a first conductivity type, the lower electrode on the back surface of the semiconductor substrate is formed, a surface emitting semiconductor laser according to 4 any one claims 1. An upper electrode electrically connected to the second semiconductor multilayer reflective film and formed with a laser beam exit is formed on the top of the post, and the upper electrode and the electrode pad are electrically connected. are surface emitting semiconductor laser according to 5 any one claims 1. The first semiconductor multilayer reflection film includes a n-type AlGaAs layer, the second semiconductor multilayer reflection film includes a p-type AlGaAs layer, a surface-emitting type semiconductor according to 6 any one claims 1 laser. Module mounted with a surface-emitting type semiconductor laser and the optical member according to any one claims 1 to 7. An optical transmission device comprising: the module according to claim 8; and a transmission unit configured to transmit a laser beam emitted from the module via an optical medium. An optical space transmission apparatus comprising: the module according to claim 8; and a transmission unit that spatially transmits light emitted from the module. An optical transmission system comprising: the module according to claim 8; and a transmission unit configured to transmit laser light emitted from the module. An optical space transmission system comprising: the module according to claim 8; and a transmission unit that spatially transmits light emitted from the module. Laminating at least a first semiconductor multilayer reflective film of a first conductivity type, an active region, and a second semiconductor multilayer reflective film of a second conductivity type on a substrate;
Forming a post by removing a semiconductor film from the second semiconductor multilayer reflective film to a part of the first semiconductor multilayer reflective film;
Injecting proton ions into the first semiconductor multilayer reflective film exposed at the bottom of the post to insulate the surface of the first semiconductor multilayer reflective film;
Forming an insulating film on the entire surface of the substrate including the insulating first semiconductor multilayer reflective film and the post; and
Etching the insulating film to form a contact hole at the top of the post;
An upper electrode electrically connected to the second semiconductor multilayer film reflecting mirror through the contract hole, a lead wiring extending from the top electrode to the bottom of the post, and the insulation connected to the lead wiring and at the bottom of the post Forming an electrode pad formed on the membrane;
Manufacturing method of surface emitting semiconductor laser having The manufacturing method according to claim 13 , further comprising the step of oxidizing a current confinement layer included in the first or second semiconductor multilayer reflective film in the post from a side surface of the post after forming the post. .

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