JP4609508B2 - Surface emitting semiconductor laser array device with improved reliability by stress control of interlayer insulating film - Google Patents

Description

  The present invention relates to a surface emitting semiconductor array element, and more particularly to a stacked structure of surface emitting semiconductor laser array elements.

  A surface-emitting semiconductor laser (Vertical-Cavity Surface-Emitting Laser diode: hereinafter referred to as VCSEL) element is a laser diode that emits light from the surface of a semiconductor substrate, and is driven in comparison with an edge-emitting laser diode. Therefore, it has excellent characteristics such as low current value (low threshold current), characteristic inspection at wafer level (non-destructive measurement), and easy two-dimensional array. For this reason, it is used as a light source of an optical information processing device, an optical communication element, or a data storage device using light.

FIG. 17 schematically shows the structure of a conventional selective oxidation VCSEL element disclosed in Patent Document 1. An n-type lower DBR layer 3 formed on the substrate 1, a p-type upper DBR layer 9, an active region 7 disposed between the DBR layers, and a selectively oxidized oxide region 8b. And a current confinement layer 8. The mesa structure formed on the substrate includes a contact layer 10, an upper DBR layer 9, and a current confinement layer 8, and an edge portion, a side surface, and a mesa bottom portion of the mesa structure are covered with an interlayer insulating film 13. Patent Document 1 discloses an oxidized VCSEL element in which the internal stress of the interlayer insulating film 13 is set to 1.5 × 10 ⁹ (dyne / cm ² ) or less to prevent the mesa structure from falling off and to extend the life of the element. Yes.

  U.S. Pat. No. 6,057,059 forms an oxidation cavity that partially penetrates the VCSEL structure and oxidizes the layers in this structure. Further, a first passivation layer is formed on the surface of the oxidation cavity, and a second passivation layer is formed thereon. The first passivation layer is formed of silicon nitride (SiN), and the second passivation layer is formed of silicon oxynitride (SiON). Since the pinhole that may exist in one of the passivation layers is covered with the other passivation layer, the path for moisture remaining in the manufacturing process is cut off, and the reliability of the oxidized VCSEL element is improved.

  In Patent Document 3, a first insulating film made of an inorganic material, a resin layer filling a peripheral portion, and a second insulating film made of an inorganic material are formed on the side surface of the mesa structure. An upper contact electrode having an opening is formed on the upper surface of the mesa structure. As a result, oxidation and alteration of the resin layer are suppressed during manufacturing, and a highly reliable VCSEL element that suppresses oxidation and alteration of the resin layer sandwiched between the insulating films by embedding the mesa structure without gaps can be obtained. .

JP 2004-200211 A JP 2004-241777 A JP 2006-86498 A

  Incidentally, one of the problems of the selective oxidation type VCSEL device is a problem of so-called sudden death. This is because dislocations (point defects) occur in the laminated film due to the composition change of the laminated material due to oxidation, and the heat generated accompanying laser oscillation promotes and propagates the movement of dislocations, which suddenly dies through the active layer. It is thought to induce (element degradation). However, in subsequent research, dislocations are not caused simply by the oxidation reaction, but internal stress (stress) generated between the insulating layers formed in the vicinity of the oxidized region is one of the factors. I understand.

  Since the semiconductor layer serving as the base of the VCSEL and the interlayer insulating film composed of the dielectric film have different thermal expansion coefficients, the occurrence of stress when the temperature rises is unavoidable. This phenomenon is particularly remarkable in a long array element (having a plurality of light emitting points) that is likely to be stressed due to warping of the substrate, and a solution for this phenomenon is awaited.

  It is an object of the present invention to provide a surface emitting semiconductor laser array element and a method for manufacturing the same, which suppresses the lifetime deterioration due to stress by controlling the stress generated in the interlayer insulating film and improves the reliability. To do.

  A surface emitting semiconductor laser array device according to the present invention includes a substrate extending in a longitudinal direction on which at least a first multilayer reflective film, an active layer, and a second multilayer reflective film are formed, and the first multilayer A plurality of mesa portions formed on the substrate by selectively removing at least a part of the film reflection film, the active layer, and the second multilayer film reflection film, and the first multilayer film reflection film or A selective oxidation region formed on at least one of the second multilayer reflective film, an interlayer insulating film that covers at least the side and bottom of the mesa portion, and a surface protective film that covers the interlayer insulating film, A plurality of grooves for removing at least a part of the surface protective film are formed in the surface protective film along the longitudinal direction of the substrate.

  The trench can be formed up to the surface protective film and the interlayer insulating film immediately below it. The groove may include a slit formed in a short direction of the substrate. Preferably, when the number of mesa portions arranged in a line is n (n is a natural number of 2 or more), the number of grooves is at least n-1. For example, when eight mesa parts (light emitting parts) are arranged in a line, at least seven grooves are formed. Preferably, the interlayer insulating film is a single inorganic insulating film or a laminated film including a plurality of inorganic insulating films made of different materials. Preferably, the surface protective film is a film quality insulating film having a normal stress opposite to the normal stress of the interlayer insulating film. Preferably, the interlayer insulating film is made of an inorganic insulating film containing at least one layer of aluminum. Further, the interlayer insulating film may be a laminated film including an inorganic insulating film containing aluminum and an inorganic insulating film containing silicon. Preferably, the first and second multilayer reflective films are III-V group semiconductor layers containing Al, and the selective oxidation region is a semiconductor layer containing Al selectively oxidized from the side surface of the mesa portion. . More preferably, the groove may be filled with an insulating material.

  According to the present invention, there is provided a method of manufacturing a surface emitting semiconductor laser array element having a plurality of mesa portions formed on a substrate extending in a longitudinal direction, at least a first multilayer reflective film, an active layer, and a second layer. Forming a plurality of mesa portions on the substrate, etching the at least part of the first multilayer film reflection film, the active layer, and the second multilayer film reflection film; Forming an oxidized region selectively oxidized from a side surface of the plurality of mesa portions; forming an interlayer insulating film on the substrate so as to cover at least side portions and bottom portions of the plurality of mesa portions; and Forming a surface protective film on the interlayer insulating film; and forming a plurality of grooves in the surface protective film along a longitudinal direction of the substrate to remove at least a part of the surface protective film.

  According to the present invention, the internal stress generated between the oxide region provided in the vicinity of the active layer and the interlayer insulating film has a structure in which the surface protective film formed so as to cover the interlayer insulating film has no groove. In comparison, the growth of dislocations in the laminated material can be suppressed, and a highly reliable semiconductor laser array element can be obtained.

  Also, the temperature rise in the vicinity of the active layer due to heat generation is due to the heat generated by the active layer compared to the structure that does not use an insulating film mainly made of aluminum with high heat dissipation in the interlayer insulating film covering the side surface of the mesa. It can be efficiently discharged to the outside.

  Hereinafter, embodiments of the selective oxidation type VCSEL array device according to the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a schematic plan view of an array element of a selective oxidation VCSEL according to an embodiment of the present invention. The array element 20 illustrated in FIG. 1 has a plurality of mesa portions 24 (light emitting portions) arranged in a straight line on an elongated rectangular substrate 22. Eight mesa portions 24 are formed on the substrate at substantially constant intervals. A plurality of p-side electrodes 26 and a plurality of n-side electrodes 28 are formed on the substrate corresponding to the mesa portions 24. The p-side electrode 26 is electrically connected to the p-type contact layer at the top of the mesa portion 24, and the n-side electrode 28 is electrically connected to the n-type semiconductor layer of the mesa portion 24. By applying a forward bias current to the p-side electrode 26 and the n-side electrode 28, laser light is emitted from the top of the corresponding mesa portion 24. The example shown in FIG. 1 shows a plurality of p-side electrodes 26 and a plurality of n-side electrodes 28. However, when all the mesa portions 24 are driven simultaneously, the plurality of p-side electrodes 26 are combined into one electrode. A plurality of n-side electrodes 28 may be shared by one electrode.

  A surface protective film 32 for protecting the mesa portion 24 is formed on the surface of the substrate. In this embodiment, a separation groove for separating the mesa portion from the mesa portion is formed in the surface protective film 32. 30 is formed. Preferably, when n (n is a natural number of 2 or more) mesa portions 24 are linearly arranged on the substrate, the separation groove 30 is at least n−1 so as to partition between the mesa portions 24. Individually formed. However, the separation groove formed between one mesa portion and a mesa portion adjacent thereto may be single or plural. In the example of FIG. 1, seven separation grooves 30 are formed for eight mesa portions arranged in a straight line.

  As shown in FIG. 1, the separation groove 30 may extend from one end of the surface protective film 32 to the other end to completely divide the surface protective film 32, or partially divide the surface protective film 32. You may do. The shape of the separation groove 30 may be a straight line, but may be a curved line 31a as shown in FIG. 2, a bent part 31b, or a part 31c including an orthogonal part. In the example of FIG. 1, the separation grooves 30 extend in a straight line in an oblique direction so as to intersect with each other in parallel and at a certain angle with respect to the longitudinal direction of the substrate, thereby completely dividing the surface protective film 32. ing.

  FIG. 3 shows a schematic plan view of the array element when a plurality of mesa portions (light emitting portions) are arranged two-dimensionally. The mesa portions 24 are arranged in 5 rows × 2 columns along the longitudinal direction of the rectangular substrate 22. In order to separate the mesa portions, four separation grooves 30 are formed in the row direction and one in the column direction. Preferably, when the arrangement of the mesa portions 24 is n rows × m columns (n and m are natural numbers), the row direction separation grooves are at least n−1, and the column direction separation grooves are at least m−1. It is.

  Next, a detailed configuration of the VCSEL array element will be described. 4A is a cross-sectional view taken along line AA of the VCSEL shown in FIG. 1, and FIG. 4B is a cross-sectional view taken along line BB of the VCSEL shown in FIG. For convenience, the p-side electrode and the n-side electrode are omitted in FIG. 4B. Further, this cross-sectional view does not necessarily match the scale of the plan view shown in FIG.

On a semi-insulating semiconductor substrate 22, an n-type lower multilayer reflector (hereinafter referred to as a lower DBR) 40, a spacer layer 42 (42a closer to the substrate and 42b farther), a quantum well active layer 44, a p-type The semiconductor thin films are laminated in the order of the oxidation control layer 46 and the p-type upper multilayer reflector (hereinafter referred to as upper DBR) 48. The lower DBR 40 and the upper DBR 48 are distributed Bragg reflectors and form a vertical resonator structure on the substrate. Since the spacer layer 42 is stacked in the vertical direction of the substrate surface with the quantum well active layer 44 interposed therebetween, the side closer to the substrate is represented by 42a and the side far from the substrate is represented by 42b. A p-type contact layer 50 is formed on the upper DBR 48, and an annular contact electrode 52 is formed on the contact layer 50. The opening 52a of the contact electrode 52 serves as a laser light emission window.

  By etching the semiconductor thin film from the upper DBR 48 to the spacer layer 42 or the lower DBR 40, a cylindrical (columnar) mesa portion (or post) 24 is formed on the substrate 22. The peripheral edge, the side wall, and the bottom of the top of the mesa portion 24 are covered and protected by the interlayer insulating film 54. At the top of the mesa portion 24, a circular contact hole 54 a for exposing a part of the contact electrode 52 is formed in the interlayer insulating film 54.

  Further, a surface protective film 32 is formed on the interlayer insulating film 54 so as to cover the entire surface of the substrate. At the top of the mesa portion 24, a circular contact hole 32 a is formed in the surface protection film 32 to expose the contact hole 54 a of the interlayer insulating film 54. The contact hole 32a is somewhat larger in diameter than the contact hole 54a. Further, as shown in FIG. 1, the surface protection film 32 is formed with an isolation groove 30 for separating the mesa portion 24 from the mesa portion 24 by etching. The shape, width, etc. of the isolation trench 30 are not particularly limited, but the surface of the interlayer insulating film 54 is exposed by the isolation trench 30.

As shown in FIG. 4A, the p-side electrode 26 is connected to the contact electrode 52 exposed by the contact hole 32a of the surface protective film 32 and the contact hole 54a of the interlayer insulating film 54 at the top of the mesa portion 24. The n-side electrode 28 is electrically connected to the n-type lower DBR 40 exposed at the bottom of the mesa portion 24 by contact holes 54b and 32b formed in the interlayer insulating film 54 and the surface protection film 32, respectively.

  According to the VCSEL array element according to the present embodiment, the separation groove 30 for separating the mesa portions is formed in the surface protective film 32. For this reason, the propagation of the stress mediated by the surface protective film 32 to the inside of the element is interrupted, thereby reducing the stress generated between the oxidized region 46a of the oxidation control layer 46 and the interlayer insulating film 54. The deterioration of the long-term reliability of the VCSEL array element due to the above is suppressed. In particular, when the substrate is warped due to a difference in thermal expansion coefficient between the substrate and the semiconductor thin film laminated thereon, stress propagation through the surface protective film 32 easily occurs. This suppresses the propagation of stress.

  FIG. 5 is a diagram for explaining the relationship between the normal stresses of the interlayer insulating film and the surface protective film. When the normal stress f1 contracting in the normal direction of the mesa portion 24 as shown in the figure is generated in the interlayer insulating film 54 due to the strain stress caused by the oxidation region 46a of the oxidation control layer 46 near the active layer 44, surface protection The film 32 preferably has a film quality having a normal stress f2 opposite to the normal stress f1. On the contrary, if the normal stress f1 of the interlayer insulating film 54 extends, the surface protective film 32 desirably has a film quality in a direction in which the normal stress f2 contracts. A good combination of the material, film thickness, etc. of the interlayer insulating film 54 and the surface protective film 32 is selected so as to have such a relationship. Thereby, even if the stress from the interlayer insulating film 54 propagates to the surface protective film 32, all or a part of the normal stress f <b> 1 of the interlayer insulating film 54 is canceled and the stress is propagated to each layer in the mesa portion 24. Can be reduced.

Next, a manufacturing method of the VCSEL array element will be described with reference to FIGS. 6 and 7 correspond to the portion shown in FIG. 4B. As shown in FIG. 6A, an n-type lower multilayer reflector (DBR) 40 formed on a GaAs substrate 12 has, for example, Al _0.9 Ga _0.1 As and Al _0.3 Ga _0.7 As alternately in a plurality of periods (pairs). ) And the thickness of each layer is λ / 4n _r (where λ is the oscillation wavelength and n _r is the refractive index of the medium). Spacer layer 42 (4 2a, 4 2b) is, for example, an undoped Al _0.5 Ga _0.5 As, a quantum well active layer 44 is, for example, Al _0.2 Ga _0.8 As barrier layers of GaAs quantum well layer and undoped undoped Composed. The total thickness of the spacer layer 32 and the quantum well active layer 44 is λ / n _r . The p-type upper multilayer reflector (DBR) 48 includes, for example, Al _0.9 Ga _0.1 As and Al _0.3 Ga _0.7 As stacked alternately in a plurality of pairs, and the thickness of each layer is the same as that of the lower multilayer reflector 40. 1/4 of the inner wavelength. A p-type AlAs layer (oxidation control layer) 46 is laminated below the upper multilayer reflector 48, and a p-type GaAs contact layer 50 having a higher carrier concentration is laminated on the opposite upper layer, for example. Part of the reflector.

  Subsequently, as shown in FIG. 6B, an annular contact electrode 52 is formed on the top of the contact layer 50. The contact electrode 52 has a two-layer structure of Ti / Au, for example, and has a ring shape because it serves as an opening through which laser light is emitted.

Next, a predetermined mask pattern by photolithography on the substrate, as shown in FIG. 6 C, the semiconductor layer from the upper multilayer reflective mirror 48 up to the portion of the spacer layer 42a or the lower multilayer reflective mirror 40 Li Active ion etching is performed to form a plurality of cylindrical or rectangular mesa portions (posts) 24. Here, two cylindrical mesa portions 24 are shown.

  Next, as shown in FIG. 7A, an oxidation region 46 a is formed around the oxidation control layer (AlAs layer) 46 in the mesa 24 by heat-treating the substrate under high-temperature steam. As a result, a light confinement region and a current confinement layer 46 b are formed inside the oxidation control layer 46.

Next, as shown in FIG. 7B, an interlayer insulating film 54 is laminated on the entire surface of the substrate, and a contact hole 54a is formed by removing only the inside of the contact electrode 52 at the top of the mesa portion 24. The interlayer insulating film 54 is etched using a mask pattern formed by a known photolithography process. As a material of the interlayer insulating film 54, for example, an inorganic insulating film such as aluminum nitride (AlN), alumina (Al ₂ O ₃ ), silicon nitride (SiN _x ), or the like is used. In particular, an insulating material containing aluminum has high thermal conductivity and is preferable as an interlayer insulating film material. The interlayer insulating film 54 may be a single layer of AlN or a laminated film combined with an inorganic insulating film such as Al ₂ O ₃ or SiN _x .

  Subsequently, as shown in FIG. 7C, a surface protective film 32 having a stress (normal stress f2) opposite to the normal stress f1 of the interlayer insulating film 54 is stacked on the entire surface of the substrate on the interlayer insulating film 54. Then, the surface protection film 32 is etched so that a contact hole 32 a somewhat larger than the contact hole 54 a of the interlayer insulating film 54 is formed at the top of the mesa portion 24. Simultaneously with the formation of the contact holes 32a, as shown in FIG. 4B, separation grooves 30 for separating the mesa portions 24 are formed in the surface protective film 32 by etching. The surface protection film 32 is etched using a mask pattern formed by a known photolithography process.

As a material of the surface protective film 32, silicon nitride (SiN _x ), silicon oxide (SiO ₂ ), silicon oxynitride (SiON), or the like can be used. For example, when an AlN or Al ₂ O ₃ single layer or laminated film is used for the interlayer insulating film 54, it is desirable to use silicon nitride (SiN _x ) for the surface protective film 32 because of the normal stress. When silicon nitride (SiN _x ) is used for the interlayer insulating film 54, it is preferable to use silicon oxide (SiO ₂ ) or silicon oxynitride (SiON).

  FIG. 8 is a comparative example of the reliability of the VCSEL array element according to the present embodiment by a high-temperature energization test. In this specification, the time when the optical output is reduced by 2 dB (down about 37%) at the time of constant current injection is defined as a failure, and the time until half of the elements put into the test fail is referred to as an average failure time Ft. For this average failure time Ft, FIG. 8A shows the result of the conventional structure in which the surface protective film 32 is continuously formed and there is no separation groove, and FIG. 8B shows that the surface protective film 32 is cut between the mesa portions 24. The result obtained by the VCSEL array element according to the present embodiment having the separation groove 30 is shown. As is clear from these figures, the average failure time Ft of the VCSEL array element of the conventional structure is about 120 hours, whereas the average failure time Ft of the VCSEL array element of this embodiment is about 180 hours. In addition, it can be seen that the VCSEL array element according to this example has an average failure time increased by about 50% and improved reliability.

In addition, since AlN, Al ₂ O _{3 and the} like used for the interlayer insulating film 54 have high thermal conductivity and good heat dissipation, the heat generated together with light from the quantum well active layer 44 is generated by the interlayer insulating film 54. It can be efficiently discharged to the outside via As a result, the characteristics of the VCSEL device at high temperature were improved, and the maximum oscillation temperature was improved by 20% from 100 degrees to 120 degrees (not shown). As a result, stable operation can be maintained even at high temperature operation.

  Next, a second embodiment of the present invention will be described. In the first embodiment, the isolation groove is formed only in the surface protective film, but in the second embodiment, the isolation groove is formed in the surface protective film and the interlayer insulating film immediately below the surface protective film.

  FIG. 9 is a diagram showing a cross-section of the main part of the VCSEL array element according to the second embodiment. The same components as those in FIG. 4B are given the same reference numerals. As shown in the drawing, the isolation trench 30a of the second embodiment penetrates not only the surface protective film 32 but also the interlayer insulating film 54 and reaches the semiconductor surface. As described above, by providing the surface protective film 32 having normal stress in the opposite direction on the interlayer insulating film 54, one of the aims of the invention is to relieve the stress or suppress its generation. However, it is difficult to eliminate this completely. Accordingly, since the interlayer insulating film 54 itself is expected to mediate the propagation of stress, the stress is also propagated through the interlayer insulating film 54 by forming a cut or slit similarly to the surface protective film 32. It is cut off and long-term reliability can be improved.

  Next, a third embodiment of the present invention will be described. In the second embodiment, the isolation groove 30a removes a part of the interlayer insulating film 54. However, if the semiconductor surface exposed by the removal of the interlayer insulating film 54 is exposed to the atmosphere, it causes oxidation and corrosion. sell. In order to avoid this, in the third embodiment, as shown in FIG. 10, it is possible to fill a resin 60 such as polyimide in a space including the separation groove 30a between the mesa portions. Polyimide, which is an organic polymer compound containing an imide bond, is more stretchable than an inorganic insulating film, and is less likely to cause stress with the surface protective film 32 in contact therewith. Furthermore, since it does not mediate the propagation of stress, the influence of the stress basis on the long-term reliability is small. However, because of its low thermal conductivity and hygroscopicity, use in high temperature and high humidity environments requires special attention.

  In the following, the fourth to ninth embodiments of the present invention will be described. In the drawings used for these descriptions, the same reference numerals are assigned to the same components as those in the first to third embodiments. It is attached.

FIG. 11 shows a plan view of a VCSEL array element according to the fourth embodiment of the present invention. In the fourth embodiment, as shown in FIG. 11A, a plurality of grooves 70A are formed along the longitudinal direction of the substrate 22 on which the array elements are formed. Not completely divided. That is, the grooves 70A is a slit closed with a fixed length in the lateral direction perpendicular to the longitudinal direction of the substrate 22, the surface protective film 3 2 remain without being separated at both ends in the short direction of the substrate 22 ing. Similar to the first to third embodiments, such a groove 70A relieves the stress of the interlayer insulating film and reduces the exposed area by the groove 70A, so that moisture and moisture enter from the outside. This makes it difficult to improve moisture resistance and water resistance.

  FIG. 11B is a modification of the fourth embodiment. In this modification, the groove 70B formed between the mesa portions has a plurality of slits instead of a single slit. In the example shown in the figure, the groove 70B has three slits in the edge direction, which are arranged between the mesa portions in the longitudinal direction of the substrate. Since the exposed area by the groove 70B is further reduced, moisture resistance and water resistance to the array element can be improved.

  Next, FIG. 12 shows a plan view of a VCSEL array element according to the fifth embodiment of the present invention. In the first embodiment, an example in which n-1 separation grooves are formed when the number of mesas is n is shown. However, in the fifth embodiment, the number of grooves is not limited to n-1. , Forming a smaller number of grooves. In the example shown in FIG. 12A, the grooves 70 </ b> C are formed between every two mesa portions except for the mesa portions located on the left and right. This is an example. For example, when the number of mesa portions formed in the longitudinal direction of the substrate 22 becomes very large, the grooves may be formed at intervals of three or more. The groove pattern is not limited to one type, and a plurality of patterns may be formed. For example, as shown in FIG. 12B, every two grooves 70D including a plurality of slits are formed between the mesa parts, and every two straight grooves 70E are formed between the mesa parts, and the grooves 70D and 70E are formed. Are alternately arranged in the longitudinal direction of the substrate 22. By reducing the number of grooves with respect to the number of mesa portions, the exposed area is reduced, so that moisture resistance and water resistance are improved. On the other hand, the stress of the interlayer insulating film due to the trench is also relieved.

  Next, FIG. 13 shows a cross-sectional view of an essential part of a VCSEL array according to the sixth embodiment of the present invention. In the sixth embodiment, the groove 70 </ b> F is formed at a certain depth of the surface protective film 32 without completely dividing the surface protective film 32. For example, the groove 70F having a desired depth can be obtained by adjusting the etching time. Since the groove 70F does not expose the underlying interlayer insulating film 54, moisture and moisture are prevented from entering the interlayer insulating film 54 from the groove 70F, and the moisture resistance and water resistance of the array element are improved.

  Further, as shown in FIG. 13B, the cross-sectional shape of the groove 70G can be tapered. For example, the taper is formed by performing isotropic wet etching. Compared with the groove 70F having an acute step as shown in FIG. 13A, the groove 70G has an inclined step, so that stress concentration at the step is reduced. In addition, the adhesion of the surface protective film 32 to the interlayer insulating film 54 is also improved. Further, when the embedding resin as shown in FIG. 10 is filled in the groove 70G, there is an advantage that voids are hardly generated in the groove 70G because the groove is inclined.

  Next, FIG. 14 shows a cross-sectional view of an essential part of a VCSEL array according to the seventh embodiment of the present invention. The seventh embodiment is a modification of the third embodiment shown in FIG. That is, in the seventh embodiment, the embedded resin 60A fills the groove 70G formed in the surface protective film 32 and the interlayer insulating film 54, but does not fill the entire space between the mesa portions. By limiting the filling amount of the embedded resin 60A, it is possible to reduce the thermal stress that the resin 60A may have in the vicinity of the oxidation control layer in the mesa portion.

  Next, FIG. 15 shows a cross-sectional view of a relevant part of a VCSEL array according to an eighth embodiment of the present invention. In the eighth embodiment, the space between the mesas is filled with an insulating material 80 such as polyimide, and the space between the mesas 24 is flattened. The interlayer insulating film 54B and the surface protective film 32B are formed on the planarized insulating material 80, and a groove 70H is formed in the surface protective film 32B. By flattening between the mesa portions, the interlayer insulating film 54B and the surface protective film 32B can be easily formed, and the film thicknesses thereof can be reduced.

Next, FIG. 16 shows a cross-sectional view of an essential part of a VCSEL array according to the ninth embodiment of the present invention. FIG. 16 corresponds to a cross section taken along line BB in FIG. In the ninth embodiment, unlike the first embodiment (see FIG. 4B), an intermediate mesa portion 24A is formed between the mesa portion 24 and the mesa portion 24 that emit light. The intermediate mesa portion 24A has the same semiconductor laminated structure as the mesa portion 24, and an electrode layer is wired on the top of the mesa. In such an array device configuration, grooves 70J are formed in the surface protective film 32 on the bottom of the main support section, the groove 70K is formed on the surface protective film 32 of the mesa top of the intermediate mesa portion 24A. Since the groove 70J is close to the mesa portion 24, the stress relaxation of the interlayer insulating film 54 can be effectively performed. Further, since the groove 70K is located at a position away from the mesa unit 24, a moisture or moisture intrusion path to the mesa unit 24 becomes long from the groove 70K, which is effective for moisture resistance or water resistance of the mesa unit 24.

  As described above, according to the above embodiment, the stress of the interlayer insulating film is relieved by the formation of the surface protective film and the formation of the isolation groove or groove in the VCSEL array element, and the reliability of the element can be improved. The number or shape of the separation grooves or grooves can be changed as appropriate according to the purpose and application. It is also possible to combine the first to ninth embodiments.

  The above-described embodiments are illustrative, and the scope of the present invention should not be construed as being limited thereto, and can be realized by other methods within the scope satisfying the configuration requirements of the present invention. Needless to say.

  The surface-emitting type semiconductor array device according to the present invention is applied to light-emitting devices such as LEDs and laser diodes arranged in a one-dimensional or two-dimensional array on a substrate, and these are used as light sources for optical communication and optical recording. Can be used.

It is a top view which shows the structure of the VCSEL element by which the mesa part based on the Example of this invention was arranged in linear form. It is a figure which shows the other example of the separation groove formed on a board | substrate. It is a top view which shows the structure of the VCSEL element by which the mesa part based on the Example of this invention was arranged in two dimensions. 4A is a view showing a cross section taken along line AA of the array element shown in FIG. 1, and FIG. 4B is a view showing a cross section taken along line BB of the array element shown in FIG. 1 (excluding electrodes). It is a figure explaining the relationship of the normal stress of an interlayer insulation film and a surface protective film. It is process sectional drawing for demonstrating the manufacturing process of the VCSEL array element based on the Example of this invention. It is process sectional drawing for demonstrating the manufacturing process of the VCSEL array element based on the Example of this invention. It is a graph which shows the result of the high temperature electricity supply test compared with the VCSEL array element which concerns on the Example of this invention, and the conventional VCSEL array element. It is principal part sectional drawing of the VCSEL array element based on 2nd Example of this invention. It is principal part sectional drawing of the VCSEL array element which concerns on the 3rd Example of this invention. It is a top view which shows the structure of the VCSEL element by which the mesa part based on the 4th Example of this invention was arranged in linear form. It is a top view which shows the structure of the VCSEL element by which the mesa part based on the 5th Example of this invention was arranged in linear form. It is principal part sectional drawing of the array element which concerns on the 6th Example of this invention. It is principal part sectional drawing of the array element which concerns on the 7th Example of this invention. It is principal part sectional drawing of the array element which concerns on the 8th Example of this invention. It is principal part sectional drawing of the array element which concerns on the 9th Example of this invention. It is sectional drawing which shows the structure of the conventional VCSEL element.

Explanation of symbols

20: VCSEL array element 22: substrate 24: mesa portion 26: p-side electrode 28: n-side electrode 30, 30a: separation grooves 31a, 31b, 31c: separation groove pattern 32: surface protective film 40: lower DBR
42 (42a, 42b): spacer layer 44: active layer 46: AlAs layer 46a: oxidized region 48: upper DBR
50: Contact (cap) layer 52: Contact electrode 54: Interlayer insulating film 54a, 32a: Contact hole 60, 60A: Filling resin 70A, 70B, 70C, 70D, 70E: Groove 70F, 70G, 70H, 70J, 70K: Groove 80: Insulating material

Claims (19)

A longitudinally extending substrate on which at least a first multilayer reflective film, an active layer, and a second multilayer reflective film are formed;
A plurality of mesa portions formed in a predetermined arrangement direction on the substrate by selectively removing at least a part of the first multilayer film reflection film, the active layer, and the second multilayer film reflection film; ,
A selective oxidation region formed on at least one of the first multilayer film reflective film or the second multilayer film reflective film;
An interlayer insulating film covering the periphery, sidewalls and bottom of the top of each mesa portion ;
A surface protective film covering the interlayer insulating film,
In the surface protective film, a plurality of grooves that partition between the mesa portions are formed along the arrangement direction .
Surface emitting semiconductor laser array element. 2. The surface emitting semiconductor laser array element according to claim 1, wherein the groove is formed to reach the surface protective film and the interlayer insulating film immediately below the surface protective film. 3. The surface emitting semiconductor laser array element according to claim 1, wherein the groove is a slit that closes in a short direction perpendicular to the longitudinal direction of the substrate with a certain length . The surface emission according to any one of claims 1 to 3, wherein the number of the grooves is n-1 where n is the number of mesa portions arranged in a line (n is a natural number of 2 or more). Type semiconductor laser array element. 5. The surface emitting semiconductor laser array element according to claim 1, wherein the interlayer insulating film is a single inorganic insulating film or a laminated film composed of a plurality of inorganic insulating films made of different materials. The surface protective film is an insulating film having a film quality having a normal stress opposite to the normal stress when the interlayer insulating film has a normal stress that contracts or extends in a normal direction of the mesa portion. Item 6. The surface emitting semiconductor laser array device according to any one of Items 1 to 5. The surface emitting semiconductor laser array element according to claim 1, wherein at least one layer of the interlayer insulating film is made of an inorganic insulating film containing aluminum. 7. The surface emitting semiconductor laser array element according to claim 1, wherein the interlayer insulating film is a laminated film including an inorganic insulating film containing aluminum and an inorganic insulating film containing silicon. The surface emitting semiconductor laser array device according to claim 1, wherein the groove is filled with an insulating material. The first and second multilayer reflective films are III-V group semiconductor layers containing Al, and the selective oxidation region is a semiconductor layer containing Al selectively oxidized from the side surface of the mesa portion. 10. A surface emitting semiconductor laser array element according to claim 1, wherein A method of manufacturing a surface emitting semiconductor laser array element having a plurality of mesa portions formed,
Forming at least a first multilayer reflective film, an active layer, and a second multilayer reflective film on a substrate extending in a longitudinal direction;
Etching at least a part of the first multilayer film reflective film, the active layer, and the second multilayer film reflective film to form a plurality of mesa portions in a predetermined arrangement direction on the substrate;
Forming an oxidized region selectively oxidized from a side surface of the plurality of mesas,
Forming an interlayer insulating film on the substrate so as to cover the peripheral edge, side wall, and bottom of the top of each mesa unit ;
Forming a surface protective film on the interlayer insulating film;
Forming multiple grooves that partition the respective mesa portions on the surface protective film along the arrangement direction,
A method of manufacturing a surface emitting semiconductor laser array device having: The manufacturing method according to claim 11, wherein the groove reaches the interlayer insulating film immediately below the surface protective film. The manufacturing method according to claim 11, further comprising a step of filling the groove with an insulating resin. 14. The manufacturing method according to claim 11, wherein the number of the grooves is n−1, where n is the number of mesa portions arranged linearly (n is a natural number of 2 or more). . The manufacturing method according to claim 11, wherein the interlayer insulating film is a single inorganic insulating film or a laminated film including a plurality of inorganic insulating films made of different materials. The surface protective film is an insulating film having a film quality having a normal stress opposite to the normal stress when the interlayer insulating film has a normal stress that contracts or extends in a normal direction of the mesa portion. Item 16. The production method according to any one of Items 11 to 15. 17. The manufacturing method according to claim 11, wherein at least one layer of the interlayer insulating film is made of an inorganic insulating film containing aluminum. The manufacturing method according to claim 11, wherein the interlayer insulating film is a laminated film including an inorganic insulating film containing aluminum and an inorganic insulating film containing silicon. The manufacturing method according to claim 11, wherein the groove is a slit that closes with a certain length in a short direction perpendicular to the longitudinal direction of the substrate .

Images