JP6958592B2 - Surface emitting semiconductor laser element - Google Patents

Description

The present invention relates to a surface emitting semiconductor laser device.

Patent Document 1 describes a lower reflector formed by alternately laminating semiconductor films having different refractive coefficients on the surface of a semiconductor substrate, an active layer made of a semiconductor film, and a current constriction layer made of a semiconductor film. By etching a part of the semiconductor film formed by the semiconductor layer forming step and the semiconductor layer forming step of forming the upper reflecting mirror formed by alternately laminating semiconductor films having different refractive coefficients by epitaxial growth. , The mesa structure forming step of forming the mesa structure, the element separating groove forming step of forming the element separating groove by etching the semiconductor film formed by the semiconductor layer forming step to the surface of the semiconductor substrate, and the wall surface of the element separating groove. It is characterized by having an insulator protective film forming step of forming an insulator protective film made of an insulator and a metal film forming step of forming a metal protective film made of a metal material on the insulator protective film. A method for manufacturing a surface emitting laser is disclosed.

Patent Document 2 describes a second conductive type second semiconductor multilayer film that constitutes a resonator together with at least a first conductive type first semiconductor multilayer film, an active region, and a first semiconductor multilayer film on a substrate. A surface-emitting semiconductor laser apparatus in which a semiconductor layer including a contact layer is laminated and a light emitting portion for emitting laser light and a pad forming region are separated by a groove formed in the semiconductor layer, and is an outer edge of the pad forming region. An outer peripheral groove having a depth reaching the substrate is formed by etching the semiconductor layer, and the side surface of the pad forming region exposed by the outer peripheral groove and the surface of the pad forming region are covered with an insulating film. A surface-emitting semiconductor laser apparatus is disclosed, which is patterned so as to expose a substrate on the bottom surface of the semiconductor.

Japanese Unexamined Patent Publication No. 2011-114227 Japanese Patent No. 4946041

An object of the present invention is to provide a surface-emitting semiconductor laser device in which the complexity of the manufacturing process is suppressed as compared with the case where an antioxidant structure is provided on the side surface of the surface-emitting semiconductor laser device.

In order to achieve the above object, the surface emitting semiconductor laser element according to claim 1 includes an individualized substrate and a first conductive type first semiconductor multilayer film formed on the substrate. Formed in a mesa shape by a semiconductor layer including an active region and a second conductive type second semiconductor multilayer film forming a resonator together with the first semiconductor multilayer film, and a first groove provided in the semiconductor layer. A second groove provided so as to surround the first groove and a surface of the second groove are formed between the light emitting portion and the outer periphery of the substrate and the first groove. An antioxidant portion is provided , and the antioxidant portion is composed of a part of an insulating film integrally formed from the side surface of the light emitting portion to the outer periphery, and covers the entire inside of the second groove. It is a thing.

Further, in the invention according to claim 2 , at least a part of the insulating film is cut between the light emitting portion and the second groove in the invention according to claim 1.

Further, the invention according to claim 3 is an electrode arranged between the light emitting portion and the second groove and connected to the light emitting portion in the invention according to claim 1 or 2. A pad is further provided, and the second groove is provided so as to surround the light emitting portion and the electrode pad.

The invention according to claim 4 is the invention according to claim 1, wherein the antioxidant portion is a metal film, an oxide film, a semiconductor layer, and an ion implantation region formed inside the second groove. It is one of the above.

Further, in the invention according to claim 5 , in the invention according to any one of claims 1 to 4 , the first groove has a depth that does not reach the substrate, and the second groove has a depth that does not reach the substrate. The groove has a depth that reaches the substrate.

The invention according to claim 6 is the invention according to any one of claims 1 to 5 , wherein the second groove is formed along the entire circumference of the outer periphery.

According to the invention of claim 1, in the surface emitting semiconductor laser device, the complexity of the manufacturing process is suppressed as compared with the case where the antioxidant structure is provided on the side surface of the surface emitting semiconductor laser element. The effect is obtained.

According to the second aspect of the present invention, as compared with the case where the insulating film is continuous between the light emitting portion and the second groove, the obstacle due to the oxidation of the side surface of the semiconductor layer causes the light emitting portion. It is possible to obtain the effect that the ripple effect on the above is further suppressed.

According to the third aspect of the present invention, there is an effect that the electrode can be taken out more easily as compared with the case where the second groove is not provided so as to surround the light emitting portion and the electrode pad.

According to the invention of claim 4 , the method of the antioxidant treatment is selected from a variety of methods according to the target surface emitting semiconductor laser device, as compared with the case where the antioxidant portion is an insulating film. The effect of being done is obtained.

According to the fifth aspect of the present invention, there is an effect that oxidation of the light emitting portion and the like is more reliably prevented as compared with the case where the second groove is formed without reaching the substrate. Be done.

According to the invention of claim 6 , it is possible to obtain the effect that oxidation of the light emitting portion or the like is more reliably prevented as compared with the case where the second groove is formed along a part of the outer circumference. ..

It is a vertical cross-sectional view which shows an example of the structure of the surface light emitting type semiconductor laser element which concerns on 1st Embodiment. It is a figure explaining the relationship between the antioxidant structure of the surface emitting semiconductor laser device which concerns on 1st Embodiment, and a dicing region. It is a top view which shows the wafer of the surface emitting type semiconductor laser array which concerns on 1st Embodiment. It is a part of the vertical sectional view which shows an example of the manufacturing method of the surface light emitting type semiconductor laser element which concerns on embodiment. It is a part of the vertical sectional view which shows an example of the manufacturing method of the surface light emitting type semiconductor laser element which concerns on embodiment. It is a part of the vertical sectional view which shows an example of the manufacturing method of the surface light emitting type semiconductor laser element which concerns on embodiment. It is a part of the vertical sectional view which shows an example of the manufacturing method of the surface light emitting type semiconductor laser element which concerns on embodiment. It is a vertical cross-sectional view which shows an example of the structure of the surface light emitting type semiconductor laser element which concerns on 2nd Embodiment. It is a vertical cross-sectional view which shows the structure of the surface light emitting type semiconductor laser element which concerns on the prior art.

Hereinafter, embodiments for carrying out the present invention will be described in detail with reference to the drawings.

[First Embodiment]
FIG. 1 is a vertical cross-sectional view showing an example of the configuration of a surface emitting semiconductor laser (VCSEL: Vertical Cavity Surface Emitting Laser) element 10 according to the present embodiment. In this embodiment, a GaAs-based surface-emitting semiconductor laser device using an n-type GaAs substrate will be described as an example, but the present invention is not limited to this, and InGaAsP-based, AlGaInP-based, InGaN / GaN-based materials, etc. It may be in the form of being applied to a surface emitting semiconductor laser device using. Further, the substrate is not limited to the n-type, and a p-type may be used. In that case, in the following description, the n-type and the p-type may be read in reverse.

As shown in FIG. 1, the VCSEL element 10 according to the present embodiment includes a post P, a pad forming region PA, an antioxidant structure 60, and an oxidation sacrificial region 62. The post P is a light emitting portion formed in a mesa shape, and the pad forming region PA is a region for forming the electrode pad 42. Further, the antioxidant structure 60 is a structure for preventing the side surface and the inside of the VCSEL element 10 from being oxidized. The oxidation sacrificial region 62 is a layer for allowing oxidation of the side surface and preventing the oxidation from proceeding inside the VCSEL element 10 in cooperation with the antioxidant structure 60.

As shown in FIG. 1, the post P, the pad forming region PA, and the oxidation sacrificial region 62 of the VCSEL element 10 have each semiconductor layer formed in common. That is, the VCSEL element 10 includes an n-type GaAs buffer layer 14 formed on the n-type GaAs substrate 12, a lower DBR (Distributed Bragg Reflector) 16, an active region 24, an AlAs layer 32, an upper DBR26, and a P-type GaAs contact layer. It is composed of 28 components. The resonator is composed of the interface between the lower DBR 16 and the active region 24 and the interface between the upper DBR 26 and the active region 24.

A silicon oxynitride film (SiON film) 34 as an insulating film is formed around the semiconductor layer including the mesa structure, and a P-type electrode 36 is provided via the silicon oxynitride film 34. The P-type electrode 36 is connected to the P-type GaAs contact layer 28 and forms ohmic contact with the P-type GaAs contact layer 28. The P-type electrode 36 is formed by, for example, forming a Ti (titanium) / Au (gold) laminated film. The silicon oxynitride film is an example of a material for an insulating film, and other materials such as a silicon nitride film (SiN) may be used.

On the other hand, the n-type electrode 30 is provided on the surface of the n-type GaAs substrate 12 opposite to the surface on which the semiconductor layer is formed. As an example, the n-type electrode 30 is formed by forming a laminated film of AuGe (alloy of gold and germanium) / Au.

Further, a silicon nitride film 40 is provided between the P-type GaAs contact layer 28 and the silicon oxynitride film 34 in the pad forming region PA and the oxidation sacrifice region 62. Further, an emission protection film 38 that protects the light emission surface is provided on the P-type GaAs contact layer 28.

As the n-type GaAs substrate 12 according to the present embodiment, a Si (silicon) -doped GaAs substrate is used as an example.

The n-type GaAs buffer layer 14 formed on the n-type GaAs substrate 12 and composed of Si-doped GaAs as an example is provided in order to improve the crystallinity of the substrate surface after thermal cleaning.

The n-type lower DBR 16 formed on the n-type GaAs buffer layer 14 has a thickness of 0.25λ /, respectively, when the oscillation wavelength of the VCSEL element 10 is λ and the refractive index of the medium (semiconductor layer) is n. It is a multilayer film reflector configured by alternately and repeatedly laminating two semiconductor layers having n and different refractive indexes. Specifically, the lower DBR16 has an _{n-type low refractive index layer made of Si-doped Al 0.9} Ga _0.1 As and an n-type layer made of Si-doped Al _0.3 Ga _0.7 As. It is configured by alternately and repeatedly laminating the high refractive index layer of. In the surface emitting semiconductor laser device 10 according to the present embodiment, the oscillation wavelength λ is set to 780 nm as an example.

The active region 24 according to the present embodiment is configured by laminating a lower spacer layer, a quantum well active layer, and an upper spacer layer in this order from the n-type GaAs substrate 12 side. The quantum well active layer according to the present embodiment is a quantum well active layer composed of four layers of Al _0.3 Ga _0.7 As and three layers of Al _0.11 Ga _0.89 As provided between them. It is composed of a well layer. The lower spacer layer and the upper spacer layer are arranged between the quantum well active layer and the lower DBR16 and the upper DBR26, respectively, to have a function of adjusting the length of the resonator and as a clad layer for confining the carrier. It also has a function.

The p-type AlAs layer 32 provided on the active region 24 is a current constriction layer, and includes a current injection region 32a and a selective oxidation region 32b. The current flowing from the p-type electrode 36 toward the n-type electrode 30 is throttled by the current injection region 32a.

The upper DBR26 formed on the AlAs layer 32 is a multilayer film reflector formed by alternately and repeatedly laminating two semiconductor layers having a film thickness of 0.25λ / n and different refractive indexes. Specifically, the upper DBR26 has a C (carbon) -doped Al _0.9 Ga _0.1 As p-type low refractive index layer and a C-doped Al _0.3 Ga _0.7 As. It is configured by alternately and repeatedly laminating the p-type high refractive index layer according to the above.

By the way, the above-mentioned VCSEL element can take out the laser output in the direction perpendicular to the substrate and can be easily arrayed by two-dimensional integration. Therefore, it is a light source for optical communication or a light source for electronic devices, for example, an electron. It is used as a light source for writing in a photographic system, a light source for drying ink, or a light source for machining.

The VCSEL element is an active layer (quantum well activity) provided between a pair of distributed Bragg reflectors (lower DBR16 and upper DBR26) provided on a semiconductor substrate (n-type GaAs substrate 12) and a pair of distributed Bragg reflectors. Layer) and a resonator spacer layer (lower spacer layer and upper spacer layer). Then, current is injected into the active layer by the electrodes (p-type electrode 36 and n-type electrode 30) provided on both sides of the distributed Bragg reflector to generate laser oscillation perpendicular to the substrate surface, and the upper part of the element (p-type electrode 36 and n-type electrode 30). The light oscillated from the surface side of the p-type GaAs contact layer 28) is emitted.

Further, it is provided with an oxidative constriction layer (AlAs layer 32) formed by oxidizing a semiconductor layer containing Al in the composition by reducing the threshold current and controlling the transverse mode. In this oxide-stenotic layer, a semiconductor layer that has been epitaxially grown (hereinafter, may be referred to as “epi-growth”) is etched in a mesa shape to form a post P, and the side surface of the post P is intentionally oxidized. Formed by doing.

When the VCSEL element formed as described above is separated by dicing and separated into individual pieces, the side surface of the semiconductor layer is exposed and is exposed to the outside air as it is. Therefore, unintended oxidation may proceed from the exposed side surface of the semiconducting layer, the semiconductor layer may deteriorate over time, and the insulating film may be peeled off or the metal wiring may be broken. This phenomenon occurs particularly remarkably under high temperature and high humidity.

FIG. 9 is a diagram for explaining the above phenomenon by exemplifying the VCSEL element 100 according to the prior art. The VCSEL element 100 does not have the antioxidant structure 60 and the oxidation sacrificial region 62 in the VCSEL element 10 according to the present embodiment. Since other configurations are the same as those of the VCSEL element 10, the same reference numerals are given to the same configurations.

As shown in FIG. 9, in the VCSEL element 100, an unintended oxidation region OX is formed in the layer directly connected to the post P. Although FIG. 9 illustrates the case where the lower DBR16 is oxidized, the oxidation can occur not only in the lower DBR16 but also in other semiconductor layers such as the upper DBR26 or the active region 24.

In order to cope with the above phenomenon, an antioxidant structure is known in which a groove is formed in a dicing region (planned division region) and the surface exposed by the groove is covered with an insulating film. In this antioxidant structure, after forming the antioxidant structure, dicing is performed along the groove. Therefore, in this antioxidant structure, it is necessary to form the groove width of the antioxidant structure wider than the width of the groove for dicing. As a result, the etching time for forming the groove of the antioxidant structure is prolonged, the thickness of the resist is increased due to the long-time etching, and the wide-width oxidation in the photolithography process after forming the groove of the antioxidant structure is performed. The manufacturing process becomes complicated, such as difficulty in removing the resist accumulated in the groove of the prevention structure.

Therefore, in the present invention, an antioxidant structure is adopted in which a groove is formed inside the dicing region and the surface of the groove is subjected to an antioxidant treatment. That is, as shown in FIG. 1, the antioxidant structure 60 according to the present embodiment is formed along the end face ES, which is the end face after dicing, and inside the end face ES. The antioxidant structure 60 includes, for example, an antioxidant groove T2 that reaches the n-type GaAs substrate 12 from the surface of the semiconductor layer, and a silicon oxynitride film 34 formed in the antioxidant groove T2. There is. The antioxidant groove T2 according to the present embodiment is an outer peripheral groove formed by surrounding the VCSEL element 10 including the post P and the pad forming region PA.

Therefore, mainly the side surface of the semiconductor layer of the VCSEL element 10 is protected by the silicon oxynitride film 34, and the oxidation of the semiconductor layer is suppressed. Further, according to the antioxidant structure 60, the antioxidant groove T2 of the antioxidant structure 60 can be formed regardless of the dicing region, so that the complexity in the manufacturing process of the VCSEL element 10 is suppressed.

The operation of the VCSEL element 10 according to the present embodiment will be described in more detail with reference to FIG. FIG. 2 is a diagram showing a VCSEL element 10 in a state immediately after the manufacturing process in a wafer state is completed and dicing, together with an adjacent VCSEL element 10', and FIG. 2A is a vertical cross-sectional view and a view thereof. 2 (b) shows a plan view.

As shown in FIG. 2, the antioxidant structure 60 of the VCSEL element 10 is provided along the dicing region 70 and inside the dicing region 70. The groove width Wa of the antioxidant structure is formed to be thinner than the dicing region width Wd. Here, the groove width Wa of the antioxidant structure is about 10 μm as an example, and the dicing region width Wd is 30 to 50 μm as an example. The width of the oxidation sacrificial region 62 is 5 to 10 μm as an example.

In FIG. 2A, the lower DBR16 of the VCSEL element 10 is oxidized to form an oxidation region OX. In this way, the end face ES after dicing may be oxidized. However, even if the end face ES is oxidized, the post P or the pad forming region PA of the VCSEL element 10 is protected by the silicon oxynitride film 34, so that the oxidation region OX proceeds to the post P or the pad forming region PA. Is suppressed. That is, the oxidation in the VCSEL element 10 is stopped in the oxidation sacrificial region 62, and in particular, the arrival at the post P which is the light emitting portion is suppressed.

FIG. 3 shows a plan view of the wafer WAF after the manufacturing process of the VCSEL element described later is completed. FIG. 3 illustrates an embodiment of the VCSEL array 10a in which the VCSEL elements 10 according to the present embodiment are arranged in an array.

The VCSEL array 10a is provided in the VCSEL elements 10 arranged in an array and the pad forming region PA, and includes each VCSEL element 10 and an electrode pad 42a connected by a wiring 44. Note that FIG. 3 illustrates a form in which 4 × 8 = 32 VCSEL elements 10 are arranged, but the present invention is not limited to this, and the number of VCSEL elements 10 is arranged as many as necessary according to the application and the like. good. Further, an electrode pad 42a is connected to each VCSEL element 10 by a wiring 44, and FIG. 3 shows an electrode pad 42a connected to one of the VCSEL elements 10 by a wiring 44.

As shown in FIG. 3, each VCSEL array 10a on the wafer WAF is separated by a dicing region (planned division region) 70, and an oxidation sacrificial region 62 and an antioxidant structure 60 are arranged on both sides of the dicing region 70. There is. Note that FIG. 3 illustrates a form in which the antioxidant structure 60 is provided in the directions of four sides of a rectangle along the dicing region 70, but the present invention is not limited to this, and the structure of the VCSEL element 10 and the like are taken into consideration. It may be provided in the direction of at least one side of the rectangle along the dicing region 70.

Next, an example of a method for manufacturing the surface-emitting semiconductor laser device 10 according to the present embodiment will be described with reference to FIGS. 4 to 8, and FIGS. 4 to 8 show manufacturing of the wafer WAF after epigrowth. Since it is a process, first, a method for manufacturing a wafer WAF until the completion of epi-growth shown in FIG. 4A will be described.

As shown in FIG. 4A, first, by the organic metal vapor phase growth (MOCVD) method or the like, an n-type having a carrier concentration of about 2 × 10 ¹⁸ cm ^-3 and a film thickness of about 500 nm is placed on the n-type GaAs substrate 12. The GaAs buffer layer 14 is laminated.

_{Next, on the n-type GaAs buffer layer 14, the Al 0.3} Ga _0.7 As layer and the Al _0.9 Ga _0.1 , each of which has a film thickness of 1/4 of the wavelength λ / n in the medium, are set. The As layer is alternately laminated for 37.5 cycles to form an n-type lower DBR16. At this time, _{the carrier concentration of the Al 0.3} Ga _0.7 As layer and the carrier concentration of the Al _0.9 Ga _0.1 As layer are each about 2 × 10 ¹⁸ cm ^-3, and the total thickness of the lower DBR 16 is It should be about 4 μm.

Next, on the lower DBR16, a lower spacer layer according to a non-doped _Al 0.6 _{Ga 0.4} As layer, and the undoped quantum well active layer, an upper non-doped a _Al 0.6 _{Ga 0.4} As layer It forms an active region 24 composed of a spacer layer. The quantum well active layer consists _{of four barrier layers made of Al 0.3} Ga _0.7 As layer and three quantum well layers _{made of Al 0.11} Ga _0.89 As provided between the barrier layers. It is configured. At this time, the film thickness of the barrier layer made of _{Al 0.3} Ga _{0.7 As is about 5 nm, and the film thickness of the quantum well layer made of Al 0.11} Ga _0.89 As is about 9 nm, respectively, and the entire active region 24 is set. The film thickness is the wavelength λ / n in the medium.

Next, a p-type AlAs layer 32 is formed on the upper spacer layer, on the AlAs layer 32, each thickness has been 1/4 of the wavelength in the medium _{λ / n, Al 0.3 Ga 0} . ₇ As layer and Al _0.9 Ga _0.1 As layer are alternately laminated for 25 cycles to form a p-type upper DBR26. At this time, _{the carrier concentration of the Al 0.3} Ga _0.7 As layer and the carrier concentration of the Al _0.9 Ga _0.1 As layer were set to about 2 × 10 ¹⁸ cm ^-3 , respectively, and the total film thickness of the upper DBR26 was It should be about 3 μm. On the upper DBR 26, a p-type GaAs contact layer 28 having a carrier concentration of about 1 × 10 ¹⁹ cm ^{-3 and a film thickness of about 10 nm is formed.}

In this production method, trimethylgallium, trimethylaluminum, and arsine are used as raw materials as an example, and disilane for n-type and carbon tetrabromide for p-type are used as dopants. Further, the substrate temperature at the time of growth is set to about 700 ° C., and the raw materials are sequentially changed under reduced pressure to continuously grow. In addition, in order to reduce the electrical resistance of the lower DBR and the upper DBR, a composition gradient region having a film thickness of about 20 nm in which the Al composition is gradually changed is provided at the layer interface in the lower DBR and in the upper DBR. There is also.

Next, a method of manufacturing the VCSEL element 10 according to the present embodiment after epi-growth will be described.

First, an electrode material is formed on the P-type GaAs contact layer 28 of the wafer WAF for which epi-growth has been completed, and then the material is etched using a mask by photolithography, for example, as shown in FIG. 4 (b). A contact metal CM for taking out the P-type electrode 36 is formed. The contact metal CM is formed by using a Ti (titanium) / Au (gold) laminated film as an example.

Next, a material to be an emission protective film is formed on the wafer WAF surface, and then the material is etched using a mask by photolithography, for example, to form an emission protective film 38 as shown in FIG. 4 (c). do. As an example, a SiN film is used as the material of the emission protective film.

Next, after forming a mask material on the WAF surface of the wafer, the mask material is etched by, for example, photolithography to form a mask for forming a post P as shown in FIG. 5 (a). As an example, a silicon nitride film is used as the material of the mask, and in FIG. 5A, the mask is shown as the silicon nitride film 40. A slit S1 for etching and forming the post P is formed in the mask.

Next, the wafer WAF is etched to dig a groove T1 to form a mesa-shaped post P as shown in FIG. 5 (b). The portion other than the post P separated by the groove T1 becomes the pad forming region PA.

Next, the wafer WAF is subjected to an oxidation treatment to oxidize the AlAs layer 32 from the side surface, and an oxidation stenosis layer is formed in the post P as shown in FIG. 5 (c). The oxidative stenosis layer is composed of a current injection region 32a and a selective oxidation region 32b. The selective oxidation region 32b is a region oxidized by the oxidation treatment, and the region left without being oxidized is the current injection region 32a. The current injection region 32a has a circular shape or a shape close to a circular shape, and the current injection region 32a narrows the current flowing between the p-type electrode 36 and the n-type electrode 30 of the VCSEL element 10, for example, the VCSEL element. The lateral mode in the oscillation of 10 is controlled.

Next, etching is performed using, for example, a photolithographic mask to form an antioxidant groove T2 as shown in FIG. 6 (a). In the present embodiment, the above-mentioned formation of the groove T1 and the formation of the antioxidant groove T2 by separate etching will be described as an example, but the present invention is not limited to this, and the groove T1 and oxidation are performed by one etching. It may be in the form of forming both of the prevention grooves T2. The width of the antioxidant groove T2 according to the present embodiment is formed to be narrower than the width of the dicing slit S2 described later.

Next, as shown in FIG. 6B, an insulating film made of the silicon oxynitride film 34 is formed on the entire surface of the wafer WAF. In this step, the antioxidant structure 60 according to the present embodiment is formed in which the side surface of the semiconductor layer is covered with an insulating film.

Next, the silicon oxynitride film 34 is etched using, for example, a mask by photolithography to form a contact hole CH and a dicing slit S2 as shown in FIG. 6 (c). The contact hole CH is an opening for connecting the contact metal CM and the p-type electrode 36 described later, and the dicing slit S2 is an opening for forming the dicing region 70 described later. In the region of the dicing slit S2, the protective film, that is, the silicon nitride film 40 and the silicon oxynitride film 34 are removed.

Next, after forming an electrode material on the WAF surface of the wafer, the electrode material is etched using, for example, a mask by photolithography, and as shown in FIG. 7A, the p-type electrode 36 and the electrode pad 42 are formed. Form. The p-type electrode 36 and the electrode pad 42 are formed by using a Ti (titanium) / Au (gold) laminated film as an example. By this step, the p-type electrode 36 is connected to the contact metal CM described above.

Next, as shown in FIG. 7B, an electrode material is formed on the back surface of the wafer WAF to form an n-type electrode 30. As an example, the n-type electrode 30 is formed by forming a laminated film of AuGe / Au.

Next, as shown in FIG. 7C, dicing is performed in the dicing region 70, and the VCSEL element 10 is separated and individualized. The VCSEL element 10 is manufactured by the above steps. In the present embodiment, the method for manufacturing the VCSEL element 10 has been illustrated and described, but the VCSEL array 10a is also manufactured by the above steps.

[Second Embodiment]
The VCSEL element 10b according to the present embodiment will be described with reference to FIG. The VCSEL element 10b according to the present embodiment is the above-mentioned VCSEL element 10 provided with the antioxidant slit S3.

Even when the antioxidant structure 60 is provided on the post P, which is a light emitting portion, as in the VCSEL element 10 according to the above embodiment, for example, a part of the semiconductor layer is oxidized to provide an insulating film (for example,). , The silicon oxynitride film 34) may be peeled off, or the metal wiring (for example, the electrode pad 42) generated as a result of the peeling of the insulating film may be disconnected.

FIG. 8A shows, as an example, the peeling of the silicon oxynitride film 34 caused by the oxidation of the portion corresponding to the lower DBR 16 of the oxidation sacrificial region 62 and the generation of the oxidation region OX as an obstacle OB. There is. When this obstacle OB progresses in the direction of the pad forming region PA, the electrode pad 42 (or the post P) of the pad forming region PA or the silicon oxynitride film 34 may be peeled off. This embodiment is a form corresponding to such a phenomenon.

FIG. 8B shows the VCSEL element 10b according to the present embodiment. As shown in FIG. 8B, the VCSEL element 10b includes an antioxidant slit S3 that cuts an insulating film between the pad forming region PA and the antioxidant structure 60. With this antioxidant slit S3, even if a failure OB occurs, the failure OB and the pad forming region PA (or post P) are separated. Therefore, even if a failure OB occurs, it is possible to prevent the secondary failure from spreading to the pad forming region PA (or post P) due to the failure OB.

Here, the above-mentioned antioxidant slit S3 may be provided by an independent etching step, but may be formed at the same time in the etching step of forming the contact hole CH and the dicing slit S2 shown in FIG. 6C. In this case, since the etching process is also used, it is not necessary to increase the manufacturing process.

Further, the antioxidant slit S3 may be formed by surrounding the VCSEL element 10b (post P, pad forming region PA) along the antioxidant structure 60, or may be partially formed in consideration of the target antioxidant portion and the like. May be formed in.

In each of the above embodiments, an antioxidant structure 60 in which an insulating film (silicon oxynitride film 34 in each of the above embodiments) is formed in the antioxidant groove T2 has been described as an example, but the present invention is not limited to this. .. Instead of forming an insulating film, for example, a metal film or an oxide film may be formed to cover the semiconductor layer, ions of a predetermined atom may be injected, or another semiconductor layer may be re-injected. You may grow it.

Further, in each of the above embodiments, the embodiment in which the antioxidant groove T2 is formed by reaching the n-type GaAs substrate 12 has been illustrated and described, but the present invention is not limited to this. The antioxidant groove T2 may be formed by reaching, for example, the upper DBR26, or may be formed by reaching the AlAs layer (oxidation stenosis layer) 32 in consideration of the object of oxidation prevention.

10, 10b, 10'VCSEL element 10a VCSEL array 12 n-type GaAs substrate 14 n-type GaAs buffer layer 16 Lower DBR
24 Active region 26 Upper DBR
28 p-type GaAs contact layer 30 n-type electrode 32 AlAs layer 32a Current injection region 32b Selective oxidation region 34 Silicon oxynitride film (SiON film)
36 p-type electrode 38 Exit protection film 40 Silicon nitride film (SiN film)
42, 42a Electrode pad 44 Wiring 60 Antioxidant structure 62 Dicing area 70 Dicing area CH Contact hole CM Contact metal ES End face OB Obstacle OX Oxidation area P Post PA Pad formation area S1 Slit S2 Dicing slit S3 Antioxidation slit T1 Groove T2 Oxidation Prevention groove WAF Wafer Wa Antioxidation structure groove width Wd Dicing area width

Claims (6)

The individualized board and
A semiconductor including a first conductive type first semiconductor multilayer film formed on the substrate, an active region, and a second conductive type second semiconductor multilayer film forming a resonator together with the first semiconductor multilayer film. Layer and
A light emitting portion formed in a mesa shape by a first groove provided in the semiconductor layer, and a light emitting portion.
A second groove provided so as to surround the first groove between the outer periphery of the substrate and the first groove, and
An antioxidant portion formed on the surface of the second groove is provided .
The antioxidant portion is a surface-emitting semiconductor laser device that is composed of a part of an insulating film integrally formed from the side surface of the light emitting portion to the outer periphery and covers the entire inside of the second groove. The surface-emitting semiconductor laser device according to claim 1 , wherein at least a part of the insulating film is cut between the light emitting portion and the second groove. An electrode pad arranged between the light emitting portion and the second groove and connected to the light emitting portion is further provided.
The second is the groove surface emitting semiconductor laser device according to claim 1 or claim 2 is provided so as to surround the light emitting portion and the electrode pad. The surface emitting semiconductor laser device according to claim 1, wherein the antioxidant portion is any one of a metal film, an oxide film, a semiconductor layer, and an ion implantation region formed inside the second groove. The surface-emitting semiconductor according to any one of claims 1 to 4 , wherein the first groove has a depth that does not reach the substrate, and the second groove has a depth that reaches the substrate. Laser element. The surface-emitting semiconductor laser device according to any one of claims 1 to 5 , wherein the second groove is formed along the entire circumference of the outer circumference.

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