WO2017212887A1

WO2017212887A1 - Vertical-cavity surface-emitting laser

Info

Publication number: WO2017212887A1
Application number: PCT/JP2017/018674
Authority: WO
Inventors: 一平松原; 岩田　圭司; 新治鏑木
Original assignee: 株式会社村田製作所
Priority date: 2016-06-07
Filing date: 2017-05-18
Publication date: 2017-12-14
Also published as: TW201743523A

Abstract

In this vertical-cavity surface-emitting laser (10), a semiconductor multilayer film (5) provided on a semiconductor substrate (11) is provided with a first DBR layer (13), an active layer (15), a current confinement layer (23), and a second DBR layer (24). The upper surface of an insulating layer (31) covering the side ends of the semiconductor multilayer film (5) is connected to the upper surface of the semiconductor multilayer film (5) and extends along the semiconductor substrate (11). The end surface (62) of the insulating layer (31) is connected to the upper surface (61) of the insulating layer (31) and extends toward the semiconductor substrate (11). First and second contact electrodes (26, 27) are electrically connected with each of the first DBR layer (13) and the upper surface of the semiconductor multilayer film (5). A bonding pad (33) is provided either directly on the semiconductor substrate (11) or with an insulating film (30) therebetween. Metal wiring (32) provided on the insulating layer (31) connects the second contact electrode (26) and the bonding pad (33).

Description

Vertical cavity surface emitting laser

This disclosure relates to vertical cavity surface emitting lasers.

A vertical cavity surface emitting laser (VCSEL: Vertical Cavity Surface Emitting Laser) is a semiconductor laser device that outputs laser light in a direction perpendicular to a substrate surface by forming an optical resonator in a direction perpendicular to the substrate surface.

A specific configuration of the VCSEL is disclosed in, for example, International Publication No. 2013/176201 (Patent Document 1). As shown in FIG. 2 of Patent Document 1, a VCSEL includes a semi-insulating semiconductor substrate, an N-type semiconductor contact layer, an N-type DBR (Distributed Bragg Reflector) layer, an active layer including a quantum well, a P-type DBR layer, and a P-type Type semiconductor contact layers are provided in this order. An anode electrode is formed on the surface of the P-type semiconductor contact layer. A cathode electrode is formed in the portion where the N-type semiconductor contact layer is exposed by etching. Further, a pad electrode is formed in a region where the N-type DBR layer is exposed by etching, with a thick organic resin insulating layer such as polyimide interposed. The pad electrode is connected to the anode electrode by a metal wiring.

International Publication No. 2013/176201

In the VCSEL structure of the above-mentioned Patent Document 1, there is a problem that the pad electrode and the N-type DBR layer are opposed to each other with an insulating layer interposed therebetween, so that there is a large parasitic capacitance. As a result, the high-speed modulation characteristic of the VCSEL element changes.

This disclosure takes the above-mentioned problems into consideration, and its main purpose is to provide a vertical cavity surface emitting laser capable of reducing parasitic capacitance.

A vertical cavity surface emitting laser according to one aspect of the present disclosure includes an insulating or semi-insulating substrate and a semiconductor multilayer film provided on the substrate. The semiconductor multilayer film includes a first DBR layer, an active layer, and a second DBR layer in order from the substrate side. The semiconductor stacked film is further provided between the first DBR layer and the active layer, between the second DBR layer and the active layer, inside the first DBR layer, and inside the second DBR layer. At least one current confinement layer formed at least one is provided. The vertical cavity surface emitting laser further includes an insulating layer, a first contact electrode, a second contact electrode, a bonding pad, and a metal wiring. The insulating layer covers at least a part of the side end portion of the semiconductor multilayer film, and has an upper surface and an end surface. The upper surface of the insulating layer is connected to the upper surface of the semiconductor multilayer film and extends along the substrate. The end surface of the insulating layer is connected to the upper surface of the insulating layer and extends toward the substrate. The first contact electrode is electrically connected to the first DBR layer. The second contact electrode is provided on the upper surface of the semiconductor stacked film. The bonding pad is provided directly on the substrate or with an insulating film interposed. The metal wiring is provided on the upper surface and the end surface of the insulating layer, and connects the second contact electrode and the bonding pad.

According to the above configuration, by providing the bonding pad directly or on the insulating or semi-insulating substrate with the insulating film interposed, the parasitic capacitance of the bonding pad is suppressed and the VCSEL device can be modulated at high speed. .

Preferably, the side end portion of the semiconductor multilayer film has two or more step portions. The first step portion reaches from the upper surface of the semiconductor multilayer film to a position where the end face of the at least one current confinement layer is exposed. The step portion at the final stage reaches the substrate. The bottom surface of the step portion at the final stage is on the extended surface of the interface between the semiconductor multilayer film and the substrate or at a position closer to the back surface of the substrate than the extended surface.

Here, the step portion is constituted by two surfaces having different distances from the substrate, that is, an upper surface and a bottom surface, and an end surface connecting these two surfaces. The top surface and the bottom surface extend in a direction along the substrate, and the end surface extends in a direction intersecting the substrate. The top surface is located farther from the substrate than the bottom surface. When the second step portion is formed next to the first step portion, the bottom surface of the first step portion and the top surface of the second step portion are the same surface.

According to the above configuration, the size of the upper surface of the first step portion and the size of the upper surface of the second step portion can be controlled separately. Therefore, by reducing the area of the upper surface of the first step portion, the parasitic capacitance due to the oxidized region of the current confinement layer is suppressed, and the resistance of the VCSEL element is increased by increasing the area of the upper surface of the second step portion. The value (particularly the resistance value of the first DBR layer) can be reduced.

More preferably, the side end portion of the semiconductor laminated film has three steps including a first step portion, a second step portion, and a third step portion at the final stage.

According to the above configuration, the first step portion is formed to produce an oxide layer by exposing the end face of the at least one current confinement layer. The second step portion is formed to adjust the resistance value of the VCSEL element. The third step portion is formed to expose the surface of the substrate in order to dispose the bonding pad.

Preferably, the end surfaces of the first and second step portions are perpendicular to the substrate.
As described above, the shape of the upper surface of the first stepped portion and the shape of the upper surface of the second stepped portion can be precisely controlled by forming the end surface of the stepped portion perpendicular to the substrate.

Preferably, when the substrate is viewed in plan, the shape of the outer edge portion of the upper surface of the second stepped portion is an arc shape at least partially.

In plan view, by making the shape of the portion where the upper surface of the first stepped portion is combined with the upper surface of the second stepped portion into a substantially circular shape, the current can flow more uniformly and current concentration can be prevented. . Furthermore, stress concentration on the insulating layer can be reduced.

Preferably, the semiconductor multilayer film further includes a first semiconductor contact layer between the substrate and the first DBR layer. In this case, the second stepped portion reaches halfway through the first semiconductor contact layer. The first contact electrode is provided on the bottom surface of the second step portion.

By providing the first semiconductor contact layer as described above and forming the first contact electrode on the exposed surface of the first semiconductor contact layer, the gap between the first contact electrode and the first semiconductor contact layer is formed. Contact resistance can be stably reduced.

Preferably, when the substrate is viewed in plan, the area of the portion surrounded by the outer edge portion on the upper surface of the second stepped portion is 2000 μm ² or more.

By extending the size of the upper surface of the second step portion to the above degree, the resistance value of the VCSEL element can be sufficiently reduced until it enters the saturation region.

Preferably, the bonding pad is provided on the substrate with an insulating film interposed. This insulating film covers the portion where the surface of the substrate is exposed and the upper surface and side end portions of the semiconductor multilayer film, except for the first and second contact electrodes. This insulating film is formed of an inorganic material. The insulating layer is formed of an organic resin material and covers at least a part of the side end portion of the semiconductor multilayer film with the insulating film interposed therebetween.

By providing an insulating film made of an inorganic material as described above, the moisture resistance of the VCSEL element can be improved.

A vertical cavity surface emitting laser according to another aspect of the present disclosure includes a semi-insulating substrate and a semiconductor multilayer film formed on the substrate. The semiconductor multilayer film includes, in order from the substrate, a first semiconductor contact layer, a first DBR (Distributed Bragg Reflector) layer, an active layer, and a second DBR layer. The semiconductor stacked film is further provided between the first DBR layer and the active layer, between the second DBR layer and the active layer, inside the first DBR layer, and inside the second DBR layer. At least one current confinement layer is provided. The side end portion of the semiconductor laminated film has three steps. The first step portion reaches from the upper surface of the semiconductor multilayer film to a position where the end face of the at least one current confinement layer is exposed, but does not reach the first semiconductor contact layer. The second step portion reaches the middle of the first semiconductor contact layer from the bottom surface of the first step portion. The third step portion reaches the substrate from the bottom surface of the second step portion. The vertical cavity surface emitting laser further includes a first contact electrode and a second contact electrode. The first contact electrode is provided on the bottom surface of the second step portion. The second contact electrode is provided on the upper surface of the semiconductor stacked film.

Therefore, according to the vertical cavity surface emitting laser of this disclosure, the parasitic capacitance can be reduced.

It is sectional drawing which shows typically the structure of VCSEL by 1st Embodiment. It is a flowchart which shows the manufacturing process of VCSEL of FIG. It is sectional drawing which shows the semiconductor laminated film epitaxially grown on the semiconductor substrate. It is sectional drawing which shows the semiconductor laminated film after the process of a 1st level | step-difference part. It is sectional drawing which shows the semiconductor laminated film after formation of the 2nd and 3rd level | step-difference part. It is a figure which shows the cross-sectional structure after formation of a contact electrode and an insulating protective film in the manufacturing process of VCSEL. It is sectional drawing which shows typically the structure of VCSEL by a 1st modification. It is sectional drawing which shows typically the structure of VCSEL by a 2nd modification. It is the figure which put together the merit and demerit of the element structure of VCSEL of FIG.1, FIG.7, and FIG.8 in the table format. It is a top view which shows the example of a layout of VCSEL. FIG. 11 is a cross-sectional view taken along a cutting line XI-XI in FIG. 10. It is a figure which shows the change of the resistance value of a VCSEL element when the magnitude | size of the upper surface of a 2nd level | step-difference part is changed. It is a figure which shows the change of the parasitic capacitance when the magnitude | size of the upper surface of a 2nd level | step-difference part is changed.

Hereinafter, embodiments will be described in detail with reference to the drawings. The same or corresponding parts are denoted by the same reference numerals, and description thereof will not be repeated.

<First Embodiment>
[Configuration of VCSEL]
FIG. 1 is a cross-sectional view schematically showing the structure of the VCSEL according to the first embodiment. In FIG. 1, for ease of illustration, the thickness of each layer in the figure is not proportional to the actual device thickness. In the following description, the surface of each semiconductor layer close to the substrate is referred to as a lower surface, and the surface opposite to the substrate is referred to as an upper surface.

Referring to FIG. 1, the VCSEL 10 includes a semi-insulating semiconductor substrate 11 and a semiconductor multilayer film 5 formed on the main surface of the semiconductor substrate 11 by epitaxial growth. The semiconductor laminated film 5 includes an N-type semiconductor contact layer 12 (first semiconductor contact layer), an N-type DBR (Distributed Bragg Reflector) layer 13 (first DBR layer), a cladding layer 14, in order from the semiconductor substrate 11 side. An active layer 15 including a quantum well, a cladding layer 16, a current confinement layer 23, a P-type DBR layer 24 (second DBR layer), and a P-type semiconductor contact layer 25 (second semiconductor contact layer) are provided.

As the semiconductor substrate 11, for example, a non-doped GaAs (gallium arsenide) substrate exhibiting semi-insulating properties is used. Note that an insulating substrate may be used instead of the semi-insulating semiconductor substrate 11 as long as the semiconductor stacked film 5 can be epitaxially grown.

An N-type semiconductor contact layer 12 is formed on the surface of the semiconductor substrate 11. As the N-type semiconductor contact layer 12, in order to form a good ohmic contact with the cathode electrode 27, for example, a GaAs layer having an impurity concentration of 3.0 × 10 ¹⁸ [cm ⁻³ ] or more is formed. For example, Si (silicon) is doped to give N-type conductivity. Si coordinates to a Ga (or Al) site and easily becomes a donor.

Note that the N-type semiconductor contact layer 12 is not necessarily provided. That is, the N-type DBR layer 13 can also serve as the N-type semiconductor contact layer 12. In this case, the cathode electrode 27 is directly connected to the N-type DBR layer 13.

The N-type DBR layer 13 has, for example, a structure in which Al _0.12 Ga _0.88 As and Al _0.9 Ga _0.1 As are alternately stacked at an optical thickness of λ / 4. λ represents the wavelength of the laser beam. Si (silicon) is doped to give N-type conductivity, and its concentration is, for example, 2 to 3 × 10 ¹⁸ [cm ⁻³ ].

Al _X Ga _(1-X) As (aluminum, gallium, arsenic) is a mixed crystal semiconductor of GaAs and AlAs. The higher the Al composition (X), the wider the energy gap and the lower the refractive index. When the Al composition (X) is 0 ≦ X <0.43, the direct transition type is obtained. Since the lattice constant hardly changes depending on the Al composition (X), an Al _x Ga _(1-x) As film having any Al composition (X) can be epitaxially grown on the GaAs substrate. In this specification, when the Al composition (X) is not specified, it may be described as AlGaAs.

An active region 17 for generating laser light is formed on the N-type DBR layer 13. The active region 17 includes the clad

layers

14 and 16 and the active layer 15 having an optical gain sandwiched between the

clad layers

14 and 16. In the active layer 15, a multiple quantum well (MQW) in which a quantum well layer and a barrier layer are stacked in multiple layers is formed. The active layer 15 is a non-doped region where impurities are not introduced.

The cladding layers 14 and 16 can be undoped or can be doped only in the vicinity of the DBR layers 13 and 24 according to the design of the resistance value of the device. The clad layers 14 and 16 are made of a material having an energy gap wider than that of the active layer 15 for carrier confinement. For example, direct transition AlGaAs is used. The clad layers 14 and 16 may be provided only on one side or on both sides.

A current confinement layer 23 is formed on the active region 17. The current confinement layer 23 efficiently injects a current into the active region and brings about a lens effect. As shown in FIG. 1, the current confinement layer 23 has an unoxidized region 21 at the center and an oxidized region 22 of a substantially insulator around the center. In this structure, the current confinement layer 23 is formed of Al _X Ga _(1-X) As satisfying 0.95 ≦ X ≦ 1 (when X = 1, that is, including AlAs), and the current confinement is included in the semiconductor laminated film 5. After the portion including the layer 23 is processed into a mesa post shape, the current confinement layer 23 is selectively oxidized from the surroundings in a heated steam atmosphere. Since only the unoxidized region 21 in the central portion serves as a current path, current can be efficiently injected into the active region.

Although different from the case of FIG. 1, it is also possible to provide the current confinement layer 23 in either the DBR layers 13 and 24 (desirably close to the active layer 15) and the

clad layers

14 and 16. It is also possible to provide a plurality of current confinement layers 23. Therefore, more generally, the current confinement layer 23 is formed between the N-type DBR layer 13 and the active layer 15, between the P-type DBR layer 24 and the active layer 15, inside the N-type DBR layer 13, and P At least one is provided at one or more locations inside the mold DBR layer 24.

A P-type DBR layer 24 is provided on the current confinement layer 23. Similar to the N-type DBR layer 13, the P-type DBR layer 24 has a structure in which, for example, Al _0.12 Ga _0.88 As and Al _0.9 Ga _0.1 As are alternately stacked at an optical thickness of λ / 4. In order to give P-type conductivity, C (carbon) is doped, and its concentration is, for example, 2 to 3 × 10 ¹⁸ [cm ⁻³ ]. C is easily coordinated to the As site and becomes an acceptor. The N-type DBR layer 13 and the P-type DBR layer 24 constitute an optical resonator.

A P-type semiconductor contact layer 25 is formed on the upper surface of the P-type DBR layer 24. As the P-type semiconductor contact layer 25, in order to form a good ohmic contact with the anode electrode 26, for example, a GaAs layer having an impurity concentration of 3.0 × 10 ¹⁸ [cm ⁻³ ] or more is formed. For example, C is doped to provide P-type conductivity. Note that the P-type semiconductor contact layer 25 is not necessarily provided. That is, the P-type DBR layer 24 can also serve as the P-type semiconductor contact layer 25. In this case, the anode electrode 26 is formed on the upper surface of the P-type DBR layer 24.

Three

step portions

41, 42, and 43 are formed by etching at the side end portion of the semiconductor laminated film 5 described above. The first step portion 41 reaches from the upper surface of the semiconductor multilayer film 5 to a position where the end face of the current confinement layer 23 is exposed. In the case of FIG. 1, the first step portion 41 reaches halfway through the N-type DBR layer 13. The second step portion 42 reaches the middle of the N-type semiconductor contact layer 12 from the bottom surface of the first step portion 41. The third step portion 42 reaches the semiconductor substrate 11 from the bottom surface of the second step portion 42.

The VCSEL 10 further includes a cathode electrode 27, an anode electrode 26, an insulating protective film 30 (insulating film), an insulating layer 31, a bonding pad 33, and a metal wiring 32. The cathode electrode 27 and the anode electrode 26 are collectively referred to as a contact electrode (the cathode electrode 27 is referred to as a first contact electrode, and the anode electrode 26 is referred to as a second contact electrode).

The cathode electrode 27 is formed on the upper surface of the N-type semiconductor contact layer 12 exposed by etching. The anode electrode 26 is formed on the upper surface of the P-type semiconductor contact layer 25. When the N-type semiconductor contact layer 12 and the P-type semiconductor contact layer 25 are not provided, the cathode electrode 27 is formed on the upper surface of the N-type DBR layer 13 exposed by etching, and the anode electrode 26 is formed of P It is formed on the upper surface of the type DBR layer 24.

The insulating protective film 30 is provided for moisture resistance, and excludes the cathode electrode 27 and the anode electrode 26, and the upper surface and side end portions (

step portions

41, 42, 43) of the semiconductor multilayer film 5 and the main surface of the semiconductor substrate 11. It is formed so as to cover. The insulating protective film 30 is an inorganic insulating film, and for example, silicon nitride or silicon oxide is used. Note that the insulating protective film 30 is not necessarily provided.

The insulating layer 31 is formed on the insulating protective film 30 so as to cover at least a part of the side end portions (

step portions

41, 42, 43) of the semiconductor multilayer film 5. As shown in FIG. 1, the insulating layer 31 has an upper surface 61 and an end surface 62. The upper surface 61 of the insulating layer 31 is connected to the upper surface of the semiconductor stacked film 5 and extends along the semiconductor substrate 11 (that is, faces the semiconductor substrate 11). The end surface 62 of the insulating layer 31 is connected to the upper surface 61 of the insulating layer 31 and extends toward the semiconductor substrate 11. As the insulating layer 31, a photosensitive organic resin material such as photosensitive polyimide is used.

The insulating layer 31 does not need to cover the entire side end portion of the semiconductor laminated film 5. In the region between the bonding pad 33 and the upper surface of the semiconductor multilayer film 5 (the upper surface of the P-type semiconductor contact layer 25), the insulating layer 31 is formed on the side end portions (

step portions

41, 42, 43) of the semiconductor multilayer film 5. It covers everything. On the other hand, in the region between the cathode electrode 27 and the upper surface of the semiconductor multilayer film 5 (the upper surface of the P-type semiconductor contact layer 25), the insulating layer 31 covers the first step portion 41 and the second step portion 42. However, the third stepped portion 43 and the cathode electrode 27 are not covered.

The bonding pad 33 is formed on the main surface of the semiconductor substrate 11 exposed by etching the semiconductor multilayer film 5 with the insulating protective film 30 interposed therebetween. When the insulating protective film 30 is not provided, the bonding pad 33 is formed directly on the main surface of the semiconductor substrate 11.

The metal wiring 32 that connects the bonding pad 33 and the anode electrode 26 is formed on the upper surface 61 and the end surface 62 of the insulating layer 31. In order to reduce the parasitic capacitance, the area of the metal wiring 32 is made sufficiently small in plan view of the semiconductor substrate 11 (which is considerably smaller than the area of the bonding pad 33). Since the bonding pad 33 does not exist on the insulating layer 31 and does not face the N-type semiconductor contact layer 12 and the N-type DBR layer 13, the parasitic capacitance due to the bonding pad 33 becomes sufficiently small.

[Manufacturing method of VCSEL]
FIG. 2 is a flowchart showing manufacturing steps of the VCSEL of FIG. The VCSEL manufacturing process will be described below with reference to FIG. 2 and the cross-sectional views of FIGS. 3 to 6, the thickness of each layer in the figure is not proportional to the actual device thickness in order to facilitate illustration.

First, the semiconductor multilayer film 5 is epitaxially grown on the semiconductor substrate 11 (step S100). FIG. 3 is a cross-sectional view showing the semiconductor laminated film 5 epitaxially grown on the semiconductor substrate. As described above, the semiconductor multilayer film 5 includes the N-type semiconductor contact layer 12, the N-type DBR (Distributed Bragg Reflector) layer 13, the clad layer 14, the active layer 15 including the quantum well, and the clad layer in this order from the semiconductor substrate 11 side. 16. A current confinement layer 23 before oxidation, a P-type DBR layer 24, and a P-type semiconductor contact layer 25 are provided. For the formation of the semiconductor laminated film 5, a technique such as MOCVD (Metal Organic Chemical Vapor Deposition) or MBE (Molecular Beam Epitaxy) is used. The thickness of the current confinement layer 23 before being oxidized is desirably 40 nm or less in order to suppress the influence of distortion due to volume shrinkage during the oxidation treatment.

Next, by performing dry etching using a resist pattern formed by photolithography as a mask, the semiconductor multilayer film 5 of FIG. 3 is processed into a mesa post shape (step S110). Thereby, the first step portion 41 is formed.

FIG. 4 is a cross-sectional view showing the semiconductor laminated film after processing the first step portion. It is desirable that the dimension of the upper surface 51 of the stepped portion 41 (the dimension of the top surface of the mesa post portion) when viewed in plan is as small as possible within a range that can be stably processed. For example, the upper surface 51 of the step portion 41 is formed in a circular shape having a diameter of 20 μm. The height of the step portion 41 (etching depth) is desirably the minimum depth necessary for exposing the end face of the current confinement layer 23. In the case of FIG. 4, the stepped portion 41 reaches from the upper surface of the semiconductor stacked film 5 (upper surface of the P-type semiconductor contact layer 25) to the middle of the N-type DBR layer 13.

Note that, as described above, the stepped portion 41 is configured by the top surface 51 and the bottom surface 53 that are two surfaces having different distances from the semiconductor substrate 11 and the end surface 52 that connects these two surfaces. The upper surface 51 and the bottom surface 53 extend in a direction along the semiconductor substrate 11, and the end surface 52 extends in a direction intersecting the semiconductor substrate 11. The upper surface 51 is located farther from the semiconductor substrate 11 than the bottom surface 53. The exposed surface of the N-type DBR layer 13 by etching corresponds to the bottom surface 53 of the step portion 41. The upper surface 51 of the step portion 41 corresponds to the upper surface of the P-type semiconductor contact layer 25. A surface connecting the upper surface 51 and the bottom surface 53 is referred to as an end surface 52 of the step portion 41.

Next, after processing the first step portion 41, the semiconductor substrate 11 with the semiconductor laminated film is heated to 400 ° C. or higher in a water vapor atmosphere. As a result, oxidation proceeds from the outer peripheral portion of the current confinement layer 23, and a current confinement structure (see FIG. 5) including the oxidized region 22 in the peripheral portion and the unoxidized region 21 in the central portion is formed (step S120). . The diameter of the unoxidized region is, for example, 10 μm.

Next, the second step portion 42 and the third step portion 43 are formed by performing dry etching using a resist pattern formed by photolithography as a mask (step S130). As a result, the side end portion 6 including the first to

third step portions

41, 42, 43 is formed in the semiconductor laminated film 5.

FIG. 5 is a cross-sectional view showing the semiconductor laminated film after the formation of the second and third step portions. Referring to FIG. 5, second step portion 42 reaches halfway of N-type semiconductor contact layer 12 from bottom surface 53 (exposed surface of N-type DBR layer 13 by etching) of first step portion 41. The exposed surface of the N-type semiconductor contact layer 12 by etching corresponds to the bottom surface 55 of the second step portion 42. The upper surface 53 of the second step portion 42 and the bottom surface 53 of the first step portion 41 are the same surface. A surface connecting the upper surface 53 and the bottom surface 55 of the second step portion 42 is referred to as an end surface 54 of the second step portion 42.

The third stepped portion 43 reaches the semiconductor substrate 11 from the bottom surface 55 of the second stepped portion 42 (exposed surface of the N-type semiconductor contact layer 12 by etching). The exposed surface of the semiconductor substrate 11 by etching corresponds to the bottom surface 57 of the third step portion 43. The upper surface 55 of the third step portion 43 and the bottom surface 55 of the second step portion 42 are the same surface. A surface connecting the upper surface 55 of the third step portion 43 and the bottom surface 57 of the third step portion 43 is referred to as an end surface 56 of the third step portion 43.

Since the bottom surface 57 of the third step portion 43 is an exposed surface of the semiconductor substrate 11 by etching, this bottom surface 57 is the interface between the semiconductor stacked film 5 and the semiconductor substrate 11 (the N-type semiconductor contact layer 12 and the semiconductor substrate 11). On the extended surface of the semiconductor substrate 11 or closer to the back surface of the semiconductor substrate 11 than the extended surface.

The first step portion 41 forms a first mesa structure, the second step portion 42 forms a second mesa structure, and the third step portion 43 forms a third mesa structure. You can also think that In this case, the second mesa structure (stepped portion 42) has a larger area on the top surface than the first mesa structure (stepped portion 41), and the first mesa structure is on the top surface of the second mesa structure. Are formed (in plan view, the first mesa structure is included in the second mesa structure). Similarly, the area of the top surface of the third mesa structure (stepped portion 43) is larger than that of the second mesa structure (stepped portion 42), and the second mesa structure is on the top surface of the third mesa structure. Formed (in plan view, the second mesa structure is included in the third mesa structure).

It is desirable that the end surface 52 of the first step portion 41 and the end surface 54 of the second step portion 42 are formed in a direction perpendicular to the semiconductor substrate 11. Thereby, the accuracy of the dimension of the first mesa and the accuracy of the dimension of the second mesa can be increased. In this specification, the term “perpendicular to the semiconductor substrate 11” does not mean strictly perpendicular to the semiconductor substrate 11, but refers to a range including manufacturing errors. The end surface 56 of the third step portion 43 may be inclined with respect to the semiconductor substrate 11.

When forming the second step portion 42, the surface of the N-type semiconductor contact layer is surely exposed without being affected by variations in etching rate (in-plane variation or process-to-process variation). The thickness of the N-type semiconductor contact layer 12 is desirably 3 μm or more.

Next, referring to FIG. 6, on the upper surface of the first step portion 41 (upper surface of the P-type semiconductor contact layer 25) and the bottom surface of the second step portion 42 (exposed surface of the N-type semiconductor contact layer 12), For example, the contact electrodes (the anode electrode 26 and the cathode electrode 27) are formed using photolithography and vapor deposition techniques (step S140). As the contact electrode, for example, a laminated film made of Ti (titanium), Pt (platinum), and Au (gold) can be used.

Next, the moisture-proof insulating protective film 30 is formed on the entire surface of the semiconductor substrate 11 (step S150). An inorganic insulating film such as silicon nitride or silicon oxide is used as the insulating protective film 30. The insulating protective film 30 is formed using a method such as CVD in order to improve the coverage of the step portion.

Subsequently, an opening is formed in the insulating protective film 30 above the contact electrodes (the anode electrode 26 and the cathode electrode 27). The opening of the insulating protective film 30 is formed by, for example, dry etching using a resist pattern as a mask by photolithography. FIG. 6 is a diagram showing a cross-sectional structure after formation of the contact electrode and the insulating protective film in the VCSEL manufacturing process.

Next, referring to FIG. 1, a photosensitive organic resin insulating layer 31 is formed so as to cover at least a part of the side end portions (

step portions

41, 42, 43) of the semiconductor laminated film 5 (steps). S160). The insulating layer 31 is formed, for example, by applying photosensitive polyimide to the entire surface of the semiconductor substrate 11 by spin coating, and then exposing and developing the pattern of the insulating layer 31. After development, the photosensitive polyimide pattern is cured.

By forming the insulating layer 31, the

step portions

41, 42, 43 are covered, and the surface from the surface of the P-type semiconductor contact layer 25 to the surface of the semiconductor substrate 11 is connected by the insulating layer 31 having a smooth planar or curved surface shape. Will be. The smooth surface of the insulating layer 31 is important for preventing the metal wiring 32 formed thereon from being disconnected.

Further, the film thickness of the photosensitive organic resin film formed by spin coating and the film thickness of the semiconductor multilayer film 5 are equal so that the step between the upper surface 61 of the insulating layer 31 and the upper surface of the semiconductor multilayer film 5 becomes small. It is desirable to form so that it becomes. “Equal film thickness” in this case does not mean that the film thicknesses are strictly the same, but means a range including manufacturing errors.

Next, the metal wiring 32 and the bonding pad 33 connected to the anode electrode 26 are formed by vapor deposition (step S170). For example, the metal wiring 32 and the bonding pad 33 are formed by lift-off using a resist pattern by photolithography. A metal wiring (not shown) connected to the cathode electrode 27 and a bonding pad (not shown) are also formed at the same time.

Next, the semiconductor substrate is separated into chips by a technique such as dicing (step S180). At this time, in order to suppress wear of the dicing blade and to prevent the impact of dicing from being transmitted to the VCSEL element portion, it is desirable to remove the insulating protective film 30 on the dicing line in advance. The removal of the insulating protective film 30 can be realized, for example, by performing an etching process using a resist pattern formed by photolithography as a mask.

[Modification]
Hereinafter, a plurality of modified examples of the VCSEL of FIG. 1 will be shown, and the advantages of the VCSEL structure of FIG. 1 will be described by comparing with these modified examples. In any of the following modifications, the bonding pad 33 electrically connected to the anode electrode 26 is formed on the main surface of the semiconductor substrate 11 with the insulating protective film 30 interposed. Therefore, as in the case of FIG. 1, the parasitic capacitance of the bonding pad 33 is reduced as compared with the case of the conventional structure (FIG. 2 of Patent Document 1).

FIG. 7 is a cross-sectional view schematically showing the structure of a VCSEL according to the first modification. The VCSEL 10A of FIG. 7 is different from the VCSEL 10 of FIG. 1 in that two

step portions

41A and 43 are provided at the side end of the semiconductor laminated film 5.

Specifically, the first step portion 41 </ b> A reaches from the upper surface of the semiconductor multilayer film 5 (upper surface of the P-type semiconductor contact layer 25) to the middle of the N-type semiconductor contact layer 12. The second step portion 43 reaches the semiconductor substrate 11 from the bottom surface of the first step portion 41A (the exposed surface of the N-type semiconductor contact layer 12). The first step portion 41A in FIG. 7 can be considered as a combination of the first step portion 41 and the second step portion 42 in FIG. The second step portion 43 in FIG. 7 corresponds to the third step portion 43 in FIG. Since the other points of FIG. 7 are the same as those of FIG. 1, the same or corresponding parts are denoted by the same reference numerals and description thereof will not be repeated.

In the case of the structure of the VCSEL 10A of FIG. 7 described above, the area of the upper surface of the first step portion 41 (the top surface of the first mesa structure) is suppressed in order to suppress the parasitic capacitance caused by the oxidized region 22 of the current confinement layer 23. Accordingly, the cross-sectional area of the N-type DBR layer 13 (the cross-sectional area in the substrate parallel direction) is also reduced. Then, the resistance value of the VCSEL element becomes too large, which is not preferable (the resistance value of the VCSEL element is mainly determined by the current flowing in the DBR layer in the vertical direction).

On the other hand, in the VCSEL 10 of FIG. 1, the cross-sectional area of the N-type DBR layer 13 is provided by providing three step portions (particularly the second step portion 42) at the side end portion of the semiconductor multilayer film 5. Is larger. As a result, the resistance value of the VCSEL element can be reduced.

FIG. 8 is a cross-sectional view schematically showing the structure of a VCSEL according to the second modification. The VCSEL 10B of FIG. 8 is different from the VCSEL 10 of FIG. 1 in that two

step portions

41 and 42A are provided at the side end of the semiconductor laminated film 5.

Specifically, the first step portion 41 reaches the middle of the N-type DBR layer 13 from the upper surface of the semiconductor stacked film 5 (upper surface of the P-type semiconductor contact layer 25). The second step portion 42A reaches the semiconductor substrate 11 from the bottom surface of the first step portion 41 (exposed surface of the N-type DBR layer 13). The first step 41 in FIG. 8 corresponds to the first step 41 in FIG. The second step portion 42A in FIG. 8 can be considered as a combination of the second step portion 42 and the third step portion 43 in FIG.

Further, the VCSEL 10B of FIG. 8 is provided with a groove 49 that reaches the N-type semiconductor contact layer 12 from the exposed surface of the N-type DBR layer 13 (the bottom surface of the first step portion 41). And different. In the VCSEL 10B of FIG. 8, the cathode electrode 27 is formed on the exposed surface of the N-type semiconductor contact layer 12, which is the bottom surface of the groove 49. Since the other points of FIG. 8 are the same as those of FIG. 1, the same or corresponding parts are denoted by the same reference numerals and description thereof will not be repeated.

In the case of the VCSEL 10B of FIG. 8, the resistance value of the element can be reduced to the same extent as in the case of FIG. Therefore, the high-speed modulation characteristics of the VCSEL element can be optimized to the same extent as in FIG. However, in the case of the VCSEL 10B of FIG. 8, it is necessary to form the groove 49 in order to expose the surface of the N-type semiconductor contact layer 12. On the other hand, in the VCSEL 10 of FIG. 1, the N-type semiconductor contact layer 12 is exposed when the second step portion 42 is formed, so that the cathode electrode 27 is formed on the exposed surface of the N-type semiconductor contact layer 12. Can be formed. Therefore, there is an advantage that it is not necessary to form the groove portion 49 as shown in FIG.

FIG. 9 is a table summarizing the advantages and disadvantages of the VCSEL device structure of FIGS. 1, 7, and 8 in a tabular format. FIG. 9 also shows a comparison with Patent Document 1 (WO2013 / 176201).

Referring to FIG. 9, regarding the parasitic capacitance of the bonding pad, in the case of FIG. 2 of Patent Document 1 (WO2013 / 176201), the pad electrode and the N-type DBR layer are opposed to each other with the insulating layer interposed therebetween. There is a problem of having parasitic capacitance. On the other hand, in any of FIGS. 1, 7, and 8 of the present application, the bonding pad 33 is formed on the main surface of the semiconductor substrate 11 with the insulating protective film 30 interposed therebetween. The parasitic capacitance of the pad 33 is smaller than that of the conventional structure (FIG. 2 of Patent Document 1).

Next, regarding the resistance of the VCSEL element, in the case of the structure of FIG. 7, since the cross-sectional area of the N-type DBR layer 13 is relatively small, the element resistance is large, which is not preferable. In the case of other structures (FIGS. 1 and 8 of the present application and FIG. 2 of Patent Document 1), by increasing the cross-sectional area of the N-type DBR layer 13, the element resistance can be reduced, which is more preferable.

For the above reason, in the case of FIG. 2 of Patent Document 1, it is difficult to widen the band because the high-speed modulation characteristics deteriorate, but in the case of FIGS. 1, 7, and 8 of the present application, it is possible to widen the band. It is. In particular, the structures shown in FIGS. 1 and 8 are optimal in that the element resistance can be adjusted while reducing the parasitic capacitance due to the oxidized region 22 of the current confinement layer 23.

On the other hand, when compared in terms of the height of the step portion provided at the side end portion of the semiconductor laminated film 5 (distance in the substrate vertical direction between the top surface and the bottom surface), the step in the case of FIG. The height of the part can be kept relatively low. On the other hand, in FIG. 7 and FIG. 8, since the number of steps of the step portion at the side end of the semiconductor laminated film 5 is two, the height of the step portion per step is high. In the case of the VCSEL in FIG. 1, the stepped portion has three steps, so that the height of the stepped portion is medium compared with the above case. If the height of the stepped portion is too high, the coverage of the stepped portion may not be sufficient when the insulating layer 31 is formed.

[effect]
As described above, according to the VCSEL of the first embodiment, the semiconductor laminated film 5 (the N-type semiconductor contact layer 12, the N-type DBR layer 13, the active layer in order from the substrate side) is formed on the main surface of the semi-insulating semiconductor substrate 11. Region 17, current confinement layer 23, P-type DBR layer 24, and P-type semiconductor contact layer 25) are formed. An insulating layer 31 made of an organic resin is formed so as to cover the side end portion of the semiconductor laminated film 5. Further, a bonding pad 33 is formed directly on the semiconductor substrate 11 or with an insulating protective film 30 interposed therebetween. The bonding pad 33 and the anode electrode 26 formed on the upper surface of the P-type semiconductor contact layer 25 are formed of an insulating layer. They are connected via metal wiring 32 formed on 31.

According to the above configuration, since the bonding pad 33 is not disposed so as to face the N-type DBR layer 13 or the N-type semiconductor contact layer 12, the parasitic capacitance caused by the bonding pad 33 can be reduced.

Furthermore, according to the VCSEL of the first embodiment, two or more step portions are formed at the side end portion of the semiconductor multilayer film 5. The first step portion 41 reaches from the upper surface of the semiconductor stacked film 5 to a position where the end face of the current confinement layer 23 is exposed, and the step portion 43 at the final stage reaches the semiconductor substrate 11.

According to the above configuration, by reducing the area of the upper surface of the first step portion 41 (the area of the top surface of the first mesa), the parasitic capacitance caused by the oxidized region 22 of the current confinement layer 23 is suppressed, The resistance value of the VCSEL element can be reduced by increasing the area of the upper surface of the second step portion (the area of the top surface of the second mesa).

In the above embodiment, an example in which the number of stepped portions is three steps (FIG. 1) and an example in which the number of stepped portions is two steps (FIGS. 7 and 8) are shown. The number of stages is not limited as long as it is two or more.

In the above embodiment, an N-type layer (N-type semiconductor contact layer 12 and N-type DBR layer 13) is provided at a position close to the substrate, and a P-type layer (P-type semiconductor contact layer 25, P-type is provided at a position away from the substrate. A type DBR layer 24) is provided. On the contrary, a P-type layer may be provided at a position close to the substrate, and an N-type layer may be provided at a position away from the substrate.

Furthermore, it goes without saying that the features described above can be arbitrarily combined.

<Second Embodiment>
In the second embodiment, an example of a specific planar layout of the VCSEL element described in the first embodiment will be described.

[VCSEL layout example]
FIG. 10 is a plan view illustrating a layout example of the VCSEL. 10, the anode electrode 26, the cathode electrode 27, the upper surface of the first step portion 41, the upper surface of the second step portion 42, the upper surface of the third step portion 43, the insulating layer 31, the

bonding pads

33 and 35, and the metal Each layout of the

wirings

32 and 34 is shown. For ease of illustration, the

bonding pads

33 and 35 and the

metal wirings

32 and 34 are hatched.

Referring to FIG. 10, the shape of the upper surface of the first step portion 41 is a circle having a diameter L1. In the present embodiment, the diameter L1 is 20 μm. A ring-shaped anode electrode 26 is provided on the upper surface of the first step portion 41.

The shape of the portion where the upper surface of the first step portion 41 is combined with the upper surface of the second step portion 42 is a substantially circular shape having a diameter L2. In the present embodiment, the diameter L2 is 56 μm. However, in order to save space, the outer shape of the portion close to the cathode electrode 27 is linear (therefore, the shape of the outer edge portion of the upper surface of the second step portion 42 is at least partially arc-shaped. Can be said).

As described above, the substantially circular shape allows the current to flow more uniformly and prevents current concentration. Furthermore, the stress concentration of the organic resin on the insulating layer 31 can be reduced.

The shape of the portion in which the upper surfaces of the first and

second step portions

41 and 42 are combined with the upper surface of the third step portion 43 is a shape obtained by connecting a circular shape and a substantially square shape. In the present embodiment, the diameter L3 of the circular portion is 76 μm.

The organic resin insulating layer 31 covers the entire upper surface of the second step portion 42, but covers only a part of the upper surface of the third step portion 43. Most of the substantially square portion of the upper surface of the third step portion 43, in particular, the portion where the cathode electrode 27 is provided is not covered with the insulating layer 31.

The

bonding pads

33 and 35 are provided in a portion where the semiconductor substrate is exposed, and the shape thereof is a substantially square shape with one side L8. In the present embodiment, the length of the side L8 is 65 μm.

The bonding pad 33 is connected to the anode electrode 26 through the metal wiring 32 having a width L4. In the present embodiment, the width L4 of the metal wiring 32 is 18 μm, and the length of the metal wiring 32 (from the outer edge portion of the first step portion 41 to the outer edge portion of the bonding pad 33) is 45 μm. The bonding pad 35 is connected to the cathode electrode 27 via the metal wiring 34.

FIG. 11 is a cross-sectional view taken along the cutting line XI-XI in FIG. Referring to FIGS. 10 and 11, in the case of the second embodiment, the end surfaces of the first and

second step portions

41 and 42 are perpendicular to the semiconductor substrate, but the end surface of the third step portion 43 is a semiconductor. Inclined with respect to the substrate.

Further, in the case of the second embodiment, the length L5 from the inner edge to the outer edge of the upper surface of the second step portion 42 is 18 μm. In a plan view, the length L6 from the end surface of the second step portion to the lower end of the end surface of the third step portion 43 is 5 μm. A length L7 from the lower end of the end surface of the third step portion 43 to the bonding pad 33 is 10 μm.

The height H1 of the first step portion 41 is 3.7 μm, and the total value H2 of the height of the first step portion 41 and the height of the second step portion 42 is 9.0 μm. The total height H3 of the first to

third step portions

41, 42, 43 is 13.0 μm.

[Resistance value of VCSEL]
FIG. 12 is a diagram illustrating a change in the resistance value of the VCSEL element when the size of the upper surface of the second step portion is changed. In FIG. 12, the horizontal axis represents the diameter of the outer edge portion of the upper surface of the second step portion 42 (corresponding to the diameter L2 in FIG. 10), and the vertical axis represents the resistance value of the VCSEL element.

In the case of the VCSEL element structure shown in FIGS. 10 and 11, the diameter L2 is 56 μm, and the area of the portion surrounded by the outer edge of the upper surface of the second step portion 42 is 2552 μm ² . As shown in FIG. 12, when the diameter L2 of the outer edge portion of the upper surface of the second step portion 42 is made smaller than the above value, the resistance value of the VCSEL element gradually increases. It can also be seen that if the area of the portion surrounded by the outer edge of the upper surface of the second stepped portion 43 is 2000 μm ² or more, the resistance value tends to saturate at a substantially minimum value. Therefore, the area of the portion surrounded by the outer edge of the upper surface of the second stepped portion 43 is desirably 2000 μm ² or more.

[Parasitic capacitance of VCSEL]
FIG. 13 is a diagram illustrating a change in parasitic capacitance when the size of the upper surface of the second step portion is changed. In FIG. 13, the horizontal axis represents the diameter of the outer edge portion of the upper surface of the second step portion 42 (corresponding to the diameter L <b> 2 in FIG. 10), and the vertical axis represents the value of the parasitic capacitance generated by the metal wiring 32 portion. Show. Specifically, in the VCSEL device structure shown in FIGS. 10 and 11, the capacitance (solid line in FIG. 12) of the portion facing the upper surface of the second step portion 42 is obtained by calculation. The width of the facing portion is L4, the length of the facing portion is (L2-L1) / 2, and the thickness of the insulating layer 31 is 3.7 μm. It is fixed at L1 = 20 μm and L4 = 18 μm (L2: variable). Furthermore, the dielectric constant of the insulating layer 31 is set to 3.0.

Further, in FIG. 13, the capacitance in the case of a conventional structure in which the metal wiring 32 and the bonding pad 33 are opposed to the N-type DBR layer is indicated by a broken line. In the calculation of the capacitance in the case of this conventional structure, the width L4 of the metal wiring 32 is 18 μm and the length is 45 μm. The area of the bonding pad 33 is 65 μm × 65 μm. Furthermore, the thickness of the insulating layer 31 at these opposing portions is set to 2.0 μm.

As shown in FIG. 13, even when the diameter L2 of the outer edge of the upper surface of the second step portion 42 is increased to 300 μm, the size of the parasitic capacitance is ½ that of the conventional structure. It can be seen that the structure can sufficiently reduce the parasitic capacitance.

The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

5 semiconductor laminated film, 11 semiconductor substrate, 12 N-type semiconductor contact layer, 13 N-type DBR layer, 14, 16 cladding layer, 15 active layer, 17 active region, 21 unoxidized region, 22 oxidized region, 23 current confinement layer, 24 P-type DBR layer, 25 P-type semiconductor contact layer, 26 anode electrode, 27 cathode electrode, 30 insulation protective film, 31 insulation layer, 32, 34 metal wiring, 33, 35 bonding pad, 41, 41A, 42, 42A, 43 steps, 49 grooves, 61 top surface of insulating layer, 62 end surface of insulating layer.

Claims

A vertical cavity surface emitting laser,
An insulating or semi-insulating substrate;
A semiconductor laminated film provided on the substrate,
The semiconductor multilayer film includes, in order from the substrate side, a first DBR (Distributed Bragg Reflector) layer, an active layer, and a second DBR layer,
The semiconductor laminated film further includes a gap between the first DBR layer and the active layer, a gap between the second DBR layer and the active layer, an inside of the first DBR layer, and the second DBR layer. Comprising at least one current confinement layer formed in at least one of the interiors of the DBR layer;
The vertical cavity surface emitting laser further comprises:
Covering at least a part of the side end of the semiconductor multilayer film, and comprising an insulating layer having an upper surface and an end surface; the upper surface of the insulating layer is connected to the upper surface of the semiconductor multilayer film and extends along the substrate; The end surface of the insulating layer is connected to the upper surface of the insulating layer and extends toward the substrate;
The vertical cavity surface emitting laser further comprises:
A first contact electrode electrically connected to the first DBR layer;
A second contact electrode provided on the upper surface of the semiconductor multilayer film;
A bonding pad provided directly or via an insulating film on the substrate;
A vertical cavity surface emitting laser provided on the upper surface and the end surface of the insulating layer, and comprising a metal wiring connecting the second contact electrode and the bonding pad.
The side end portion of the semiconductor laminated film has two or more step portions,
The first step portion reaches from the upper surface of the semiconductor multilayer film to a position where the end face of the at least one current confinement layer is exposed,
The step portion of the final stage reaches the substrate, and the bottom surface of the step portion of the final stage is on the extended surface of the interface between the semiconductor laminated film and the substrate, or the back surface of the substrate is more than the extended surface. The vertical cavity surface emitting laser according to claim 1, wherein the vertical cavity surface emitting laser is at a position close to.
The said side edge part of the said semiconductor laminated film has a three-step level | step difference part containing the said 1st level | step-difference part, a 2nd level | step-difference part, and the said 3rd level | step-difference part of the last stage of Claim 2. Vertical cavity surface emitting laser.
4. The vertical cavity surface emitting laser according to claim 3, wherein end surfaces of the first and second step portions are perpendicular to the substrate.
5. The vertical cavity surface emitting laser according to claim 3, wherein the shape of the outer edge portion of the upper surface of the second stepped portion is an arc shape at least partially when the substrate is viewed in plan.
The semiconductor stacked film further includes a first semiconductor contact layer between the substrate and the first DBR layer,
The second stepped portion reaches halfway through the first semiconductor contact layer,
6. The vertical cavity surface emitting laser according to claim 3, wherein the first contact electrode is provided on a bottom surface of the second step portion.
The vertical resonator surface according to any one of claims 3 to 6, wherein an area of a portion surrounded by an outer edge portion of the upper surface of the second stepped portion in a plan view is 2000 μm 2 or more. Light emitting laser.
The bonding pad is provided on the substrate with the insulating film interposed therebetween,
The insulating film covers a portion where the surface of the substrate is exposed, and an upper surface and a side edge of the semiconductor laminated film, except for the first and second contact electrodes, and the insulating film is inorganic. Formed by material,
The insulating layer according to any one of claims 1 to 7, wherein the insulating layer is formed of an organic resin material and covers at least a part of the side end portion of the semiconductor multilayer film with the insulating film interposed therebetween. Vertical cavity surface emitting laser.
An insulating or semi-insulating substrate;
A semiconductor multilayer film formed on the substrate,
The semiconductor laminated film includes, in order from the substrate, a first semiconductor contact layer, a first DBR (Distributed Bragg Reflector) layer, an active layer, and a second DBR layer,
The semiconductor laminated film further includes a gap between the first DBR layer and the active layer, a gap between the second DBR layer and the active layer, an inside of the first DBR layer, and the second DBR layer. Comprising at least one current confinement layer formed in at least one of the interiors of the DBR layer;
The side end portion of the semiconductor multilayer film has three steps.
The first step portion reaches the position where the end face of the at least one current confinement layer is exposed from the upper surface of the semiconductor multilayer film, but does not reach the first semiconductor contact layer,
The second step portion reaches from the bottom surface of the first step portion to the middle of the first semiconductor contact layer,
The third step portion reaches the substrate from the bottom surface of the second step portion,
A first contact electrode provided on a bottom surface of the second step portion;
A vertical cavity surface emitting laser comprising: a second contact electrode provided on an upper surface of the semiconductor multilayer film.