JP2009238815A - Surface light-emitting semiconductor laser and manufacturing method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a surface light-emitting semiconductor laser which can enhance optical output by reducing the element resistance. <P>SOLUTION: A VCSEL 10 comprises a substrate 12, an n-type lower DBR 14, an active region 16, and a p-type upper DBR 18. The lower DBR 14 further comprises an oxidized layer 40 which functions to confine light, and a current route layer 60 of high impurity concentration between the oxidized layer 40 and the active region 16. The upper DBR 18 has an oxidized layer 50 which functions to constrict a current. In addition to a current route K1 by a non-oxidized region 46 surrounded by an oxidized region 42, a current route K2 turning around the oxidized region 42 is formed for the carriers injected from a lower electrode 22. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a surface emitting semiconductor laser, and more particularly to a surface emitting semiconductor laser that performs fundamental transverse mode oscillation.

  As a light source for data communication using an optical fiber or the like, or as a light source for an information processing apparatus such as a copying machine, a surface-emitting semiconductor laser (Vertical-Cavity Surface-Emitting Laser diode) that can be easily formed into a two-dimensional array and consumes less power Hereinafter referred to as VCSEL).

  A typical VCSEL has a lower DBR, an active layer, and an upper DBR, and the light emitted from the active layer is oscillated by the vertical resonators of the lower DBR and the upper DBR. The VCSEL uses a current confinement layer or an optical confinement layer in order to efficiently oscillate laser light with a low threshold current. Patent Document 1 and Patent Document 2 disclose a VCSEL using one oxide layer as a current confinement and the other oxide layer as a higher-order mode control layer. Patent Document 3 discloses a VCSEL that enables high-order single mode oscillation by making a hole in the upper DBR.

Japanese Patent Laid-Open No. 2004-253408 JP 2005-259951 A JP 2006-41181 A

  When the VCSEL is operated in a single mode, that is, a basic transverse mode, it is desired to reduce the element resistance, suppress the heat generation associated therewith, and increase the light output. However, the current VCSEL still has a problem that the element resistance is still high and the maximum light output is insufficient.

  The present invention solves the above-described conventional problems, and an object thereof is to provide a surface-emitting type semiconductor laser capable of reducing element resistance and improving light output and a method for manufacturing the same.

  A surface-emitting type semiconductor laser according to the present invention includes a substrate, a first conductivity type first semiconductor multilayer film reflecting mirror formed on the substrate and including at least one first oxide layer, and a first semiconductor multilayer film. An active region formed on the film reflector, and a second semiconductor multilayer reflector of the second conductivity type formed on the active region and including at least one second oxide layer, The semiconductor multilayer mirror includes a high impurity concentration region having an impurity concentration higher than that of the other semiconductor multilayer film between the first oxide layer and the active region, and the first oxide layer includes an oxide region. The second oxide layer has a second conductive region surrounded by an oxide region, and the first oxide layer is more than the second oxide layer. Is also far from the center of the active region.

  Preferably, the first conductive region is equal to or larger than the second conductive region. Preferably, when the oscillation wavelength is λ, the thickness of the high impurity concentration region is larger than 1.5λ / n (n is the refractive index of the medium). The high impurity concentration region may be smaller than the reflectance of another semiconductor multilayer film of the first semiconductor multilayer film reflector.

  Preferably, a plurality of holes reaching the first oxide layer are formed in the first semiconductor multilayer mirror, and the first oxide layer is selectively oxidized from a side surface exposed by the plurality of holes. An oxidized region. Preferably, the first and second semiconductor multilayer film reflectors alternately include a low Al semiconductor layer having a low Al composition and a high Al semiconductor layer having a high Al composition, wherein the first and second oxide layers include the high Al semiconductor layer. A semiconductor layer having an Al composition larger than that of the Al semiconductor layer is included. Preferably, a mesa is formed on the substrate by etching of at least the second semiconductor multilayer reflector, and the second oxide layer includes an oxidized region selectively oxidized from the side surface of the mesa. Preferably, the first oxide layer and the second oxide layer have simultaneously oxidized regions. Preferably, an upper electrode is formed on the top of the mesa, and a lower electrode is formed on the back surface of the substrate. Further, an upper electrode may be formed on the top of the mesa, and a lower electrode electrically connected to the high impurity concentration region may be formed on the substrate.

  A surface-emitting type semiconductor laser according to the present invention includes a substrate, a first conductivity type first semiconductor multilayer film reflecting mirror formed on the substrate and including at least one first oxide layer, and a first semiconductor multilayer film. An active region formed on the film reflector, and a second semiconductor multilayer reflector of the first conductivity type formed on the active region and including at least one second oxide layer, The semiconductor multilayer film reflector includes a high impurity concentration region having an impurity concentration higher than that of the other semiconductor multilayer film between the first oxide layer and the active region, and the second semiconductor multilayer film reflector includes The first oxide layer includes a first conductive region surrounded by an oxide region, and the second oxide layer is a second conductive region surrounded by the oxide region. The first oxide layer is more active than the second oxide layer. Apart et al.

  A method for manufacturing a surface-emitting type semiconductor laser according to the present invention includes a first conductive type first semiconductor multilayer including at least one first oxide layer on a substrate and a high impurity concentration region on the first oxide layer. Laminating a semiconductor layer including a film reflector, an active region, a second semiconductor multilayer reflector of the second conductivity type including at least one second oxide layer, and exposing at least the second oxide layer; Etching the semiconductor layer to form a mesa on the substrate, and forming a plurality of holes having a depth reaching at least the first oxide layer in the first semiconductor multilayer reflector; The first oxide layer exposed on the side surface of the mesa and the second oxide layer exposed on the side surface of the hole are oxidized at the same time, and the first conductive region and the second region surrounded by the first oxide region Second surrounded by an oxidized region of Forming a conductive region in the first and second oxide layers; electrically connected to the first electrode and the second multilayer reflector that are electrically connected to the first multilayer reflector; Forming a second electrode.

  According to the present invention, the first and second oxide layers are formed so as to sandwich the active region, and the first and second oxide layers play the role of light confinement and current confinement, respectively. And the second oxide layer can be arranged at positions suitable for optical confinement and current confinement, thereby reducing the element resistance when oscillating in a single mode and improving the optical output. . Furthermore, the element resistance can be further reduced by interposing the high concentration impurity region between the first oxide layer and the active region.

  The best mode for carrying out the present invention will be described with reference to the drawings. Note that the following drawings are to explain the main configuration or features of the VCSEL, and do not necessarily show the final form of the VCSEL, and do not represent the actual VCSEL on the same scale.

  1A is a schematic plan view of a VCSEL according to a first embodiment of the present invention, and FIG. 1B is a schematic cross-sectional view taken along line A1-A1 of FIG. 1A. The VCSEL 10 according to the first embodiment is formed on an n-type substrate 12, an n-type distributed Bragg reflector (hereinafter referred to as DBR) 14 formed on the substrate 12, and a lower DBR 14. Active region 16, p-type upper DBR 18 formed on active region 16, annular upper electrode 20 formed on upper DBR 18, and lower electrode 22 formed on the back surface of substrate 12. Consists of. In FIG. 1A, the upper electrode 20 is hatched.

  The substrate 12 is made of, for example, n-type GaAs. A plurality of semiconductor layers are stacked on the substrate 12 by epitaxial growth to form the lower DBR 14, the active region 16, and the upper DBR 18. The lower DBR 14 and the upper DBR 18 are formed, for example, by stacking a plurality of pairs of a low refractive index AlGaAs layer having a high Al composition and a high refractive index AlGaAs layer having a low Al composition. The film thickness of each layer is 1 / 4λ (λ is an oscillation wavelength).

  A cylindrical post (or mesa) P is formed by etching the semiconductor layer from the upper DBR 18 to the lower DBR 14, and an upper electrode 20 having an emission window 24 formed in the center is formed on the top of the post P. The When a forward bias is applied to the upper electrode 20 and the lower electrode 22, the light emitted from the active region 16 is amplified by the vertical resonators of the lower DBR 14 and the upper DBR 18 and emitted from the emission window 24 as laser light.

  In a conventional typical selective oxidation type VCSEL, an oxide layer selectively oxidized in the post P is formed, and current confinement and optical confinement are performed by the oxide layer. On the other hand, in the VCSEL 10 of this embodiment, the oxide layer 40 for optical confinement is formed in the lower DBR 14 and the oxide layer 50 for current confinement is formed in the upper DBR 18.

  Four rectangular holes 30 are formed at positions that are rotationally symmetric with respect to the central axis C of the post P. As shown in FIG. 1A, the holes 30 are arranged at equal distances from the central axis C at equal intervals of 90 degrees. The distance from the central axis C to the side wall of the hole 30 is equal to or slightly larger than the radius of the post P. Since the hole 30 is used for selective oxidation of the oxide layer 40 as will be described later, the hole 30 has a depth that reaches at least the oxide layer 40. In addition, the hole 30 shown here is an example, Comprising: The number, a magnitude | size, a shape, etc. of the hole 30 can be changed suitably. For example, the holes 30 may be cylindrical and may be formed with eight intervals of 45 degrees.

As described above, the lower DBR 14 includes the oxide layer 40 that forms an oxide region for optical confinement, and the upper DBR 18 includes an oxide layer 50 that forms an oxide region for current confinement. For example, when the lower DBR ₁₄ has a pair of an n-type Al _x Ga _1-x As layer and an Al _y Ga _1-y As layer (X> Y), the oxide layer 40 is an n-type AlAs layer or an Al _z Ga layer. _1-z As layer (Z> X) is included. In this case, the Al _x Ga _1-x As layer may be replaced with an Al _z Ga _1-z As layer. Further, when the upper DBR 18 has a pair of a p-type Al _x Ga _1-x As layer and an Al _y Ga _1-y As layer (X> Y), the oxide layer 50 has a p-type AlAs layer or an Al _z Ga layer. _1-z As layer (Z> X) is included. In this case, the Al _x Ga _1-x As layer may be replaced with an Al _z Ga _1-z As layer.

  The oxide layer 40 has a side surface exposed by the hole 30 and is oxidized by a certain distance from this side surface. The oxidation of the oxide layer 40 isotropically spreads in the radial direction around the hole 30, and the stop position thereof is determined by controlling the oxidation time. As shown in FIG. 1A, the boundary 44 of the oxidized region 42 proceeding from the side surface of one hole 30 can be seen as being approximately concentric with the hole 30. The oxidized region 42 overlaps with the oxidized region 42 of another adjacent hole 30 to form a non-oxidized region 46 surrounded by the boundary 44 of the oxidized region 42. The oxidized region 42 is an electrically insulated region, and the non-oxidized region 46 is an electrically conductive region.

  The outline of the non-oxidized region 46 shown in FIG. 1A is a substantially polygonal shape determined by the four boundaries 44, and the approximate center of the non-oxidized region 46 coincides with the central axis C of the post P. The size of the non-oxidized region 46 is appropriately selected according to the lateral mode to be controlled and according to the distance from the active region 16. In other words, the farther the oxide layer 40 is from the active region 16, the larger the diameter of the non-oxidized region 46. Preferably, when the fundamental transverse mode oscillation is performed, the size of the non-oxidized region 46 is 5 μm or more. . A diameter of 5 μm or more can contribute to suppression of a decrease in light output and a reduction in resistance. In FIG. 1A, the non-oxidized region 46 has a quadrangular shape. However, if the number of holes is increased, the contour of the non-oxidized region 46 becomes a polygon and approaches a circular shape.

  The oxidized layer 50 is oxidized by a certain distance from the side surface of the post P, whereby an oxidized region 52 and a non-oxidized region 54 surrounded by the oxidized region 52 are formed. Oxidation of the oxide layer 50 proceeds from the side surface of the post P substantially isotropically toward the inside, so that the planar arrow view of the non-oxidized region 54 has a circular shape reflecting the outer shape of the post P. The center of the non-oxidized region 54 substantially coincides with the center axis C of the post P, and further substantially coincides with the center of the non-oxidized region 46 of the oxide layer 40 in the lower DBR 14. The oxidized region 52 is electrically insulating, and the non-oxidized region 54 is electrically conductive.

  The oxide layer 40 and the oxide layer 50 can be oxidized in a simultaneous oxidation process. If the thicknesses and Al compositions of the oxide layer 40 and the oxide layer 50 are equal, the oxidation rates of the oxide layer 40 and the oxide layer 50 can be made equal. If the side wall of the hole 30 is close to the side surface of the post P, the oxidized region 42 and the oxidized region 52 are made equal, and as a result, the non-oxidized region 46 and the non-oxidized region 54 are made to have substantially the same size. it can.

  On the other hand, when the oxidation rate of the oxide layer 50 is made faster than that of the oxide layer 40, the Al composition of the oxide layer 50 is made higher or thicker than the Al composition and film thickness of the oxide layer 40. Good. For example, when the Al composition of the oxide layer 40 is 98% and the film thickness is 30 nm, the Al composition of the oxide layer 50 is 99% to 100%, the film thickness is 30 nm or the Al composition is 98%, and the film thickness is 30 nm. Increased. Thereby, when the oxide layers 40 and 50 are oxidized simultaneously, the non-oxidized regions 44 and 52 having different sizes can be formed. In the case where the oxidation rate of the oxide layer 40 is made faster than that of the oxide layer 50, it can be performed in the same manner as described above.

  Preferably, since the non-oxidized region 46 functions exclusively as an optical confinement layer, the size of the non-oxidized region 46 can be set to the maximum size capable of oscillating the fundamental transverse mode. The size can be increased as the distance from the active region 16 increases. On the other hand, since the non-oxidized region 54 functions exclusively as a current confinement layer, the non-oxidized region 54 must be equal to or smaller than a size that enables fundamental transverse mode oscillation.

  The lower DBR 14 includes a current path layer 60 between the oxide layer 40 and the active region 16. The current path layer 60 is formed by laminating a high refractive index AlGaAs layer and a low refractive index AlGaAs layer in the same manner as the other lower DBRs 14, but the impurity concentration of these layers is higher than the impurity concentration of the other AlGaAs layers. Is also high. The film thickness of the current path layer 60 is preferably larger than 1.5λ / n (n is the refractive index of the medium) when the oscillation wavelength is λ. Further, the reflectivity of the current path layer 60 may be smaller than the reflectivity of the other lower DBR 14, and may be about 95% when the reflectivity of the other lower DBR 14 is 99% or more, for example. .

  When driving the VCSEL 10 shown in FIGS. 1A and 1B, the lower DBR 14 and the upper DBR 18 are forward-biased, and holes are injected from the upper electrode 20 and electrons are injected from the lower electrode 22. At this time, the current path from the lower electrode 22 to the active region 16 is a path that is not surrounded by the oxidized region 42 in addition to the path K1 that passes through the non-oxidized region (conductive region) 46 surrounded by the oxidized region 42, that is, Since the path K2 passing through the outside of the non-oxidized region 46 is formed, the resistance can be reduced. Further, since the current path layer 60 having a high impurity concentration is interposed between the oxide layer 40 and the active region 16, the resistance of the current path is further reduced. On the other hand, since the oxide layer 50 is disposed close to the active region 16, the holes injected from the upper electrode 20 can be effectively confined and the holes can be efficiently guided to the active region 16. . Thereby, the coupling probability of electron-hole pairs is increased, and the light output can be improved.

  As described above, according to the first embodiment, the oxide layer 40 that can function as a layer for optical confinement is formed in the n-type lower DBR 14, and the oxide layer 50 that can function as a current confinement layer is formed in the p-type upper DBR 18. Since the oxide layers 40 and 50 are formed at the optimum positions for optical confinement and current confinement, and the sizes of their non-oxidized regions can be individually set, oscillation is performed in the fundamental transverse mode. Element resistance is reduced, heat generation due to this is suppressed, and light output can be improved.

  Next, a second embodiment of the present invention is shown in FIG. In the VCSEL 10A according to the second embodiment, the lower electrode 22A is electrically connected to the current path layer 60 of the lower DBR 14. The other configuration is the same as that of the first embodiment. Although not shown here, the side wall and the bottom of the post P are covered with an insulating film, and the lower electrode 22A is connected to the current path layer 60 through a contact hole formed in the insulating film. In this case, the uppermost layer of the current path layer 60 has an impurity concentration such that it is in ohmic contact with the lower electrode 22A. Further, the semiconductor multilayer film that can be formed from the GaAs substrate 12 or the oxide layer 40 of the lower DBR 14 is not necessarily n-type, and may be semi-insulating without being doped with impurities.

  According to the second embodiment, as shown in FIG. 2, since the current path K3 of electrons injected from the lower electrode 22A passes only through the current path layer 60 having a high impurity concentration, the element resistance becomes very small. . Furthermore, the distance of the current path K3 from the lower electrode 22A to the active region 16 is shortened, which also contributes to the reduction in resistance.

  Next, a third embodiment of the present invention will be described. FIG. 3A is a plan view showing the characteristic part of the VCSEL according to the third embodiment, and FIG. 3B is a schematic cross-sectional view taken along the lines AC and BC in FIG. 3A. The third embodiment is a modification of the VCSEL of the first embodiment. That is, in the first embodiment, the cylindrical post P is formed by forming a continuous annular groove on the substrate. However, in the third embodiment, as shown in FIG. The post P is connected to the surrounding semiconductor region 74 by a bridge 72 by forming four arc-shaped grooves 70 thereon.

  By connecting the post P and the peripheral semiconductor region 74 with a plurality of bridges 72, the strength of the post P is improved. Then, protons are injected into a part of the bridge 72 and the surrounding semiconductor region 74 to form an insulating region 76, and the post P is electrically isolated from the surrounding semiconductor region 74. In FIG. 1A, the proton injection region is hatched for easy understanding. In the case of implanting proton ions, an insulating region can be formed in the upper DBR 18 by forming a mask in a portion other than the insulating region 76 and injecting protons with a constant energy.

  Next, a fourth embodiment of the present invention will be described. FIG. 4A is a plan view illustrating a characteristic portion of a VCSEL according to the fourth embodiment, and FIG. 4B is a schematic cross-sectional view taken along the lines AC and BC in FIG. 4A. The fourth embodiment is a further modification of the third embodiment, and does not form a groove for forming the post P on the substrate. Instead, protons are ion-implanted into the upper DBR. An annular insulating region 80 is formed. An etching process for forming the post P is not required, and there is no post for forming the light emitting portion. Therefore, it is possible to eliminate a failure such as a dropout of the post. In the fourth embodiment, the oxidized regions 40 and the oxidized regions 42 and 52 of the oxidized layer 50 are simultaneously formed by oxidation from the holes 30.

  In the above embodiment, the oxide layer 50 is formed in the upper DBR 18, but the current confinement may be performed by an insulating region by proton ion implantation without forming the oxide layer 50. In this case, as shown in FIG. 5, an insulating region 82 is formed by proton ion implantation so that a conductive region 84 having a size capable of operating in a single basic mode is formed.

  Next, a fifth embodiment of the present invention will be described. FIG. 6 is a schematic cross-sectional view of a VCSEL according to the fifth embodiment. The VCSEL 10D according to the fifth embodiment uses a tunnel junction. A p-type semiconductor has lower carrier mobility, higher electric resistance, and higher light absorption than an n-type semiconductor. For this reason, if the upper DBR 18 is formed of an n-type semiconductor, it is possible to reduce the resistance and increase the output.

  The fifth embodiment includes an n-type lower DBR 14, an active region 16, and an n-type upper DBR 18A. The n-type upper DBR 18A includes a p-type oxide layer 50 on the active region 16, and a p-type oxide on the p-type oxide layer 50. And a high impurity layer 90 of a high concentration impurity of the type. When the VCSEL 10D is driven, electrons injected from the lower electrode 22 pass through the junction between the p-type high impurity layer 90 and the n-type multilayer reflector by the tunnel effect and flow to the upper electrode 20.

  In the first to fifth embodiments described above, a single spot type VCSEL in which a single post P is formed on a substrate is illustrated, but a plurality of laser beams in which a plurality of posts P are formed on a substrate are used. A multi-spot type VCSEL that emits light may be used. Furthermore, although the said Example illustrated VCSEL using the AlGaAs type semiconductor layer, VCSEL using the other III-V group compound semiconductor may be sufficient. Further, the post P may have a rectangular shape in addition to the cylindrical shape.

Next, a manufacturing method of the VCSEL according to the first embodiment of the present invention will be described with reference to FIGS. As shown in FIG. 7A, Al _0.9 Ga _0.1 As and Al _0.15 Ga _0.85 As are formed on an n-type GaAs substrate 12 by metal organic chemical vapor deposition (MOCVD), and the thickness of each of them is 1 / of the wavelength in the medium. N-type lower DBR ¹⁴ having an carrier concentration of 1 × 10 ¹⁸ cm ⁻³ , an undoped lower Al _0.6 Ga _0.4 As spacer layer, and an undoped quantum well active layer (film thickness) The film thickness is composed of three 70 nm GaAs quantum well layers and four 50 nm thick Al _0.3 Ga _0.7 As barrier layers) and the undoped upper Al _0.6 Ga _0.4 As spacer layer. The carrier concentration obtained by alternately stacking 30 cycles of the active region 16 and Al _0.9 Ga _0.1 As and Al _0.15 Ga _0.85 As on the active region 16 so that each film thickness becomes ¼ of the wavelength in the medium is 1 × 10 ¹⁸ cm. ^-3 P-type upper DBRs 18 are sequentially stacked.

In the lower DBR 14, an oxide layer 40 made of n-type AlAs for confining light is formed as a transverse mode control layer. Further, an n-type current path layer 60 is formed on the oxide layer 40. The n-type current path layer 60 includes, for example, one or more pairs of Al _0.9 Ga _0.1 As and Al _0.15 Ga _0.85 As, and the carrier concentration thereof is higher than the impurity concentration of other DBR pairs. Further, an n-type GaAs buffer layer having a carrier concentration of 1 × 10 ¹⁸ cm ⁻³ may be formed between the substrate 12 and the lower DBR ¹⁴ .

An oxide layer 50 made of p-type AlAs is formed on the upper DBR 18. A P-type GaAs contact layer having a film thickness of about 20 nm and a carrier concentration of 1 × 10 ¹⁹ cm ⁻³ can be formed on the uppermost layer of the upper DBR 18.

  Next, as shown in FIG. 7B, a mask M1 is formed on the upper DBR 18 by a photolithography process, and etching is performed until the lower DBR 14 is reached by reactive ion etching. Thereby, a cylindrical post P is formed on the lower DBR 14. This etching may be performed until the active region 16 is reached, or a part of the lower DBR 14 may be etched without necessarily stopping at the surface of the lower DBR 14.

  As shown in FIG. 7C, a mask M2 is formed on the entire surface of the substrate except for the flow area where the holes 30 are formed. An opening corresponding to the hole 30 to be formed in the lower DBR 14 is formed in the mask M2. Reactive ion etching is performed using the mask M <b> 2 to form a plurality of holes 30 in the lower DBR 14. The hole 30 has a depth that reaches the oxide layer 40.

  Next, after removing the mask M2, the substrate is oxidized as shown in FIG. 8A. The oxide layer 50 in the post P is oxidized from the side surface of the post P, and the oxide layer 40 in the lower DBR 14 is oxidized from the side surface of the hole 30. As a result, a non-oxidized region 54 surrounded by the oxidized region 52 is formed in the post P, and a non-oxidized region 46 surrounded by the oxidized region 42 is formed in the lower DBR 14.

  Preferably, the oxidation rate of the oxide layer 40 is smaller than the oxidation rate of the oxide layer 50. For this reason, the thickness of the oxide layer 40 is made thinner than the semiconductor oxidized layer 50 or the Al composition of the oxide layer 40 is made smaller than the Al composition of the oxide layer 50. In the latter case, the oxide layer 40 can be an AlGaAs layer instead of AlAs.

  When proton ion implantation is performed as in the third and fourth embodiments, an ion implantation mask is formed after the step of FIG. 8B, and proton ions are implanted.

  Next, after forming an interlayer insulating film or the like (not shown), as shown in FIG. 8B, an upper electrode 20 made of Au is formed on the top of the post P, and a lower electrode 22 made of Au / Ge is formed on the back surface of the substrate. Is formed.

  Next, an optical device (module), a light irradiation device, a light transmission device, a transmission system, a light transmission device, and the like using the VCSEL of this embodiment will be described with reference to the drawings. FIG. 9A is a cross-sectional view showing a configuration of an optical device mounted with a VCSEL. The optical device 300 fixes the chip 310 on which the VCSEL is formed on the disk-shaped metal stem 330 via the conductive adhesive 320. Conductive leads 340 and 342 are inserted into through holes (not shown) of the stem 330, one lead 340 is electrically connected to the n-side electrode of the VCSEL, and the other lead 342 is a p-side electrode. Is electrically connected.

  A rectangular hollow cap 350 is fixed on the stem 330 including the chip 310, and a ball lens 360 is fixed in the central opening of the cap 350. The optical axis of the ball lens 360 is positioned so as to substantially coincide with the center of the chip 310. The distance between the chip 310 and the ball lens 360 is adjusted so that the ball lens 360 is included within the spread angle θ of the laser light from the chip 310. Further, a light receiving element or a temperature sensor for monitoring the light emission state of the VCSEL may be included in the cap.

  FIG. 8B is a diagram showing the configuration of another optical device. In the optical device 302 shown in FIG. 8B, a flat glass 362 is fixed in the central opening of the cap 350 instead of using the ball lens 360. The center of the flat glass 362 is positioned so as to substantially coincide with the center of the chip 310. The distance between the chip 310 and the flat glass 362 is adjusted so that the opening diameter of the flat glass 362 is equal to or greater than the spread angle θ of the laser light from the chip 310.

  FIG. 10 is a diagram illustrating an example of a light irradiation apparatus to which a VCSEL is applied as a light source. As shown in FIG. 9A or 9B, the light irradiation device 370 rotates at a constant speed, an optical device 300 or 302 mounted with a VCSEL, a collimator lens 372 that receives multi-beam laser light from the optical device 300 or 302, From the polygon mirror 374 that reflects the light beam from the collimator lens 372 at a certain divergence angle, the fθ lens 376 that receives the laser beam from the polygon mirror 374 and irradiates the reflection mirror 378, the line-shaped reflection mirror 378, and the reflection mirror 378 A photosensitive drum 380 that forms a latent image based on the reflected light. As described above, optical information processing such as a copying machine or a printer provided with an optical system for condensing the laser light from the VCSEL on the photosensitive drum and a mechanism for scanning the condensed laser light on the optical drum. It can be used as a light source for the apparatus.

  FIG. 11 is a cross-sectional view illustrating a configuration when the optical device illustrated in FIG. 9A is applied to an optical transmission device. The optical transmission device 400 includes a cylindrical casing 410 fixed to the stem 330, a sleeve 420 integrally formed on the end surface of the casing 410, a ferrule 430 held in the opening 422 of the sleeve 420, and a ferrule 430. The optical fiber 440 to be held is included. An end of the housing 410 is fixed to a flange 332 formed in the circumferential direction of the stem 330. The ferrule 430 is accurately positioned in the opening 422 of the sleeve 420 and the optical axis of the optical fiber 440 is aligned with the optical axis of the ball lens 360. The core wire of the optical fiber 440 is held in the through hole 432 of the ferrule 430.

  The laser light emitted from the surface of the chip 310 is collected by the ball lens 360, and the collected light is incident on the core wire of the optical fiber 440 and transmitted. Although the ball lens 360 is used in the above example, other lenses such as a biconvex lens and a plano-convex lens can be used. Further, the optical transmission device 400 may include a drive circuit for applying an electrical signal to the leads 340 and 342. Furthermore, the optical transmission device 400 may include a reception function for receiving an optical signal via the optical fiber 440.

  FIG. 12 is a diagram showing a configuration when the optical device shown in FIG. 9A is used in a spatial transmission system. The spatial transmission system 500 includes an optical device 300, a condenser lens 510, a diffusion plate 520, and a reflection mirror 530. The light condensed by the condenser lens 510 is reflected by the diffusion plate 520 through the opening 532 of the reflection mirror 530, and the reflected light is reflected toward the reflection mirror 530. The reflection mirror 530 reflects the reflected light in a predetermined direction and performs optical transmission.

  FIG. 13A is a diagram illustrating a configuration example of an optical transmission system using a VCSEL as a light source. The optical transmission system 600 receives a light source 610 including a chip 310 on which a VCSEL is formed, an optical system 620 that collects laser light emitted from the light source 610, and the laser light output from the optical system 620. A light receiving unit 630 and a control unit 640 that controls driving of the light source 610 are included. The control unit 640 supplies a drive pulse signal for driving the VCSEL to the light source 610. Light emitted from the light source 610 is transmitted to the light receiving unit 630 via an optical system 620 by an optical fiber, a reflection mirror for spatial transmission, or the like. The light receiving unit 630 detects the received light with a photodetector or the like. The light receiving unit 630 can control the operation of the control unit 640 (for example, the start timing of optical transmission) by the control signal 650.

  FIG. 13B is a diagram illustrating a general configuration of an optical transmission device used in the optical transmission system. The optical transmission device 700 includes a case 710, an optical signal transmission / reception connector joint 720, a light emitting / receiving element 730, an electric signal cable joint 740, a power input unit 750, an LED 760 indicating that an operation is in progress, an LED 770 indicating occurrence of an abnormality, and a DVI. It includes a connector 780 and has a transmission circuit board / reception circuit board inside.

  A video transmission system using the optical transmission apparatus 700 is shown in FIG. The video transmission system 800 uses the optical transmission device shown in FIG. 13B in order to transmit the video signal generated by the video signal generation device 810 to the image display device 820 such as a liquid crystal display. That is, the video transmission system 800 includes a video signal generation device 810, an image display device 820, a DVI electric cable 830, a transmission module 840, a reception module 850, a video signal transmission optical signal connector 860, an optical fiber 870, and a control signal electrical. A cable connector 880, a power adapter 890, and an electric cable 900 for DVI are included.

  The preferred embodiment of the present invention has been described in detail above, but the present invention is not limited to the specific embodiment, and various modifications can be made within the scope of the present invention described in the claims. Deformation / change is possible.

FIG. 1A is a schematic plan view of a VCSEL according to a first embodiment of the present invention, and FIG. 1B is a schematic cross-sectional view taken along line A1-A1 thereof. It is a general | schematic schematic sectional drawing of VCSEL which concerns on the 2nd Example of this invention. FIG. 3A is a plan view showing a characteristic portion of a VCSEL according to a third embodiment of the present invention, and FIG. 3B is a schematic cross-sectional view of the line AC and the line BC. FIG. 4A is a plan view showing a characteristic portion of a VCSEL according to the fourth embodiment of the present invention, and FIG. 4B is a schematic cross-sectional view taken along the lines AC and BC. It is sectional drawing of VCSEL which shows a 4th modification. It is a schematic sectional drawing of VCSEL which concerns on the 5th Example of this invention. It is sectional drawing which shows the manufacturing process of VCSEL of a 1st Example. It is sectional drawing which shows the manufacturing process of VCSEL of a 1st Example. It is a schematic sectional drawing which shows the structure of the module which mounted the optical component in VCSEL which concerns on a present Example. It is a figure which shows the structural example of the light source device which uses VCSEL. It is a schematic sectional drawing which shows the structure of the optical transmission device using the optical apparatus shown in FIG. It is a figure which shows a structure when the optical apparatus shown in FIG. 9 is used for a transmission system. FIG. 13A is a block diagram showing a configuration of the optical transmission system, and FIG. 13B is a diagram showing an external configuration of the optical transmission device. It is a figure which shows the video transmission system using the optical transmission apparatus of FIG. 13B.

Explanation of symbols

10: VCSEL 12: Substrate 14: Lower DBR 16: Active region 18: Upper DBR 20: Upper electrode 22: Lower electrode 24: Opening 30: Hole 40: Oxidized layer 42: Oxidized region 44: Oxidized region boundary 46: Non-oxidized Region 50: Oxidized layer 52: Oxidized region 54: Non-oxidized region 60: Current path layer 70: Groove 72: Bridge 74: Peripheral semiconductor regions 76, 80, 82: Insulating region (proton implantation region)
90: High impurity layer

Claims (20)

A substrate,
A first semiconductor multilayer reflector of a first conductivity type formed on a substrate and including at least one first oxide layer;
An active region formed on the first semiconductor multilayer mirror;
A second semiconductor multilayer reflector of a second conductivity type formed on the active region and including at least one second oxide layer;
The first semiconductor multilayer film reflector includes a high impurity concentration region having a higher impurity concentration than other semiconductor multilayer films between the first oxide layer and the active region,
The first oxide layer has a first conductive region surrounded by an oxide region;
The second oxide layer has a second conductive region surrounded by an oxide region;
The surface emitting semiconductor laser, wherein the first oxide layer is farther from the center of the active region than the second oxide layer. The surface emitting semiconductor laser according to claim 1, wherein the first conductive region is equal to or larger than the second conductive region. 2. The surface emitting semiconductor laser according to claim 1, wherein when the oscillation wavelength is λ, the thickness of the high impurity concentration region is larger than 1.5λ / n (n is a refractive index of the medium). 4. The surface emitting semiconductor laser according to claim 3, wherein the high impurity concentration region is smaller than a reflectance of another semiconductor multilayer film of the first semiconductor multilayer film reflector. A plurality of holes reaching the first oxide layer are formed in the first semiconductor multilayer mirror, and the first oxide layer is selectively oxidized from the side surface exposed by the plurality of holes. The surface emitting semiconductor laser according to claim 1, further comprising an oxidized region. The first and second semiconductor multilayer film reflectors alternately include a low Al semiconductor layer having a low Al composition and a high Al semiconductor layer having a high Al composition, and the first and second oxide layers comprise the high Al semiconductor layer. The surface emitting semiconductor laser according to claim 1, comprising a semiconductor layer having an Al composition larger than that of the semiconductor layer. The mesa is formed on the substrate by etching of at least a second semiconductor multilayer film reflecting mirror, and the second oxide layer includes an oxidized region selectively oxidized from a side surface of the mesa. The surface emitting semiconductor laser described. 8. The surface emitting semiconductor laser according to claim 7, wherein the first oxide layer and the second oxide layer have an oxidized region that is simultaneously oxidized. 8. The surface emitting semiconductor laser according to claim 7, wherein an upper electrode is formed on the top of the mesa and a lower electrode is formed on the back surface of the substrate. 8. The surface emitting semiconductor laser according to claim 7, wherein an upper electrode is formed on the top of the mesa, and a lower electrode electrically connected to the high impurity concentration region is formed on the substrate. 11. The surface-emitting type semiconductor laser according to claim 1, wherein the first conductivity type is an n-type, and the second conductivity type is a p-type. A substrate,
A first semiconductor multilayer reflector of a first conductivity type formed on a substrate and including at least one first oxide layer;
An active region formed on the first semiconductor multilayer mirror;
A second semiconductor multilayer reflector of a first conductivity type formed on the active region and including at least one second oxide layer;
The first semiconductor multilayer film reflector includes a high impurity concentration region having a higher impurity concentration than other semiconductor multilayer films between the first oxide layer and the active region,
The second semiconductor multilayer mirror includes a tunnel junction inside,
The first oxide layer has a first conductive region surrounded by an oxide region;
The second oxide layer has a second conductive region surrounded by an oxide region;
The surface emitting semiconductor laser, wherein the first oxide layer is farther from the active region than the second oxide layer. 13. The surface-emitting type semiconductor laser according to claim 1, an electrical connection terminal electrically connected to the surface-emitting type semiconductor laser, and an optical system that receives light emitted from the surface-emitting type semiconductor laser. And an optical device. A surface emitting semiconductor laser according to any one of claims 1 to 12, and an irradiating means for irradiating light emitted from the surface emitting semiconductor laser through an optical component including at least one of a lens and a mirror; A light irradiation device provided. An information processing apparatus comprising: the optical device according to claim 13; and a transmission unit that transmits light emitted from the surface-emitting type semiconductor laser. An optical transmission device comprising: the optical device according to claim 13; and a transmission unit that transmits light emitted from the surface-emitting type semiconductor laser. An optical space transmission device comprising: the optical device according to claim 13; and a transmission unit that spatially transmits light emitted from the surface-emitting type semiconductor laser. An optical transmission system comprising: the optical device according to claim 13; and a transmission unit that transmits light emitted from the surface-emitting type semiconductor laser. A method of manufacturing a surface emitting semiconductor laser,
A first semiconductor multilayer reflector of a first conductivity type including at least one first oxide layer and a high impurity concentration region on the first oxide layer on the substrate; an active region; and at least one second oxide. Laminating a semiconductor layer including a second semiconductor multilayer reflector of the second conductivity type including a layer;
Etching the semiconductor layer to expose at least the second oxide layer to form a mesa on the substrate;
Forming a plurality of holes with a depth reaching at least the first oxide layer in the first semiconductor multilayer mirror;
The first oxide layer exposed on the side surface of the mesa and the second oxide layer exposed on the side surface of the hole are simultaneously oxidized to form a first conductive region and a second region surrounded by the first oxide region. Forming a second conductive region surrounded by an oxide region in the first and second oxide layers;
Forming a first electrode electrically connected to the first multilayer reflector and a second electrode electrically connected to the second multilayer reflector;
Manufacturing method of surface emitting semiconductor laser having The manufacturing method according to claim 19, wherein the first oxide layer is further away from the center of the active region than the second oxide layer.

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