JP4921665B2 - プレディケーションを用いたマスクに基づくパックされたデータからのデータ要素の選択的書き込み - Google Patents

プレディケーションを用いたマスクに基づくパックされたデータからのデータ要素の選択的書き込み Download PDF

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Publication number
JP4921665B2
JP4921665B2 JP2001525517A JP2001525517A JP4921665B2 JP 4921665 B2 JP4921665 B2 JP 4921665B2 JP 2001525517 A JP2001525517 A JP 2001525517A JP 2001525517 A JP2001525517 A JP 2001525517A JP 4921665 B2 JP4921665 B2 JP 4921665B2
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data element
currently selected
data
packed
storage location
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JP2003510682A5 (enExample
JP2003510682A (ja
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ドュロン，カロル
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Intel Corp
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Intel Corp
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30018—Bit or string instructions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
    • G06F9/30038—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations using a mask
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30072—Arrangements for executing specific machine instructions to perform conditional operations, e.g. using predicates or guards
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30094—Condition code generation, e.g. Carry, Zero flag

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  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Executing Machine-Instructions (AREA)
  • Advance Control (AREA)
  • Devices For Executing Special Programs (AREA)
  • Pharmaceuticals Containing Other Organic And Inorganic Compounds (AREA)
JP2001525517A 1999-09-20 2000-08-29 プレディケーションを用いたマスクに基づくパックされたデータからのデータ要素の選択的書き込み Expired - Lifetime JP4921665B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/399,612 1999-09-20
US09/399,612 US6484255B1 (en) 1999-09-20 1999-09-20 Selective writing of data elements from packed data based upon a mask using predication
PCT/US2000/023721 WO2001022216A1 (en) 1999-09-20 2000-08-29 Selective writing of data elements from packed data based upon a mask using predication

Publications (3)

Publication Number Publication Date
JP2003510682A JP2003510682A (ja) 2003-03-18
JP2003510682A5 JP2003510682A5 (enExample) 2010-11-18
JP4921665B2 true JP4921665B2 (ja) 2012-04-25

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JP2001525517A Expired - Lifetime JP4921665B2 (ja) 1999-09-20 2000-08-29 プレディケーションを用いたマスクに基づくパックされたデータからのデータ要素の選択的書き込み

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US (2) US6484255B1 (enExample)
JP (1) JP4921665B2 (enExample)
CN (1) CN100440138C (enExample)
AU (1) AU6945400A (enExample)
DE (1) DE10085391T1 (enExample)
GB (1) GB2371135B (enExample)
HK (1) HK1044202B (enExample)
WO (1) WO2001022216A1 (enExample)

Families Citing this family (41)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6484255B1 (en) 1999-09-20 2002-11-19 Intel Corporation Selective writing of data elements from packed data based upon a mask using predication
JP3964593B2 (ja) * 2000-02-24 2007-08-22 富士通株式会社 半導体記憶装置
US7155601B2 (en) * 2001-02-14 2006-12-26 Intel Corporation Multi-element operand sub-portion shuffle instruction execution
US7861071B2 (en) * 2001-06-11 2010-12-28 Broadcom Corporation Conditional branch instruction capable of testing a plurality of indicators in a predicate register
US7624138B2 (en) 2001-10-29 2009-11-24 Intel Corporation Method and apparatus for efficient integer transform
US7685212B2 (en) * 2001-10-29 2010-03-23 Intel Corporation Fast full search motion estimation with SIMD merge instruction
US20040054877A1 (en) * 2001-10-29 2004-03-18 Macy William W. Method and apparatus for shuffling data
US7739319B2 (en) * 2001-10-29 2010-06-15 Intel Corporation Method and apparatus for parallel table lookup using SIMD instructions
US7631025B2 (en) * 2001-10-29 2009-12-08 Intel Corporation Method and apparatus for rearranging data between multiple registers
US7725521B2 (en) * 2001-10-29 2010-05-25 Intel Corporation Method and apparatus for computing matrix transformations
US7818356B2 (en) 2001-10-29 2010-10-19 Intel Corporation Bitstream buffer manipulation with a SIMD merge instruction
JP3773195B2 (ja) * 2002-10-25 2006-05-10 インターナショナル・ビジネス・マシーンズ・コーポレーション メモリモジュール、情報処理装置、メモリモジュールに関する初期設定方法、並びにプログラム
US7275149B1 (en) * 2003-03-25 2007-09-25 Verisilicon Holdings (Cayman Islands) Co. Ltd. System and method for evaluating and efficiently executing conditional instructions
US7395531B2 (en) 2004-06-07 2008-07-01 International Business Machines Corporation Framework for efficient code generation using loop peeling for SIMD loop code with multiple misaligned statements
US7478377B2 (en) 2004-06-07 2009-01-13 International Business Machines Corporation SIMD code generation in the presence of optimized misaligned data reorganization
US7367026B2 (en) * 2004-06-07 2008-04-29 International Business Machines Corporation Framework for integrated intra- and inter-loop aggregation of contiguous memory accesses for SIMD vectorization
US7475392B2 (en) * 2004-06-07 2009-01-06 International Business Machines Corporation SIMD code generation for loops with mixed data lengths
US8549501B2 (en) 2004-06-07 2013-10-01 International Business Machines Corporation Framework for generating mixed-mode operations in loop-level simdization
US7386842B2 (en) * 2004-06-07 2008-06-10 International Business Machines Corporation Efficient data reorganization to satisfy data alignment constraints
US7480787B1 (en) * 2006-01-27 2009-01-20 Sun Microsystems, Inc. Method and structure for pipelining of SIMD conditional moves
US8156310B2 (en) * 2006-09-11 2012-04-10 International Business Machines Corporation Method and apparatus for data stream alignment support
US20080071851A1 (en) * 2006-09-20 2008-03-20 Ronen Zohar Instruction and logic for performing a dot-product operation
US20080077772A1 (en) * 2006-09-22 2008-03-27 Ronen Zohar Method and apparatus for performing select operations
US9069547B2 (en) 2006-09-22 2015-06-30 Intel Corporation Instruction and logic for processing text strings
US8006114B2 (en) * 2007-03-09 2011-08-23 Analog Devices, Inc. Software programmable timing architecture
US9529592B2 (en) 2007-12-27 2016-12-27 Intel Corporation Vector mask memory access instructions to perform individual and sequential memory access operations if an exception occurs during a full width memory access operation
US8078836B2 (en) 2007-12-30 2011-12-13 Intel Corporation Vector shuffle instructions operating on multiple lanes each having a plurality of data elements using a common set of per-lane control bits
JP5930558B2 (ja) * 2011-09-26 2016-06-08 インテル・コーポレーション ストライド機能及びマスク機能を有するベクトルロード及びベクトルストアを提供する命令及びロジック
US10203954B2 (en) * 2011-11-25 2019-02-12 Intel Corporation Instruction and logic to provide conversions between a mask register and a general purpose register or memory
CN107220027A (zh) * 2011-12-23 2017-09-29 英特尔公司 用于执行掩码位压缩的系统、装置以及方法
WO2013095642A1 (en) * 2011-12-23 2013-06-27 Intel Corporation Systems, apparatuses, and methods for setting an output mask in a destination writemask register from a source write mask register using an input writemask and immediate
CN104185837B (zh) * 2011-12-23 2017-10-13 英特尔公司 在不同的粒度等级下广播数据值的指令执行单元
CN116414459A (zh) 2011-12-23 2023-07-11 英特尔公司 在不同的粒度水平下对数据值进行广播和掩码的指令执行
CN104025019B (zh) * 2011-12-23 2018-01-05 英特尔公司 用于执行双块绝对差求和的系统、装置和方法
CN104011652B (zh) * 2011-12-30 2017-10-27 英特尔公司 打包选择处理器、方法、系统和指令
US9218182B2 (en) * 2012-06-29 2015-12-22 Intel Corporation Systems, apparatuses, and methods for performing a shuffle and operation (shuffle-op)
US9304771B2 (en) * 2013-02-13 2016-04-05 International Business Machines Corporation Indirect instruction predication
US9990202B2 (en) * 2013-06-28 2018-06-05 Intel Corporation Packed data element predication processors, methods, systems, and instructions
US9612840B2 (en) * 2014-03-28 2017-04-04 Intel Corporation Method and apparatus for implementing a dynamic out-of-order processor pipeline
US10133570B2 (en) * 2014-09-19 2018-11-20 Intel Corporation Processors, methods, systems, and instructions to select and consolidate active data elements in a register under mask into a least significant portion of result, and to indicate a number of data elements consolidated
CN115904508B (zh) * 2023-01-06 2023-05-05 北京微核芯科技有限公司 乱序处理器中队列的队列项选择方法及装置

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6059469A (ja) * 1983-09-09 1985-04-05 Nec Corp ベクトル処理装置
JPH02204861A (ja) * 1989-02-02 1990-08-14 Nec Corp ベクトルデータ処理装置
JPH09198231A (ja) * 1996-01-22 1997-07-31 Nec Corp 演算処理装置
JPH1153189A (ja) * 1997-07-31 1999-02-26 Toshiba Corp 演算装置、演算方法及びコンピュータ読み取り可能な記録媒体
JP2002512398A (ja) * 1998-04-23 2002-04-23 インフィニオン テクノロジーズ ノース アメリカ コーポレイション パックデータ上でシフト演算を実行するための方法および装置

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4141005A (en) * 1976-11-11 1979-02-20 International Business Machines Corporation Data format converting apparatus for use in a digital data processor
US4217638A (en) * 1977-05-19 1980-08-12 Tokyo Shibaura Electric Co., Ltd. Data-processing apparatus and method
JPS59135548A (ja) 1983-01-22 1984-08-03 Toshiba Corp 演算装置
JPS6089274A (ja) * 1983-10-20 1985-05-20 Nec Corp ベクトルマスク制御システム
US5249266A (en) * 1985-10-22 1993-09-28 Texas Instruments Incorporated Data processing apparatus with self-emulation capability
US5423010A (en) * 1992-01-24 1995-06-06 C-Cube Microsystems Structure and method for packing and unpacking a stream of N-bit data to and from a stream of N-bit data words
JPH05250254A (ja) * 1992-03-04 1993-09-28 Nec Corp 記憶回路
US5467413A (en) * 1993-05-20 1995-11-14 Radius Inc. Method and apparatus for vector quantization for real-time playback on low cost personal computers
US5630075A (en) * 1993-12-30 1997-05-13 Intel Corporation Write combining buffer for sequentially addressed partial line operations originating from a single instruction
US5751982A (en) * 1995-03-31 1998-05-12 Apple Computer, Inc. Software emulation system with dynamic translation of emulated instructions for increased processing speed
US5680332A (en) 1995-10-30 1997-10-21 Motorola, Inc. Measurement of digital circuit simulation test coverage utilizing BDDs and state bins
US5784607A (en) * 1996-03-29 1998-07-21 Integrated Device Technology, Inc. Apparatus and method for exception handling during micro code string instructions
US5996066A (en) * 1996-10-10 1999-11-30 Sun Microsystems, Inc. Partitioned multiply and add/subtract instruction for CPU with integrated graphics functions
US5991531A (en) * 1997-02-24 1999-11-23 Samsung Electronics Co., Ltd. Scalable width vector processor architecture for efficient emulation
US6052769A (en) * 1998-03-31 2000-04-18 Intel Corporation Method and apparatus for moving select non-contiguous bytes of packed data in a single instruction
US6173393B1 (en) * 1998-03-31 2001-01-09 Intel Corporation System for writing select non-contiguous bytes of data with single instruction having operand identifying byte mask corresponding to respective blocks of packed data
US6067617A (en) 1998-04-07 2000-05-23 International Business Machines Corporation Specialized millicode instructions for packed decimal division
EP0967544B1 (en) 1998-06-25 2006-04-19 Texas Instruments Incorporated Digital signal processor for data having a large bit-length
US20020002666A1 (en) * 1998-10-12 2002-01-03 Carole Dulong Conditional operand selection using mask operations
US6484255B1 (en) * 1999-09-20 2002-11-19 Intel Corporation Selective writing of data elements from packed data based upon a mask using predication
US7480787B1 (en) * 2006-01-27 2009-01-20 Sun Microsystems, Inc. Method and structure for pipelining of SIMD conditional moves
US9529592B2 (en) * 2007-12-27 2016-12-27 Intel Corporation Vector mask memory access instructions to perform individual and sequential memory access operations if an exception occurs during a full width memory access operation

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6059469A (ja) * 1983-09-09 1985-04-05 Nec Corp ベクトル処理装置
JPH02204861A (ja) * 1989-02-02 1990-08-14 Nec Corp ベクトルデータ処理装置
JPH09198231A (ja) * 1996-01-22 1997-07-31 Nec Corp 演算処理装置
JPH1153189A (ja) * 1997-07-31 1999-02-26 Toshiba Corp 演算装置、演算方法及びコンピュータ読み取り可能な記録媒体
JP2002512398A (ja) * 1998-04-23 2002-04-23 インフィニオン テクノロジーズ ノース アメリカ コーポレイション パックデータ上でシフト演算を実行するための方法および装置

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Publication number Publication date
US6484255B1 (en) 2002-11-19
GB0208629D0 (en) 2002-05-22
HK1044202A1 (en) 2002-10-11
DE10085391T1 (de) 2002-12-12
GB2371135A (en) 2002-07-17
AU6945400A (en) 2001-04-24
CN100440138C (zh) 2008-12-03
JP2003510682A (ja) 2003-03-18
GB2371135B (en) 2004-03-31
HK1044202B (zh) 2004-12-03
CN1391668A (zh) 2003-01-15
WO2001022216A1 (en) 2001-03-29
US20030046520A1 (en) 2003-03-06

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