DE10085391T1 - Selektives Schreiben von Datenelementen aus gepackten Daten auf der Grundlage einer Maske unter Verwendung der Prädikation - Google Patents

Selektives Schreiben von Datenelementen aus gepackten Daten auf der Grundlage einer Maske unter Verwendung der Prädikation

Info

Publication number
DE10085391T1
DE10085391T1 DE10085391T DE10085391T DE10085391T1 DE 10085391 T1 DE10085391 T1 DE 10085391T1 DE 10085391 T DE10085391 T DE 10085391T DE 10085391 T DE10085391 T DE 10085391T DE 10085391 T1 DE10085391 T1 DE 10085391T1
Authority
DE
Germany
Prior art keywords
predication
mask
selectively write
data based
write data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
DE10085391T
Other languages
English (en)
Inventor
Carole Dulong
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of DE10085391T1 publication Critical patent/DE10085391T1/de
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30018—Bit or string instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
    • G06F9/30038—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations using a mask
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30072—Arrangements for executing specific machine instructions to perform conditional operations, e.g. using predicates or guards
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30094—Condition code generation, e.g. Carry, Zero flag

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Advance Control (AREA)
  • Executing Machine-Instructions (AREA)
  • Pharmaceuticals Containing Other Organic And Inorganic Compounds (AREA)
DE10085391T 1999-09-20 2000-08-29 Selektives Schreiben von Datenelementen aus gepackten Daten auf der Grundlage einer Maske unter Verwendung der Prädikation Ceased DE10085391T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/399,612 US6484255B1 (en) 1999-09-20 1999-09-20 Selective writing of data elements from packed data based upon a mask using predication
PCT/US2000/023721 WO2001022216A1 (en) 1999-09-20 2000-08-29 Selective writing of data elements from packed data based upon a mask using predication

Publications (1)

Publication Number Publication Date
DE10085391T1 true DE10085391T1 (de) 2002-12-12

Family

ID=23580223

Family Applications (1)

Application Number Title Priority Date Filing Date
DE10085391T Ceased DE10085391T1 (de) 1999-09-20 2000-08-29 Selektives Schreiben von Datenelementen aus gepackten Daten auf der Grundlage einer Maske unter Verwendung der Prädikation

Country Status (8)

Country Link
US (2) US6484255B1 (de)
JP (1) JP4921665B2 (de)
CN (1) CN100440138C (de)
AU (1) AU6945400A (de)
DE (1) DE10085391T1 (de)
GB (1) GB2371135B (de)
HK (1) HK1044202B (de)
WO (1) WO2001022216A1 (de)

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US7631025B2 (en) * 2001-10-29 2009-12-08 Intel Corporation Method and apparatus for rearranging data between multiple registers
US7624138B2 (en) 2001-10-29 2009-11-24 Intel Corporation Method and apparatus for efficient integer transform
US7818356B2 (en) 2001-10-29 2010-10-19 Intel Corporation Bitstream buffer manipulation with a SIMD merge instruction
US7685212B2 (en) * 2001-10-29 2010-03-23 Intel Corporation Fast full search motion estimation with SIMD merge instruction
US7725521B2 (en) * 2001-10-29 2010-05-25 Intel Corporation Method and apparatus for computing matrix transformations
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US7275149B1 (en) * 2003-03-25 2007-09-25 Verisilicon Holdings (Cayman Islands) Co. Ltd. System and method for evaluating and efficiently executing conditional instructions
US8549501B2 (en) 2004-06-07 2013-10-01 International Business Machines Corporation Framework for generating mixed-mode operations in loop-level simdization
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US8156310B2 (en) * 2006-09-11 2012-04-10 International Business Machines Corporation Method and apparatus for data stream alignment support
US20080071851A1 (en) * 2006-09-20 2008-03-20 Ronen Zohar Instruction and logic for performing a dot-product operation
US20080077772A1 (en) * 2006-09-22 2008-03-27 Ronen Zohar Method and apparatus for performing select operations
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US9529592B2 (en) 2007-12-27 2016-12-27 Intel Corporation Vector mask memory access instructions to perform individual and sequential memory access operations if an exception occurs during a full width memory access operation
US8078836B2 (en) 2007-12-30 2011-12-13 Intel Corporation Vector shuffle instructions operating on multiple lanes each having a plurality of data elements using a common set of per-lane control bits
CN103827815B (zh) * 2011-09-26 2017-11-28 英特尔公司 用于提供利用跨越和掩码功能的向量加载和存储的指令和逻辑
CN103988173B (zh) * 2011-11-25 2017-04-05 英特尔公司 用于提供掩码寄存器与通用寄存器或存储器之间的转换的指令和逻辑
CN104185837B (zh) * 2011-12-23 2017-10-13 英特尔公司 在不同的粒度等级下广播数据值的指令执行单元
US9354877B2 (en) * 2011-12-23 2016-05-31 Intel Corporation Systems, apparatuses, and methods for performing mask bit compression
CN104011650B (zh) * 2011-12-23 2017-09-19 英特尔公司 使用输入写掩码和立即数从源写掩码寄存器在目的地写掩码寄存器中设置输出掩码的系统、装置和方法
CN116414459A (zh) * 2011-12-23 2023-07-11 英特尔公司 在不同的粒度水平下对数据值进行广播和掩码的指令执行
US9582464B2 (en) * 2011-12-23 2017-02-28 Intel Corporation Systems, apparatuses, and methods for performing a double blocked sum of absolute differences
EP2798464B8 (de) 2011-12-30 2019-12-11 Intel Corporation Komprimierte drehprozessoren, verfahren, systeme und anweisungen
US9304771B2 (en) * 2013-02-13 2016-04-05 International Business Machines Corporation Indirect instruction predication
US9990202B2 (en) * 2013-06-28 2018-06-05 Intel Corporation Packed data element predication processors, methods, systems, and instructions
US9612840B2 (en) * 2014-03-28 2017-04-04 Intel Corporation Method and apparatus for implementing a dynamic out-of-order processor pipeline
US10133570B2 (en) * 2014-09-19 2018-11-20 Intel Corporation Processors, methods, systems, and instructions to select and consolidate active data elements in a register under mask into a least significant portion of result, and to indicate a number of data elements consolidated

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US7480787B1 (en) * 2006-01-27 2009-01-20 Sun Microsystems, Inc. Method and structure for pipelining of SIMD conditional moves
US9529592B2 (en) * 2007-12-27 2016-12-27 Intel Corporation Vector mask memory access instructions to perform individual and sequential memory access operations if an exception occurs during a full width memory access operation

Also Published As

Publication number Publication date
GB2371135B (en) 2004-03-31
CN1391668A (zh) 2003-01-15
CN100440138C (zh) 2008-12-03
GB2371135A (en) 2002-07-17
US20030046520A1 (en) 2003-03-06
HK1044202A1 (en) 2002-10-11
US6484255B1 (en) 2002-11-19
AU6945400A (en) 2001-04-24
HK1044202B (zh) 2004-12-03
JP2003510682A (ja) 2003-03-18
GB0208629D0 (en) 2002-05-22
JP4921665B2 (ja) 2012-04-25
WO2001022216A1 (en) 2001-03-29

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OP8 Request for examination as to paragraph 44 patent law
8131 Rejection