CN100440138C - 使用推测、基于掩码、由打包数据选择写入数据元素的方法、系统和处理器 - Google Patents

使用推测、基于掩码、由打包数据选择写入数据元素的方法、系统和处理器 Download PDF

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CN100440138C
CN100440138C CNB008159319A CN00815931A CN100440138C CN 100440138 C CN100440138 C CN 100440138C CN B008159319 A CNB008159319 A CN B008159319A CN 00815931 A CN00815931 A CN 00815931A CN 100440138 C CN100440138 C CN 100440138C
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data
data element
instructions
packed
operand
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CN1391668A (zh
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C·杜龙
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Intel Corp
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Intel Corp
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30018—Bit or string instructions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
    • G06F9/30038—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations using a mask
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30072—Arrangements for executing specific machine instructions to perform conditional operations, e.g. using predicates or guards
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30094—Condition code generation, e.g. Carry, Zero flag

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  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Executing Machine-Instructions (AREA)
  • Advance Control (AREA)
  • Devices For Executing Special Programs (AREA)
  • Pharmaceuticals Containing Other Organic And Inorganic Compounds (AREA)
CNB008159319A 1999-09-20 2000-08-29 使用推测、基于掩码、由打包数据选择写入数据元素的方法、系统和处理器 Expired - Lifetime CN100440138C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/399,612 1999-09-20
US09/399,612 US6484255B1 (en) 1999-09-20 1999-09-20 Selective writing of data elements from packed data based upon a mask using predication

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CN1391668A CN1391668A (zh) 2003-01-15
CN100440138C true CN100440138C (zh) 2008-12-03

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US (2) US6484255B1 (enExample)
JP (1) JP4921665B2 (enExample)
CN (1) CN100440138C (enExample)
AU (1) AU6945400A (enExample)
DE (1) DE10085391T1 (enExample)
GB (1) GB2371135B (enExample)
HK (1) HK1044202B (enExample)
WO (1) WO2001022216A1 (enExample)

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US7739319B2 (en) * 2001-10-29 2010-06-15 Intel Corporation Method and apparatus for parallel table lookup using SIMD instructions
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US7818356B2 (en) 2001-10-29 2010-10-19 Intel Corporation Bitstream buffer manipulation with a SIMD merge instruction
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US9529592B2 (en) 2007-12-27 2016-12-27 Intel Corporation Vector mask memory access instructions to perform individual and sequential memory access operations if an exception occurs during a full width memory access operation
US8078836B2 (en) 2007-12-30 2011-12-13 Intel Corporation Vector shuffle instructions operating on multiple lanes each having a plurality of data elements using a common set of per-lane control bits
JP5930558B2 (ja) * 2011-09-26 2016-06-08 インテル・コーポレーション ストライド機能及びマスク機能を有するベクトルロード及びベクトルストアを提供する命令及びロジック
US10203954B2 (en) * 2011-11-25 2019-02-12 Intel Corporation Instruction and logic to provide conversions between a mask register and a general purpose register or memory
CN107220027A (zh) * 2011-12-23 2017-09-29 英特尔公司 用于执行掩码位压缩的系统、装置以及方法
WO2013095642A1 (en) * 2011-12-23 2013-06-27 Intel Corporation Systems, apparatuses, and methods for setting an output mask in a destination writemask register from a source write mask register using an input writemask and immediate
CN104185837B (zh) * 2011-12-23 2017-10-13 英特尔公司 在不同的粒度等级下广播数据值的指令执行单元
CN116414459A (zh) 2011-12-23 2023-07-11 英特尔公司 在不同的粒度水平下对数据值进行广播和掩码的指令执行
CN104025019B (zh) * 2011-12-23 2018-01-05 英特尔公司 用于执行双块绝对差求和的系统、装置和方法
CN104011652B (zh) * 2011-12-30 2017-10-27 英特尔公司 打包选择处理器、方法、系统和指令
US9218182B2 (en) * 2012-06-29 2015-12-22 Intel Corporation Systems, apparatuses, and methods for performing a shuffle and operation (shuffle-op)
US9304771B2 (en) * 2013-02-13 2016-04-05 International Business Machines Corporation Indirect instruction predication
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US9612840B2 (en) * 2014-03-28 2017-04-04 Intel Corporation Method and apparatus for implementing a dynamic out-of-order processor pipeline
US10133570B2 (en) * 2014-09-19 2018-11-20 Intel Corporation Processors, methods, systems, and instructions to select and consolidate active data elements in a register under mask into a least significant portion of result, and to indicate a number of data elements consolidated
CN115904508B (zh) * 2023-01-06 2023-05-05 北京微核芯科技有限公司 乱序处理器中队列的队列项选择方法及装置

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US6484255B1 (en) 2002-11-19
GB0208629D0 (en) 2002-05-22
HK1044202A1 (en) 2002-10-11
DE10085391T1 (de) 2002-12-12
GB2371135A (en) 2002-07-17
AU6945400A (en) 2001-04-24
JP2003510682A (ja) 2003-03-18
GB2371135B (en) 2004-03-31
JP4921665B2 (ja) 2012-04-25
HK1044202B (zh) 2004-12-03
CN1391668A (zh) 2003-01-15
WO2001022216A1 (en) 2001-03-29
US20030046520A1 (en) 2003-03-06

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