JP4919087B2 - ビアに相互接続を形成する方法及び該相互接続を含むマイクロエレクトロニック・ワークピース - Google Patents
ビアに相互接続を形成する方法及び該相互接続を含むマイクロエレクトロニック・ワークピース Download PDFInfo
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以下の開示は、ブラインドビア又は他の種類の孔に相互接続を形成する方法と、そのような相互接続を有するマイクロエレクトロニック・ワークピースとのいくつかの実施形態を説明する。ブラインドビアは、導電要素の接触面まで延び、相互接続は、導電要素を係合して導電要素をワークピースの異なるレベルの他の形態に電気的に連結する。以下に説明するように、本発明の多くの実施形態は、ブラインドビアを効率的に形成し、また、空隙を軽減する方法でブラインドビアを導電材料で充填する。
図1A−1Eは、本発明の実施形態によるワークピース10へのブラインドビアと相互接続の形成を示している。図1Aは、ブラインドビアと相互接続が形成される前の初期段階におけるワークピース10を示している。ワークピース10は、第1の側面14と第2の側面16とを有する基板12を含むことができる。ワークピース10はまた、基板12の第2の側面16に複数のマイクロエレクトロニック・ダイ20を含むことができる。各マイクロエレクトロニック・ダイは、集積回路22と、集積回路22と作動的に連結された複数の導電要素24とを含むことができる。図1Aに示す導電要素24は、接触面26を含む第2の側面16に露出されなかった結合パッドなどの内部形態である。図1Aに示す実施形態では、接触面26は、それらがワークピース10の外部にはない点で、ブラインド又は埋め込まれた表面である。
図2Aと2Bは、第2の開口部40を形成するための精密除去段階(図1C)の一実施形態を示す概略断面図である。図1A−2Bにおいて、同じ参照番号は同じ構成要素を指している。図2Aに関して、この段階は、レーザビームLを導電要素24と整列させる段階、及びレーザビームLを第1の孔30を通るように向ける段階を含む。図2Bに示すように、レーザビームLは、第1の開口部30の終端面32で始まって導電要素24との接触面26で終わるまで基板を除去する。この処理は、次に、各導電要素24において繰り返されて複数の開口部40を形成する。接触面26と終端面32の間の距離が接触面26と第1の側面14の間の距離よりも相当に短いために、第2の開口部40は、従来の方法よりも遥かに高い精度で形成することができる。図1Dと1Eを参照して上述したように、第2の開口部40は、導電材料で充填することができ、ワークピース10を薄くして第2の開口部に相互接続を形成することができる。
導電要素24の接触面26を露出させるために第2の開口部40を形成した後で、図1D及び1Eを参照して上述したように導電材料で第2の開口部40が充填され、ワークピースを薄くして相互接続を構成する。図5A−7Cは、第2の開口部40を充填する段階とワークピース10を薄くする段階のいくつかの実施形態を示している。
26 導電要素の接触面
30 第1の開口部、空洞
40 第2の開口部
Claims (29)
- マイクロエレクトロニック・ワークピースの導電要素が有する該マイクロエレクトロニック・ワークピースの外面上に露出していない接触面であるブラインド接触面に係合した相互接続を形成する方法であって、
第1の幅を有し、前記マイクロエレクトロニック・ワークピースの第1の外部側面から該マイクロエレクトロニック・ワークピースの中間レベルまで延びる深さを有する空洞を形成する段階と、
前記第1の幅よりも狭い第2の幅を有し、前記空洞の前記中間レベルから前記ブラインド接触面まで延びた、該ブラインド接触面で一端が閉じられている孔であるブラインドビアを形成する段階と、
前記ブラインドビアを導電材料で充填する段階と、
前記空洞が除去されるまで前記第1の外部側面から前記マイクロエレクトロニック・ワークピースを薄くする段階と、
を含むことを特徴とする方法。 - 前記空洞を形成する段階は、溝を該溝の一部分が前記導電要素と整列するように前記マイクロエレクトロニック・ワークピースの中に切り込む段階を含むことを特徴とする請求項1に記載の方法。
- 前記空洞を形成する段階は、孔を該孔の一部分が前記導電要素と整列するように前記マイクロエレクトロニック・ワークピースの中に切り込む段階を含むことを特徴とする請求項1に記載の方法。
- 前記マイクロエレクトロニック・ワークピースは、前記ブラインド接触面を備えた複数の導電要素を有する複数のダイを含み、
前記空洞を形成する段階は、複数の凹部を前記マイクロエレクトロニック・ワークピースの前記外部側面に該凹部の一部分が前記ブラインド接触面の1つ又はそれよりも多くと整列するように形成する段階を含む、
ことを特徴とする請求項1に記載の方法。 - 前記凹部は、前記マイクロエレクトロニック・ワークピース内の前記外部側面から前記中間レベルまでの深さを有する溝及び/又は孔であることを特徴とする請求項4に記載の方法。
- 前記凹部を形成する段階は、前記マイクロエレクトロニック・ワークピース内に溝及び/又は孔をレーザで切り込む段階を含むことを特徴とする請求項4に記載の方法。
- 前記凹部を形成する段階は、研磨ディスクを使用して前記マイクロエレクトロニック・ワークピース内に溝を切り込む段階を含むことを特徴とする請求項4に記載の方法。
- 前記凹部を形成する段階は、研磨先端付きルータを使用して前記マイクロエレクトロニック・ワークピース内に溝及び/又は孔を切り込む段階を含むことを特徴とする請求項4に記載の方法。
- 前記凹部を形成する段階は、前記マイクロエレクトロニック・ワークピース内に溝及び/又は孔をエッチングする段階を含むことを特徴とする請求項4に記載の方法。
- 前記マイクロエレクトロニック・ワークピース内に溝及び/又は孔をエッチングする段階は、該マイクロエレクトロニック・ワークピースの前記外部側面上にレジストの層をパターン化する段階と該マイクロエレクトロニック・ワークピースを等方性エッチングする段階とを含むことを特徴とする請求項9に記載の方法。
- 前記ブラインドビアを構成する段階は、前記第2の幅と前記空洞の前記中間レベルから前記ブラインド接触面までの第2の深さとを有する孔をエッチングする段階を含むことを特徴とする請求項1に記載の方法。
- 前記孔をエッチングする段階は、単相エッチング手順を含むことを特徴とする請求項11に記載の方法。
- 前記孔をエッチングする段階は、第1のエッチング液が前記空洞の前記中間レベルから前記ブラインド接触面上の酸化物までエッチングする第1の相と、第2のエッチング液が該酸化物から該ブラインド接触面までエッチングする第2の相とを含む2相エッチング手順を含むことを特徴とする請求項11に記載の方法。
- 前記ブラインドビアを構成する段階は、前記第2の幅を有する孔を前記空洞の前記中間レベルから前記ブラインド接触面までレーザで穿孔する段階を含むことを特徴とする請求項1に記載の方法。
- 前記ブラインドビアを導電材料で充填する段階は、該導電材料を該ブラインドビアの中にメッキする段階を含むことを特徴とする請求項1に記載の方法。
- 前記導電材料を前記ブラインドビアの中にメッキする段階は、
前記マイクロエレクトロニック・ワークピース上及び前記ブラインドビア内にシード層を堆積させる段階と、
メッキ溶液の存在下で前記シード層に電位を印加する段階と、
を含む、
ことを特徴とする請求項15に記載の方法。 - 前記導電要素は、前記マイクロエレクトロニック・ワークピースの反対側の外部側面上に露出され、
前記導電材料を前記ブラインドビアの中にメッキする段階は、
前記導電要素を前記マイクロエレクトロニック・ワークピースの前記反対側の外部側面からの電気接点と係合させる
段階と、
メッキ溶液の存在下で前記電気接点を通じて前記導電要素に電位を印加し、前記ブラインドビア内で該導電要素の前記ブラインド接触面上への下から上のメッキを引き起こす段階と、
を含む、
ことを特徴とする請求項15に記載の方法。 - 前記導電材料を前記ブラインドビアの中にメッキする段階は、該ブラインドビア内で該導電要素の前記ブラインド接触面上に材料を無電解メッキする段階を含むことを特徴とする請求項15に記載の方法。
- 前記導電材料を前記ブラインドビアの中にメッキする段階は、前記ブラインド接触面上に亜鉛の層を形成する亜鉛溶液で該ブラインド接触面を洗浄する段階と、該ブラインドビア内で該亜鉛の層上にニッケルを無電解メッキする段階とを含むことを特徴とする請求項15に記載の方法。
- マイクロエレクトロニック・ワークピースの導電要素が有する該マイクロエレクトロニック・ワークピースの外面上に露出していない接触面であるブラインド接触面に係合した相互接続を形成する方法であって、
第1の幅を有し、前記マイクロエレクトロニック・ワークピースの外面から該マイクロエレクトロニック・ワークピース内の中間の深さまで延びる第1の開口部を形成する段階と、
前記第1の開口部の前記中間の深さから前記ブラインド接触面まで延びて前記第1の幅よりも狭い第2の幅を有する第2の開口部を形成する段階と、
導電材料で前記第2の開口部を充填する段階と、
前記マイクロエレクトロニック・ワークピースの前記外面から材料を除去して、少なくとも前記第1の開口部の前記中間の深さに表面を形成する段階と、
を含むことを特徴とする方法。 - 前記第1の開口部を形成する段階は、前記外面の中に空洞を形成する段階を含み、前記第2の開口部を形成する段階は、前記ブラインド接触面で一端が閉じられている孔であるブラインドビアを構成する段階を含むことを特徴とする請求項20に記載の方法。
- 前記空洞を形成する段階は、溝を該溝の一部分が前記導電要素と整列するように前記マイクロエレクトロニック・ワークピースの中に切り込む段階を含み、
前記ブラインドビアを構成する段階は、第1のエッチング液が前記溝から前記ブラインド接触面上の酸化物までエッチングする第1の相と、第2のエッチング液が該酸化物から該ブラインド接触面までエッチングする第2の相とを含む2相エッチング手順を含み、
前記第2の開口部を導電材料で充填する段階は、該導電材料を前記ブラインドビアの中にメッキする段階を含む、
ことを特徴とする請求項21に記載の方法。 - 前記空洞を形成する段階は、溝を該溝の一部分が前記導電要素と整列するように前記マイクロエレクトロニック・ワークピースの中に切り込む段階を含み、
前記ブラインドビアを構成する段階は、前記溝から前記ブラインド接触面までエッチングする段階を含み、
前記第2の開口部を導電材料で充填する段階は、下から上へのメッキ処理を使用して該導電材料を前記ブラインドビアの中にメッキする段階を含む、
ことを特徴とする請求項21に記載の方法。 - 前記空洞を形成する段階は、レーザ及び/又は研磨ツールを使用して溝を該溝の一部分が前記導電要素と整列するように前記マイクロエレクトロニック・ワークピースの中に切り込む段階を含み、
前記ブラインドビアを構成する段階は、前記溝から前記ブラインド接触面までエッチングする段階を含み、
前記第2の開口部を導電材料で充填する段階は、該導電材料を前記ブラインドビアの中にメッキする段階を含む、
ことを特徴とする請求項21に記載の方法。 - 前記空洞を形成する段階は、レーザ及び/又は研磨剤を使用して溝を該溝の一部分が前記導電要素と整列するように前記マイクロエレクトロニック・ワークピースの中に切り込む段階を含み、
前記ブラインドビアを構成する段階は、第1のエッチング液が前記溝から前記ブラインド接触面上の酸化物までエッチングする第1の相と、第2のエッチング液が該酸化物から該ブラインド接触面までエッチングする第2の相とを含む2相エッチング手順を含み、
前記第2の開口部を導電材料で充填する段階は、下から上へのメッキ処理を使用して該導電材料を前記ブラインドビアの中にメッキする段階を含む、
ことを特徴とする請求項21に記載の方法。 - 前記空洞を形成する段階は、孔を該孔の一部分が前記導電要素と整列するように前記マイクロエレクトロニック・ワークピースの中に切り込む段階を含み、
前記ブラインドビアを構成する段階は、第1のエッチング液が前記孔から前記ブラインド接触面上の酸化物までエッチングする第1の相と、第2のエッチング液が該酸化物から該ブラインド接触面までエッチングする第2の相とを含む2相エッチング手順を含み、
前記第2の開口部を導電材料で充填する段階は、該導電材料を前記ブラインドビアの中にメッキする段階を含む、
ことを特徴とする請求項21に記載の方法。 - 前記空洞を形成する段階は、孔を該孔の一部分が前記導電要素と整列するように前記マイクロエレクトロニック・ワークピースの中に切り込む段階を含み、
前記ブラインドビアを構成する段階は、前記孔から前記ブラインド接触面までエッチングする段階を含み、
前記第2の開口部を導電材料で充填する段階は、下から上へのメッキ処理を使用して該導電材料を前記ブラインドビアの中にメッキする段階を含む、
ことを特徴とする請求項21に記載の方法。 - 前記空洞を形成する段階は、レーザ及び/又は研磨ツールを使用して孔を該孔の一部分が前記導電要素と整列するように前記マイクロエレクトロニック・ワークピースの中に切り込む段階を含み、
前記ブラインドビアを構成する段階は、前記孔から前記ブラインド接触面までエッチングする段階を含み、
前記第2の開口部を導電材料で充填する段階は、該導電材料を前記ブラインドビアの中にメッキする段階を含む、
ことを特徴とする請求項21に記載の方法。 - 前記空洞を形成する段階は、レーザ及び/又は研磨剤を使用して孔を該孔の一部分が前記導電要素と整列するように前記マイクロエレクトロニック・ワークピースの中に切り込む段階を含み、
前記ブラインドビアを構成する段階は、第1のエッチング液が前記孔から前記ブラインド接触面上の酸化物までエッチングする第1の相と、第2のエッチング液が該酸化物から該ブラインド接触面までエッチングする第2の相とを含む2相エッチング手順を含み、
前記第2の開口部を導電材料で充填する段階は、下から上へのメッキ処理を使用して該導電材料を前記ブラインドビアの中にメッキする段階を含む、
ことを特徴とする請求項21に記載の方法。
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| PCT/US2005/028149 WO2006023318A1 (en) | 2004-08-24 | 2005-08-08 | Methods for forming interconnects in vias and microelectronic workpieces including such interconnects |
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| US8084866B2 (en) | 2003-12-10 | 2011-12-27 | Micron Technology, Inc. | Microelectronic devices and methods for filling vias in microelectronic devices |
| US20050247894A1 (en) | 2004-05-05 | 2005-11-10 | Watkins Charles M | Systems and methods for forming apertures in microfeature workpieces |
| US7232754B2 (en) | 2004-06-29 | 2007-06-19 | Micron Technology, Inc. | Microelectronic devices and methods for forming interconnects in microelectronic devices |
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- 2004-08-24 US US10/925,501 patent/US7425499B2/en not_active Expired - Lifetime
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2005
- 2005-08-08 JP JP2007529900A patent/JP4919087B2/ja not_active Expired - Lifetime
- 2005-08-08 KR KR1020077005371A patent/KR100871585B1/ko not_active Expired - Lifetime
- 2005-08-08 EP EP05784984A patent/EP1792341A1/en not_active Withdrawn
- 2005-08-08 WO PCT/US2005/028149 patent/WO2006023318A1/en not_active Ceased
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| JPH02257643A (ja) * | 1989-03-29 | 1990-10-18 | Mitsubishi Electric Corp | 半導体装置及びその製造方法 |
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Also Published As
| Publication number | Publication date |
|---|---|
| KR100871585B1 (ko) | 2008-12-02 |
| TW200623323A (en) | 2006-07-01 |
| TWI296432B (en) | 2008-05-01 |
| KR20070043030A (ko) | 2007-04-24 |
| WO2006023318A1 (en) | 2006-03-02 |
| JP2008511174A (ja) | 2008-04-10 |
| US7425499B2 (en) | 2008-09-16 |
| US20060042952A1 (en) | 2006-03-02 |
| EP1792341A1 (en) | 2007-06-06 |
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