JP4901476B2 - 格子定数の異なる材料を用いる半導体構造及び同構造の形成方法 - Google Patents

格子定数の異なる材料を用いる半導体構造及び同構造の形成方法 Download PDF

Info

Publication number
JP4901476B2
JP4901476B2 JP2006533987A JP2006533987A JP4901476B2 JP 4901476 B2 JP4901476 B2 JP 4901476B2 JP 2006533987 A JP2006533987 A JP 2006533987A JP 2006533987 A JP2006533987 A JP 2006533987A JP 4901476 B2 JP4901476 B2 JP 4901476B2
Authority
JP
Japan
Prior art keywords
layer
layers
lattice constant
forming
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2006533987A
Other languages
English (en)
Japanese (ja)
Other versions
JP2007507896A5 (https=
JP2007507896A (ja
Inventor
リウ，チュン−リ
バール，アレクサンダー・エル
グラント，ジョン・エム
ヌイェン，ビチ−イェン
オルロウスキー，マリウス・ケイ
スティーブンス，タブ・エイ
ホワイト，テッド・アール
トーマス，ショーン・ジー
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP USA Inc
Original Assignee
NXP USA Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NXP USA Inc filed Critical NXP USA Inc
Publication of JP2007507896A publication Critical patent/JP2007507896A/ja
Publication of JP2007507896A5 publication Critical patent/JP2007507896A5/ja
Application granted granted Critical
Publication of JP4901476B2 publication Critical patent/JP4901476B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P10/00—Bonding of wafers, substrates or parts of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/751—Insulated-gate field-effect transistors [IGFET] having composition variations in the channel regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
    • H10D30/798—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions being provided in or under the channel regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/40—Crystalline structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/27—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials using selective deposition, e.g. simultaneous growth of monocrystalline and non-monocrystalline semiconductor materials
    • H10P14/271—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials using selective deposition, e.g. simultaneous growth of monocrystalline and non-monocrystalline semiconductor materials characterised by the preparation of substrate for selective deposition
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/27—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials using selective deposition, e.g. simultaneous growth of monocrystalline and non-monocrystalline semiconductor materials
    • H10P14/276—Lateral overgrowth
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/29—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by the substrates
    • H10P14/2901—Materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/29—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by the substrates
    • H10P14/2901—Materials
    • H10P14/2902—Materials being Group IVA materials
    • H10P14/2905—Silicon, silicon germanium or germanium
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/32—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by intermediate layers between substrates and deposited layers
    • H10P14/3202—Materials thereof
    • H10P14/3204—Materials thereof being Group IVA semiconducting materials
    • H10P14/3211—Silicon, silicon germanium or germanium
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/32—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by intermediate layers between substrates and deposited layers
    • H10P14/3242—Structure
    • H10P14/3244—Layer structure
    • H10P14/3251—Layer structure consisting of three or more layers
    • H10P14/3252—Alternating layers, e.g. superlattice
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3402—Deposited materials, e.g. layers characterised by the chemical composition
    • H10P14/3404—Deposited materials, e.g. layers characterised by the chemical composition being Group IVA materials
    • H10P14/3411—Silicon, silicon germanium or germanium
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0212—Manufacture or treatment of FETs having insulated gates [IGFET] using self-aligned silicidation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs 

Landscapes

  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thin Film Transistor (AREA)
  • Element Separation (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Recrystallisation Techniques (AREA)
JP2006533987A 2003-10-02 2004-09-27 格子定数の異なる材料を用いる半導体構造及び同構造の形成方法 Expired - Fee Related JP4901476B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US10/677,844 US6831350B1 (en) 2003-10-02 2003-10-02 Semiconductor structure with different lattice constant materials and method for forming the same
US10/677,844 2003-10-02
PCT/US2004/031516 WO2005034230A1 (en) 2003-10-02 2004-09-27 Semiconductor structure with different lattice constant materials and method for forming the same

Publications (3)

Publication Number Publication Date
JP2007507896A JP2007507896A (ja) 2007-03-29
JP2007507896A5 JP2007507896A5 (https=) 2007-11-15
JP4901476B2 true JP4901476B2 (ja) 2012-03-21

Family

ID=33490980

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006533987A Expired - Fee Related JP4901476B2 (ja) 2003-10-02 2004-09-27 格子定数の異なる材料を用いる半導体構造及び同構造の形成方法

Country Status (6)

Country Link
US (1) US6831350B1 (https=)
JP (1) JP4901476B2 (https=)
KR (1) KR101115091B1 (https=)
CN (1) CN100487876C (https=)
TW (1) TWI356491B (https=)
WO (1) WO2005034230A1 (https=)

Families Citing this family (35)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6919258B2 (en) * 2003-10-02 2005-07-19 Freescale Semiconductor, Inc. Semiconductor device incorporating a defect controlled strained channel structure and method of making the same
DE102004053307B4 (de) * 2004-11-04 2010-01-07 Siltronic Ag Mehrschichtenstruktur umfassend ein Substrat und eine darauf heteroepitaktisch abgeschiedene Schicht aus Silicium und Germanium und ein Verfahren zu deren Herstellung
US9153645B2 (en) 2005-05-17 2015-10-06 Taiwan Semiconductor Manufacturing Company, Ltd. Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication
US8324660B2 (en) 2005-05-17 2012-12-04 Taiwan Semiconductor Manufacturing Company, Ltd. Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication
FR2888400B1 (fr) * 2005-07-08 2007-10-19 Soitec Silicon On Insulator Procede de prelevement de couche
US7524707B2 (en) 2005-08-23 2009-04-28 Freescale Semiconductor, Inc. Modified hybrid orientation technology
US7947546B2 (en) * 2005-10-31 2011-05-24 Chartered Semiconductor Manufacturing, Ltd. Implant damage control by in-situ C doping during SiGe epitaxy for device applications
US7479422B2 (en) * 2006-03-10 2009-01-20 Freescale Semiconductor, Inc. Semiconductor device with stressors and method therefor
US7777250B2 (en) 2006-03-24 2010-08-17 Taiwan Semiconductor Manufacturing Company, Ltd. Lattice-mismatched semiconductor structures and related methods for device fabrication
US7700420B2 (en) * 2006-04-12 2010-04-20 Freescale Semiconductor, Inc. Integrated circuit with different channel materials for P and N channel transistors and method therefor
US8173551B2 (en) 2006-09-07 2012-05-08 Taiwan Semiconductor Manufacturing Co., Ltd. Defect reduction using aspect ratio trapping
US7875958B2 (en) 2006-09-27 2011-01-25 Taiwan Semiconductor Manufacturing Company, Ltd. Quantum tunneling devices and circuits with lattice-mismatched semiconductor structures
US20080187018A1 (en) 2006-10-19 2008-08-07 Amberwave Systems Corporation Distributed feedback lasers formed via aspect ratio trapping
US7825328B2 (en) 2007-04-09 2010-11-02 Taiwan Semiconductor Manufacturing Company, Ltd. Nitride-based multi-junction solar cell modules and methods for making the same
US8304805B2 (en) 2009-01-09 2012-11-06 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor diodes fabricated by aspect ratio trapping with coalesced films
US9508890B2 (en) 2007-04-09 2016-11-29 Taiwan Semiconductor Manufacturing Company, Ltd. Photovoltaics on silicon
US8237151B2 (en) * 2009-01-09 2012-08-07 Taiwan Semiconductor Manufacturing Company, Ltd. Diode-based devices and methods for making the same
US8329541B2 (en) * 2007-06-15 2012-12-11 Taiwan Semiconductor Manufacturing Company, Ltd. InP-based transistor fabrication
WO2009035746A2 (en) 2007-09-07 2009-03-19 Amberwave Systems Corporation Multi-junction solar cells
US8183667B2 (en) 2008-06-03 2012-05-22 Taiwan Semiconductor Manufacturing Co., Ltd. Epitaxial growth of crystalline material
US8274097B2 (en) 2008-07-01 2012-09-25 Taiwan Semiconductor Manufacturing Company, Ltd. Reduction of edge effects from aspect ratio trapping
US8981427B2 (en) 2008-07-15 2015-03-17 Taiwan Semiconductor Manufacturing Company, Ltd. Polishing of small composite semiconductor materials
WO2010033813A2 (en) 2008-09-19 2010-03-25 Amberwave System Corporation Formation of devices by epitaxial layer overgrowth
US20100072515A1 (en) 2008-09-19 2010-03-25 Amberwave Systems Corporation Fabrication and structures of crystalline material
US8253211B2 (en) 2008-09-24 2012-08-28 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor sensor structures with reduced dislocation defect densities
SG171987A1 (en) 2009-04-02 2011-07-28 Taiwan Semiconductor Mfg Devices formed from a non-polar plane of a crystalline material and method of making the same
EP2423951B1 (en) * 2010-08-05 2016-07-20 Imec Antiphase domain boundary-free III-V compound semiconductor material on semiconductor substrate and method for manufacturing thereof
US9099421B2 (en) * 2012-10-31 2015-08-04 Taiwan Semiconductor Manufacturing Company Limited Surface profile for semiconductor region
US9818884B2 (en) 2014-03-28 2017-11-14 Intel Corporation Strain compensation in transistors
US10170549B2 (en) 2014-10-21 2019-01-01 Samsung Electronics Co., Ltd. Strained stacked nanosheet FETs and/or quantum well stacked nanosheet
US9735010B1 (en) 2016-05-27 2017-08-15 International Business Machines Corporation Fabrication of semiconductor fin structures
US10249492B2 (en) 2016-05-27 2019-04-02 International Business Machines Corporation Fabrication of compound semiconductor structures
CN108807279B (zh) * 2018-06-25 2021-01-22 中国科学院微电子研究所 半导体结构与其制作方法
TWI698912B (zh) * 2018-09-03 2020-07-11 環球晶圓股份有限公司 磊晶基板及其製造方法
US12588258B2 (en) * 2023-08-03 2026-03-24 Taiwan Semiconductor Manufacturing Co., Ltd. Stacked transistor isolation features and methods of forming the same

Family Cites Families (36)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4522662A (en) 1983-08-12 1985-06-11 Hewlett-Packard Company CVD lateral epitaxial growth of silicon over insulators
US4557794A (en) 1984-05-07 1985-12-10 Rca Corporation Method for forming a void-free monocrystalline epitaxial layer on a mask
US4619033A (en) 1985-05-10 1986-10-28 Rca Corporation Fabricating of a CMOS FET with reduced latchup susceptibility
US4891092A (en) 1986-01-13 1990-01-02 General Electric Company Method for making a silicon-on-insulator substrate
US4755481A (en) 1986-05-15 1988-07-05 General Electric Company Method of making a silicon-on-insulator transistor
US4760036A (en) 1987-06-15 1988-07-26 Delco Electronics Corporation Process for growing silicon-on-insulator wafers using lateral epitaxial growth with seed window oxidation
FR2629636B1 (fr) 1988-04-05 1990-11-16 Thomson Csf Procede de realisation d'une alternance de couches de materiau semiconducteur monocristallin et de couches de materiau isolant
EP0391081A3 (en) 1989-04-06 1991-08-07 International Business Machines Corporation Fabrication and structure of semiconductor-on-insulator islands
JPH02302044A (ja) 1989-05-16 1990-12-14 Fujitsu Ltd 半導体装置の製造方法
US5202284A (en) 1989-12-01 1993-04-13 Hewlett-Packard Company Selective and non-selective deposition of Si1-x Gex on a Si subsrate that is partially masked with SiO2
US5273921A (en) 1991-12-27 1993-12-28 Purdue Research Foundation Methods for fabricating a dual-gated semiconductor-on-insulator field effect transistor
US5445107A (en) 1993-11-22 1995-08-29 Motorola, Inc. Semiconductor device and method of formation
US5963817A (en) * 1997-10-16 1999-10-05 International Business Machines Corporation Bulk and strained silicon on insulator using local selective oxidation
JP3403076B2 (ja) * 1998-06-30 2003-05-06 株式会社東芝 半導体装置及びその製造方法
US6110278A (en) 1998-08-10 2000-08-29 Saxena; Arjun N. Methods for and products of growth of single-crystal on arrayed nucleation sites (SCANS) defined in nucleation unfriendly substrates
US6392253B1 (en) 1998-08-10 2002-05-21 Arjun J. Saxena Semiconductor device with single crystal films grown on arrayed nucleation sites on amorphous and/or non-single crystal surfaces
US6350993B1 (en) 1999-03-12 2002-02-26 International Business Machines Corporation High speed composite p-channel Si/SiGe heterostructure for field effect devices
US6214653B1 (en) 1999-06-04 2001-04-10 International Business Machines Corporation Method for fabricating complementary metal oxide semiconductor (CMOS) devices on a mixed bulk and silicon-on-insulator (SOI) substrate
US6261878B1 (en) 1999-06-21 2001-07-17 Intel Corporation Integrated circuit with dynamic threshold voltage
US6228691B1 (en) 1999-06-30 2001-05-08 Intel Corp. Silicon-on-insulator devices and method for producing the same
US6326272B1 (en) 1999-11-18 2001-12-04 Chartered Semiconductor Manufacturing Ltd. Method for forming self-aligned elevated transistor
US6429099B1 (en) 2000-01-05 2002-08-06 International Business Machines Corporation Implementing contacts for bodies of semiconductor-on-insulator transistors
US6362071B1 (en) 2000-04-05 2002-03-26 Motorola, Inc. Method for forming a semiconductor device with an opening in a dielectric layer
WO2002047168A2 (en) 2000-12-04 2002-06-13 Amberwave Systems Corporation Cmos inverter circuits utilizing strained silicon surface channel mosfets
WO2002071491A1 (en) * 2001-03-02 2002-09-12 Amberwave Systems Corporation Relaxed silicon germanium platform for high speed cmos electronics and high speed analog circuits
US6703688B1 (en) * 2001-03-02 2004-03-09 Amberwave Systems Corporation Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
JP2004531054A (ja) * 2001-03-02 2004-10-07 アンバーウェーブ システムズ コーポレイション 高速ｃｍｏｓ電子機器及び高速アナログ回路のための緩和シリコンゲルマニウムプラットフォーム
US6830976B2 (en) 2001-03-02 2004-12-14 Amberwave Systems Corproation Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
US6900103B2 (en) 2001-03-02 2005-05-31 Amberwave Systems Corporation Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
US6916727B2 (en) 2001-06-21 2005-07-12 Massachusetts Institute Of Technology Enhancement of P-type metal-oxide-semiconductor field effect transistors
EP1415331A2 (en) 2001-08-06 2004-05-06 Massachusetts Institute Of Technology Formation of planar strained layers
US6974735B2 (en) 2001-08-09 2005-12-13 Amberwave Systems Corporation Dual layer Semiconductor Devices
JP2005504436A (ja) 2001-09-21 2005-02-10 アンバーウェーブ システムズ コーポレイション 画定された不純物勾配を有するひずみ材料層を使用する半導体構造、およびその構造を製作するための方法。
US6600170B1 (en) * 2001-12-17 2003-07-29 Advanced Micro Devices, Inc. CMOS with strained silicon channel NMOS and silicon germanium channel PMOS
US6492216B1 (en) 2002-02-07 2002-12-10 Taiwan Semiconductor Manufacturing Company Method of forming a transistor with a strained channel
JP2004342819A (ja) * 2003-05-15 2004-12-02 Toshiba Ceramics Co Ltd 半導体基板およびその製造方法

Also Published As

Publication number Publication date
US6831350B1 (en) 2004-12-14
TW200524155A (en) 2005-07-16
KR20060090242A (ko) 2006-08-10
KR101115091B1 (ko) 2012-03-13
WO2005034230A1 (en) 2005-04-14
CN100487876C (zh) 2009-05-13
JP2007507896A (ja) 2007-03-29
TWI356491B (en) 2012-01-11
CN1853260A (zh) 2006-10-25

Similar Documents

Publication Publication Date Title
JP4901476B2 (ja) 格子定数の異なる材料を用いる半導体構造及び同構造の形成方法
KR102110858B1 (ko) 결함 이동 및 격자 불일치된 에피택셜 막
US7791064B2 (en) Semiconductor device and fabrication method thereof
KR101354844B1 (ko) 반도체 장치 및 그의 제조 방법
CN100364052C (zh) 晶格调谐半导体衬底的形成
US20220285526A1 (en) Method of making heteroepitaxial structures and device formed by the method
US20050205936A1 (en) Semiconductor device incorporating a defect controlled strained channel structure and method of making the same
KR20120089354A (ko) 양자 웰 트랜지스터에 접촉부를 형성하는 기술
WO2014099036A1 (en) Expitaxial film on nanoscale structure
TW201635517A (zh) 具有替代通道材料之電性絕緣鰭片結構及其製法
US20170062426A1 (en) Co-integration of tensile silicon and compressive silicon germanium
KR20150000386A (ko) 응력 변형된 반도체 구조물 형성 방법
US9548355B1 (en) Compound finFET device including oxidized III-V fin isolator
CN1319124C (zh) 制造绝缘体上半导体沟道结构的方法
CN113471138A (zh) 半导体基底的制备方法及半导体器件
US9337281B2 (en) Planar semiconductor growth on III-V material
JPH07193233A (ja) ゲート壁側壁なしトランジスタの製造方法
JP4888385B2 (ja) 半導体装置及びその製造方法
US10600890B2 (en) Contact to metal gate isolation structure
JP4221928B2 (ja) 半導体基板及び電界効果型トランジスタ並びにこれらの製造方法
US20120228628A1 (en) Semiconductor device and method of fabricating the same
EP2693462B1 (en) Method for manufacturing semiconductor devices
CN120388882A (zh) 在soi衬底上生长锗硅层的方法及半导体器件
CN103227205B (zh) 具有深槽结构的图形化应变pmos器件及其制作方法
CN103227205A (zh) 具有深槽结构的图形化应变pmos器件及其制作方法

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20070926

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20070926

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20110620

RD04 Notification of resignation of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7424

Effective date: 20110912

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20110920

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20111130

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20111227

R150 Certificate of patent or registration of utility model

Ref document number: 4901476

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20150113

Year of fee payment: 3

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

S533 Written request for registration of change of name

Free format text: JAPANESE INTERMEDIATE CODE: R313533

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees