JP4879737B2 - 半導体層の分離方法 - Google Patents
半導体層の分離方法 Download PDFInfo
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- JP4879737B2 JP4879737B2 JP2006522444A JP2006522444A JP4879737B2 JP 4879737 B2 JP4879737 B2 JP 4879737B2 JP 2006522444 A JP2006522444 A JP 2006522444A JP 2006522444 A JP2006522444 A JP 2006522444A JP 4879737 B2 JP4879737 B2 JP 4879737B2
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- 238000000034 method Methods 0.000 title claims description 33
- 239000004065 semiconductor Substances 0.000 title claims description 7
- 238000010438 heat treatment Methods 0.000 claims description 43
- 238000000137 annealing Methods 0.000 claims description 30
- 238000000926 separation method Methods 0.000 claims description 26
- 238000002513 implantation Methods 0.000 claims description 15
- 239000000463 material Substances 0.000 claims description 9
- 230000000977 initiatory effect Effects 0.000 claims description 3
- 235000012431 wafers Nutrition 0.000 description 78
- 230000000295 complement effect Effects 0.000 description 5
- 238000009826 distribution Methods 0.000 description 4
- 230000003746 surface roughness Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 239000007943 implant Substances 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000012512 characterization method Methods 0.000 description 1
- 238000004581 coalescence Methods 0.000 description 1
- 238000002425 crystallisation Methods 0.000 description 1
- 230000008025 crystallization Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000009828 non-uniform distribution Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000004439 roughness measurement Methods 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
- 238000004381 surface treatment Methods 0.000 description 1
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- Crystals, And After-Treatments Of Crystals (AREA)
- Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
Description
本発明による方法の第1工程は、半導体材料ウエハの厚さ内で、分離される層を画定する脆化ゾーンを生成することからなる。
このようにして、脆化ゾーンが一旦その開始領域を有するウエハに形成されると、ウエハは、ウエハの残余部分からの、脆化ゾーンのレベルの層の分離のための処理に曝される。
脆化ゾーンが局所オーバードーズを有する注入によって形成された、本発明の好ましい実施形態の場合において、この処理はアニーリングを使用する。
上記のように、SMARTCUT(登録商標)法の代替形態に対応する好ましい実施形態と異なる実施形態により、本発明を採用することが可能である。
Claims (6)
- 半導体材料から選ばれた材料のウエハから層を分離する方法において、
前記分離される層を前記ウエハの厚さ内に画定する脆化ゾーンを前記ウエハの厚さ内に生成する工程と、
前記脆化ゾーンの非常に脆弱な領域に対応するように、大きな脆弱性を有する局所的な開始領域を前記脆化ゾーン内に形成する工程と、
前記脆化ゾーンのレベルで、前記ウエハを熱処理に曝して前記層の分離を行なう工程とを備えた方法であって、
前記ウエハが容器内で垂直に配置され、前記容器を囲むように垂直方向に順々に配置された複数の加熱素子と該複数の加熱素子の各々を選択的に制御する手段とを備えた垂直炉を用いて、前記加熱素子の各々の加熱力を選択的に制御するように、前記分離のための前記熱処理が行なわれ、
前記脆化ゾーン全体に亘って空間的に一様な熱量が前記ウエハに印加されるように、前記加熱素子の各々が制御されることを特徴とする方法。 - 前記脆化ゾーンが原子種の注入によって生成され、前記注入中に前記開始領域が原子種のオーバードーズの局所的な注入によって生成されることを特徴とする請求項1に記載の方法。
- 前記熱処理が熱アニーリングであることを特徴とする請求項2に記載の方法。
- 前記分離を行なうのに必要なエネルギーに相当する熱量を前記ウエハに印加するために前記熱アニーリングが行なわれることを特徴とする請求項3に記載の方法。
- 前記熱アニーリング中に前記開始領域のレベルで前記分離が開始されることを特徴とする請求項3又は4に記載の方法。
- 前記脆化ゾーンの全域に亘り、前記開始領域から前記分離が進行することを特徴とする請求項5に記載の方法。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/766,207 | 2004-01-29 | ||
US10/766,207 US7465645B2 (en) | 2003-08-04 | 2004-01-29 | Method of detaching a layer from a wafer using a localized starting area |
PCT/IB2004/002693 WO2005013355A1 (en) | 2003-08-04 | 2004-08-04 | Method of detaching a semiconductor layer |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2007507859A JP2007507859A (ja) | 2007-03-29 |
JP4879737B2 true JP4879737B2 (ja) | 2012-02-22 |
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Application Number | Title | Priority Date | Filing Date |
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JP2006522444A Active JP4879737B2 (ja) | 2004-01-29 | 2004-08-04 | 半導体層の分離方法 |
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JP (1) | JP4879737B2 (ja) |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2797347B1 (fr) * | 1999-08-04 | 2001-11-23 | Commissariat Energie Atomique | Procede de transfert d'une couche mince comportant une etape de surfragililisation |
EP1212787B1 (en) * | 1999-08-10 | 2014-10-08 | Silicon Genesis Corporation | A cleaving process to fabricate multilayered substrates using low implantation doses |
JP3988338B2 (ja) * | 1999-10-07 | 2007-10-10 | ウシオ電機株式会社 | 光照射式急速加熱処理装置の制御装置 |
FR2811807B1 (fr) * | 2000-07-12 | 2003-07-04 | Commissariat Energie Atomique | Procede de decoupage d'un bloc de materiau et de formation d'un film mince |
JP2002353082A (ja) * | 2001-05-28 | 2002-12-06 | Shin Etsu Handotai Co Ltd | 貼り合わせウェーハの製造方法 |
JP2003347176A (ja) * | 2002-03-20 | 2003-12-05 | Shin Etsu Handotai Co Ltd | 貼り合わせウェーハの製造方法 |
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