TW201018755A - Silicon wafer and manufacturing method thereof - Google Patents
Silicon wafer and manufacturing method thereof Download PDFInfo
- Publication number
- TW201018755A TW201018755A TW98133034A TW98133034A TW201018755A TW 201018755 A TW201018755 A TW 201018755A TW 98133034 A TW98133034 A TW 98133034A TW 98133034 A TW98133034 A TW 98133034A TW 201018755 A TW201018755 A TW 201018755A
- Authority
- TW
- Taiwan
- Prior art keywords
- wafer
- equal
- crystal
- less
- heat treatment
- Prior art date
Links
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 14
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 14
- 239000010703 silicon Substances 0.000 title claims abstract description 14
- 238000004519 manufacturing process Methods 0.000 title claims description 37
- 238000010438 heat treatment Methods 0.000 claims abstract description 83
- 239000004065 semiconductor Substances 0.000 claims abstract description 50
- 238000002844 melting Methods 0.000 claims abstract description 13
- 230000008018 melting Effects 0.000 claims abstract description 13
- 239000013078 crystal Substances 0.000 claims description 87
- 230000002093 peripheral effect Effects 0.000 claims description 48
- 238000000034 method Methods 0.000 claims description 46
- 229910052715 tantalum Inorganic materials 0.000 claims description 28
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims description 28
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 24
- 238000005336 cracking Methods 0.000 claims description 21
- 238000005498 polishing Methods 0.000 claims description 19
- 230000008569 process Effects 0.000 claims description 17
- 238000002360 preparation method Methods 0.000 claims description 16
- 238000007689 inspection Methods 0.000 claims description 14
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 11
- 239000001301 oxygen Substances 0.000 claims description 11
- 229910052760 oxygen Inorganic materials 0.000 claims description 11
- 239000000463 material Substances 0.000 claims description 8
- 239000004020 conductor Substances 0.000 claims description 6
- 229910052732 germanium Inorganic materials 0.000 claims description 6
- 239000004575 stone Substances 0.000 claims description 6
- 239000000758 substrate Substances 0.000 claims description 6
- 241000238631 Hexapoda Species 0.000 claims description 4
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 claims description 3
- 229910052707 ruthenium Inorganic materials 0.000 claims description 3
- 238000004381 surface treatment Methods 0.000 claims description 3
- 210000003298 dental enamel Anatomy 0.000 claims 1
- 238000007430 reference method Methods 0.000 claims 1
- 230000005855 radiation Effects 0.000 abstract description 4
- 235000012431 wafers Nutrition 0.000 description 325
- 239000010410 layer Substances 0.000 description 29
- 238000000137 annealing Methods 0.000 description 27
- 238000001816 cooling Methods 0.000 description 26
- 239000012535 impurity Substances 0.000 description 25
- 239000012495 reaction gas Substances 0.000 description 17
- 239000012212 insulator Substances 0.000 description 14
- 125000004429 atom Chemical group 0.000 description 12
- 230000007547 defect Effects 0.000 description 11
- 230000035882 stress Effects 0.000 description 10
- 230000015572 biosynthetic process Effects 0.000 description 9
- 239000004301 calcium benzoate Substances 0.000 description 9
- 230000004913 activation Effects 0.000 description 7
- 238000000227 grinding Methods 0.000 description 7
- 238000009792 diffusion process Methods 0.000 description 6
- 239000007789 gas Substances 0.000 description 5
- 239000004300 potassium benzoate Substances 0.000 description 5
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 4
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 239000001257 hydrogen Substances 0.000 description 4
- 229910052739 hydrogen Inorganic materials 0.000 description 4
- 239000001508 potassium citrate Substances 0.000 description 4
- 238000004151 rapid thermal annealing Methods 0.000 description 4
- 239000000523 sample Substances 0.000 description 4
- 238000001947 vapour-phase growth Methods 0.000 description 4
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 3
- 239000012298 atmosphere Substances 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 3
- 238000002513 implantation Methods 0.000 description 3
- 230000003287 optical effect Effects 0.000 description 3
- 230000010355 oscillation Effects 0.000 description 3
- 239000004299 sodium benzoate Substances 0.000 description 3
- 239000001509 sodium citrate Substances 0.000 description 3
- 239000007787 solid Substances 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 2
- CURLTUGMZLYLDI-UHFFFAOYSA-N Carbon dioxide Chemical compound O=C=O CURLTUGMZLYLDI-UHFFFAOYSA-N 0.000 description 2
- 230000009471 action Effects 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052799 carbon Inorganic materials 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 239000012809 cooling fluid Substances 0.000 description 2
- 238000005520 cutting process Methods 0.000 description 2
- 230000009849 deactivation Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 238000005286 illumination Methods 0.000 description 2
- 239000010453 quartz Substances 0.000 description 2
- 238000007493 shaping process Methods 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- 229910052684 Cerium Inorganic materials 0.000 description 1
- 241000219112 Cucumis Species 0.000 description 1
- 235000015510 Cucumis melo subsp melo Nutrition 0.000 description 1
- 101100316028 Drosophila melanogaster Uggt gene Proteins 0.000 description 1
- KDXKERNSBIXSRK-UHFFFAOYSA-N Lysine Natural products NCCCCC(N)C(O)=O KDXKERNSBIXSRK-UHFFFAOYSA-N 0.000 description 1
- 239000004472 Lysine Substances 0.000 description 1
- 241000282376 Panthera tigris Species 0.000 description 1
- 229910003822 SiHCl3 Inorganic materials 0.000 description 1
- 101150060067 Uggt1 gene Proteins 0.000 description 1
- 238000007545 Vickers hardness test Methods 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- 239000000654 additive Substances 0.000 description 1
- 230000000996 additive effect Effects 0.000 description 1
- 230000032683 aging Effects 0.000 description 1
- 229910021529 ammonia Inorganic materials 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 239000001569 carbon dioxide Substances 0.000 description 1
- 229910002092 carbon dioxide Inorganic materials 0.000 description 1
- GWXLDORMOJMVQZ-UHFFFAOYSA-N cerium Chemical compound [Ce] GWXLDORMOJMVQZ-UHFFFAOYSA-N 0.000 description 1
- 229910000420 cerium oxide Inorganic materials 0.000 description 1
- 210000000078 claw Anatomy 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 238000002425 crystallisation Methods 0.000 description 1
- 230000008025 crystallization Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 238000007865 diluting Methods 0.000 description 1
- 229910001873 dinitrogen Inorganic materials 0.000 description 1
- 235000013399 edible fruits Nutrition 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 210000000232 gallbladder Anatomy 0.000 description 1
- 125000005843 halogen group Chemical group 0.000 description 1
- 230000036541 health Effects 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 239000001307 helium Substances 0.000 description 1
- 229910052734 helium Inorganic materials 0.000 description 1
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 1
- 238000007654 immersion Methods 0.000 description 1
- 238000007373 indentation Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 230000009191 jumping Effects 0.000 description 1
- 229910052746 lanthanum Inorganic materials 0.000 description 1
- FZLIPJUXYLNCLC-UHFFFAOYSA-N lanthanum atom Chemical compound [La] FZLIPJUXYLNCLC-UHFFFAOYSA-N 0.000 description 1
- 238000011068 loading method Methods 0.000 description 1
- 238000003754 machining Methods 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910052754 neon Inorganic materials 0.000 description 1
- GKAOGPIIYCISHV-UHFFFAOYSA-N neon atom Chemical compound [Ne] GKAOGPIIYCISHV-UHFFFAOYSA-N 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 229910000069 nitrogen hydride Inorganic materials 0.000 description 1
- BMMGVYCKOGBVEV-UHFFFAOYSA-N oxo(oxoceriooxy)cerium Chemical compound [Ce]=O.O=[Ce]=O BMMGVYCKOGBVEV-UHFFFAOYSA-N 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 239000012071 phase Substances 0.000 description 1
- 239000002244 precipitate Substances 0.000 description 1
- 230000002285 radioactive effect Effects 0.000 description 1
- 229910052761 rare earth metal Inorganic materials 0.000 description 1
- 150000002910 rare earth metals Chemical class 0.000 description 1
- 238000001953 recrystallisation Methods 0.000 description 1
- 230000001568 sexual effect Effects 0.000 description 1
- 239000006104 solid solution Substances 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 229910001220 stainless steel Inorganic materials 0.000 description 1
- 239000010935 stainless steel Substances 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
- 230000001052 transient effect Effects 0.000 description 1
- 239000012808 vapor phase Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02664—Aftertreatments
- H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
- H01L21/02675—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using laser beams
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02664—Aftertreatments
- H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
- H01L21/02691—Scanning of a beam
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/268—Bombardment with radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Optics & Photonics (AREA)
- High Energy & Nuclear Physics (AREA)
- Ceramic Engineering (AREA)
- Toxicology (AREA)
- Health & Medical Sciences (AREA)
- Electromagnetism (AREA)
- Crystals, And After-Treatments Of Crystals (AREA)
Abstract
Description
201018755 六、發明說明： 【發明所屬之技術領域】 本發明係有關於一種用於矽晶圓及其製造方法中之 較佳技術。 本申請案係基於2_年9月29日於日本申靖之日本 專利特願2008-250776號並主張其優先權，於本文中引用 其内容。 【先前技術】 由於元件（device )的高積體化，於元件製程（p_ss ) 中正多用急速升降溫步驟，存在元件製程短時間化，而急 速升降溫步驟的最高溫度亦高溫化的傾向。尤其自45 nm 節點（node)( hp65 )開始’有使用被稱作閃光燈退火（flash lamp annealing ’ FLA )、雷射瞬間退火（Laser Spike Anneal， LSA)、或雷射熱處理（laser thermal process，LTP)的退 火步驟等情況。 其中，LSA熱處理中’將晶圓於熱板（hot plate)上 預先升溫至400°C〜600°C的初始溫度，並利用雷射照射來 對晶圓進行光點掃描（spot scan)，藉此將晶圓急速加熱、 驟冷至大於等於ll〇〇°C的矽的溶點附近為止。而且，熱處 理時間的單位（order)為微秒至毫秒。 關於LSA處理的技術在以下的專利文獻1及專利文獻 2中有所揭示。 如專利文獻1及專利文獻2所揭示的熱處理中會在晶 圓表面與背面產生數百它的溫度差，與以前所進行的急速 201018755 熱退火（Rapid Thermal Annealing，RTA)相比，晶圓上會201018755 VI. Description of the Invention: TECHNICAL FIELD OF THE INVENTION The present invention relates to a preferred technique for use in a germanium wafer and a method of fabricating the same. The present application is based on Japanese Patent Application No. 2008-250776, the entire disclosure of which is incorporated herein by reference. [Prior Art] Due to the high integration of devices, a rapid ramp-up step is often used in the component process (p_ss), and the component process is shortened for a short period of time, and the maximum temperature of the rapid ramp-up step tends to be high. Especially since the 45 nm node (hp65), there is a use called flash lamp annealing 'FLA, Laser Spike Anneal (LSA), or laser thermal process (LTP). The annealing step and the like. In the LSA heat treatment, the wafer is preheated on a hot plate to an initial temperature of 400 ° C to 600 ° C, and a spot scan is performed on the wafer by laser irradiation. This heats the wafer rapidly and quenches it to the vicinity of the melting point of 矽 大于 〇〇 °C. Moreover, the order of the heat treatment time is from microseconds to milliseconds. A technique for LSA processing is disclosed in Patent Document 1 and Patent Document 2 below. In the heat treatment disclosed in Patent Document 1 and Patent Document 2, a temperature difference of several hundred is generated on the surface and the back surface of the wafer, compared with the rapid 201018755 Rapid Thermal Annealing (RTA) performed on the wafer. meeting
負擔非常高的應力。而且，在晶圓直徑方向上亦會產生數 百。C的溫度差，同樣地與以前所進行的RTA相比，晶圓上 會負擔非常高的應力。 BBurden very high stress. Moreover, hundreds of wafer diameters are also generated. The temperature difference of C is similarly higher than that of the previously performed RTA, which imposes a very high stress on the wafer. B
[先行技術文獻] [專利文獻][Advanced Technical Literature] [Patent Literature]
[專利文獻1]曰本專利特表2006_505953號公報 [專利文獻2]曰本專利第4001602號公報 然而’先前的晶圓中，於如此般負擔有高應力的上述 LSA之類的毫秒退火巾，產生晶圓有可能會韻的問題。 尤其在雷射掃描晶圓最外周附近時，有時晶圓會發生破 裂，因此有要求改善此類問題。 【發明内容】 種在3 ^有胁上述情況而完成的，目的在於提供一 的晶圓。U 退火處理的毫秒退火巾仍具有破裂财受性 在極值溫度)較高’並且 條件苛収胁祕賴處理中的溫度 在―中’因各個熱處理的::方==晶 5 201018755 J^DOUpil 圓中的應力（stress)的產生狀態不同，故需要與該些加熱 方法對應的破裂防止對策。 因此，為了於該些條件的熱處理中晶圓不會發生破 裂，而調查晶圓表面上的劃痕〜裂紋〜的有無與破裂發生 的關係。 其結果發現，如後述的實施例般，在存在於晶圓緣部 的劃痕（crack ’裂紋）的大小、其位置與處理溫度之間存 在著關係。 本發明的矽晶圓，是在經鏡面加工之後，被提供給具 有掃描雷射照射型熱處理步驟的半導體元件製程的矽晶 圓，該掃描雷射照射型熱處理步驟是設為最高溫度大於等 於1100°c且小於等於矽的熔點並且處理時間為i微秒至1〇 毫秒左右為止的條件。 本發明的矽晶圓中，在上述掃描雷射照射型熱處理步 驟中成為矽晶圓破裂發生原因的大於等於10 的劃痕 被排除。上述大於等於10 的劃痕被排除的範圍是， 上述發晶圓端面、以及上述梦晶圓背面中的自最外周部朝 向晶圓直财向中心的距離與晶κ直徑尺寸之比為0〜 3/300以内的範圍，藉由該構成，解決了上述課題。 於本發明中，更好的是，在上述石夕晶圓端面、以及自 上述石夕晶圓背面最外周部朝向晶圓直财向中心為3軸 ，内的範®巾的大小大於等於2 _的LpD (亮點缺陷 小於等於10個》 本發明的上述矽晶圓的氧濃度〇i可設為大於等於5χ 201018755 J^JOUpu. 10 atoms/cm3 且小於等於 2〇χ1〇π at_/cm3( 〇id· 而且’本發明的石夕晶圓的製造方法，是將石夕晶圓進行 =加工之後’提供給具有掃财射照射麵處理步驟的 半導體請製簡⑦製造方法，其巾，掃描雷射照 射型熱處理㈣的條件是設為最高溫度大於等於聰t 且小於等於料熔點並且處理_為】微輕iq 右為止的條件。 將在上述掃描雷射照射型熱處理步驟中成為梦 破裂發生原因的大於等於10 _的劃痕，在上述發晶園 端面、以及上述石夕晶園背面中的自最外周部朝向晶圓直徑 方向中心的距離與晶圓直握尺寸之比為〇〜3/3〇〇以内的 範圍中予以排除，從而解決了上述課 而且’亦可採用下述方法：在上述發晶圓端面、以及 上述碎晶圓背面中的自最外周部朝向晶圓直徑方向中心 距離與晶圓直徑尺寸之比為〇〜3/3〇〇以内的範圍中，大小 大於等於2 //m的LPD小於等於1〇個。 本發明的碎晶圓的製造方法，是將梦晶圓進行鏡面加 工之後，提供給具有掃描f射照射型熱處理步驟的半 元件製程的梦晶圓的製造方法’該掃描雷射照射型 步驟是設為最高溫度大於等於騎於等於 點並且處理時間為1微秒至10毫秒左右為止的條件。 本發明的碎晶圓的製造方法包括： ’ 晶圓準備步驟，*單晶進行切片並進行表面處理； 緣部狀態設定步驟’對晶圓緣部狀態進行設定；’ 7 201018755 檢查步驟，對發晶圓端面以及背面所存在的劃痕進行 檢查，以及 判定步驟，在上述檢查步驟的結果中，將滿足下述判 定基準（1)的晶圓判定為合格，將不滿足的晶圓判定為不 合格’藉此，解決了上述課題。 判定基準（1)是，在上述矽晶圓端面、以及上述矽 晶圓背面中的自最外周部朝向晶圓直徑方向中心的距離與 晶圓直徑尺寸之比為〇〜3/300以内的範圍中，大於等於 10 //m的劃痕已被排除。 、 ❹ 再者，上述緣部狀態設定步驟是根據提供上述準備步 驟中所準備的梦晶圓的半導體元件製程中的上 照射型熱處理步驟而要求。 雷射 進而’在上述檢查步驟中’當在上述梦晶圓端面、以 及上述發晶圓背面中的自最外周部朝向晶圓直徑方向中心 的距離與晶圓直徑尺寸之比為Q〜3/3⑼以内的範圍中大 小於等於10個時，可判定為滿 ❹ 屋晶準備辣村包括切“層成旗的 支持ίίίΐί賴步财，有時將晶輯上树晶圓的 ，持位置μ為，自上财晶圓背面最外 r5=:二離與晶_尺寸之比成為大:二 .5/300且小於等於6/300的範圍的位置。 在本發明中，較好的是包括將發晶圓背面的研磨裕度 201018755 設為大於等於1 _且小於等於3 _的研磨㈣。 在本發^中’可將±紗晶_氧濃度Qi設定為大 =等於5xl〇 at〇ms/cm3且小於等於·〇17 (Old-ASTM)。 本發明的#晶圓可藉由上述的任-項所述之發 的製造方法而製造。[Patent Document 1] Japanese Patent Laid-Open Publication No. 2006-505953 [Patent Document 2] Japanese Patent No. 4001602. However, in the prior wafer, the millisecond annealing towel such as the above-mentioned LSA having high stress is thus burdened. There is a possibility that the wafer will have a rhyme. Especially in the vicinity of the outermost periphery of a laser scanning wafer, sometimes the wafer may be broken, so there is a demand to improve such problems. SUMMARY OF THE INVENTION The invention has been made in the above circumstances, and aims to provide a wafer. The U-annealed millisecond annealing towel still has a high rupture at the extreme temperature) and the temperature in the treatment is in the middle of the heat treatment:: square == crystal 5 201018755 J^ Since the stress generation state in the DOUpil circle is different, countermeasures against cracking corresponding to the heating methods are required. Therefore, in order to prevent the wafer from being broken during the heat treatment under these conditions, the relationship between the scratches and the cracks on the surface of the wafer and the occurrence of cracking is investigated. As a result, it has been found that, as in the examples described later, there is a relationship between the size of the scratch (crack 'crack) existing in the edge portion of the wafer, the position thereof, and the processing temperature. The germanium wafer of the present invention is subjected to mirror processing, and is supplied to a germanium wafer having a process of scanning a laser irradiation type heat treatment step, and the scanning laser irradiation type heat treatment step is set to a maximum temperature of 1100 or more. The condition that °c is less than or equal to the melting point of cerium and the treatment time is from about i microseconds to about 1 millisecond. In the tantalum wafer of the present invention, scratches of 10 or more which are causes of cracking of the tantalum wafer in the scanning laser irradiation type heat treatment step are excluded. The above-mentioned scratches of 10 or more are excluded in that the ratio of the distance from the outermost peripheral portion toward the center of the wafer straight center and the size of the crystal κ diameter in the wafer end face and the back surface of the dream wafer is 0~ With the above range of 3/300, the above problem is solved by this configuration. In the present invention, it is more preferable that the inner surface of the Shishi wafer and the outermost peripheral portion of the back surface of the Shihua wafer are three axes toward the center of the wafer, and the size of the inner standard towel is 2 or more. LpD of _ (light spot defect is less than or equal to 10) The oxygen concentration 〇i of the above-described tantalum wafer of the present invention can be set to 5 χ 201018755 J^JOUpu. 10 atoms/cm3 and less than or equal to 2〇χ1〇π at_/cm3 ( 〇 id 而且 ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' 本 本 本 本 本 本 本 本 本 本 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体The condition of the laser irradiation type heat treatment (4) is that the condition that the maximum temperature is greater than or equal to the temperature and is less than or equal to the melting point of the material and the processing is _ is micro-light iq right. The dream rupture occurs in the above-described scanning laser irradiation type heat treatment step. The cause of the scratch of 10 _ or more, the ratio of the distance from the outermost peripheral portion toward the center of the wafer diameter direction and the wafer grip size in the end face of the crystal garden and the back surface of the above-mentioned stone garden is 〇~3 Within /3〇〇 The above-mentioned lesson is solved, and the following method can also be used: the center distance from the outermost peripheral portion toward the wafer diameter direction and the wafer diameter size in the wafer end face and the back surface of the chip. In the range of 〇~3/3〇〇, the LPD having a size of 2/m or more is less than or equal to 1 。. The method for manufacturing the shredded wafer of the present invention is to perform mirror processing on the dream wafer. A method of manufacturing a dream wafer provided with a half-element process of a scanning f-irradiation type heat treatment step of the scanning laser irradiation type step of setting the maximum temperature to be equal to or greater than the riding point and processing time of 1 microsecond to 10 milliseconds Conditions for the left and right. The method for manufacturing the chip according to the present invention includes: 'wafer preparation step, * single crystal is sliced and surface treated; edge portion setting step' sets the edge state of the wafer; ' 7 201018755 In the inspection step, the scratches on the end face and the back surface of the wafer are inspected, and the determination step is performed. In the result of the above inspection step, the following criterion is satisfied. 1) The wafer is judged to be acceptable, and the unsatisfied wafer is judged to be unsatisfactory. Thus, the above problem is solved. The criterion (1) is in the end face of the tantalum wafer and the back surface of the tantalum wafer. In the range from the outermost peripheral portion to the center of the wafer diameter direction to the wafer diameter size in the range of 〇~3/300, scratches of 10 // m or more have been excluded. ❹ Furthermore, the above edge The portion state setting step is required according to an upper illumination type heat treatment step in the semiconductor element process for providing the dream wafer prepared in the above preparation step. The laser is further 'in the above inspection step' when on the end face of the dream wafer, and When the ratio of the distance from the outermost peripheral portion toward the center of the wafer diameter direction to the wafer diameter size in the rear surface of the wafer is 0 to 3/3 (9), the size is equal to or greater than 10, and it can be determined that the room is full. Preparing the spicy village includes cutting the support of the layered flag. ίίίΐί Laibucai, sometimes the crystal is placed on the tree wafer, holding the position μ, from the outermost surface of the wafer on the back r5=: the ratio of the two to the crystal _ size becomes Big: two.5/300 and small At a position equal to the range of 6/300. In the present invention, it is preferable to include a grinding margin (4) of a polishing margin 201018755 on the back side of the wafer to be greater than or equal to 1 _ and less than or equal to 3 _. In the present invention, the ±yarn crystal_oxygen concentration Qi can be set to be large = equal to 5xl 〇 at〇ms/cm3 and less than or equal to 〇17 (Old-ASTM). The # wafer of the present invention can be produced by the production method described in any of the above items.
圓 *本發明㈣晶圓’是在經鏡面加1之後，被提供給具 φ 有掃描雷射照射型熱處理步驟的半導體元件製程的石^ 圓’該f描雷射照射型熱處理步驟是設為最高溫度大於等 於1100 C且小於等於梦的溶點並且處理時間| i微秒至 毫秒左右為止的條件。 本發明的梦晶圓中，在上述掃描雷射照射型熱處理步 驟中成為發晶圓破裂發生原因的大於等於1G _的劃 痕j在上述珍晶圓端面、以及上述梦晶圓背面中的自最外 周部朝向晶圓直徑方向中心的距離與晶圓直徑尺寸之比為 0〜曰3/300以内的範圍中被排除。具有此種構成的本發明的 夕曰曰圓在具有LSA等的褅描雷射照射型熱處理步驟的半 導體元件製程中可防止破裂發生。 =5 nm節點（hP65)中，於金屬氧化物半導體場效應 電日日體（Metal-Oxide-Semiconductor Field-EffectCircle * The present invention (four) wafer 'is a stone round process which is supplied to a semiconductor device having a scanning laser irradiation type heat treatment step after being added by a mirror 1. The f-laser irradiation type heat treatment step is set to The condition that the maximum temperature is greater than or equal to 1100 C and is less than or equal to the melting point of the dream and the processing time is from i microseconds to about milliseconds. In the dream wafer of the present invention, in the scanning laser irradiation type heat treatment step, the scratch j of 1 G _ or more which is the cause of the occurrence of wafer breakage is in the end surface of the above-mentioned wafer and the back surface of the above-mentioned dream wafer. The ratio of the distance between the outermost peripheral portion toward the center of the wafer diameter direction and the wafer diameter size is within a range of 0 to 曰3/300. The 曰曰 曰曰 circle of the present invention having such a configuration can prevent cracking from occurring in a semiconductor element process having a scanning laser irradiation type heat treatment step of LSA or the like. Metal oxide semiconductor field effect in the 5 nm node (hP65). Metal-Oxide-Semiconductor Field-Effect
Transist^ ’ M0SFET )的退火步驟中，與先前的rta相比， 進打更高溫、更短時間的退火。其原因在於，在圖3所示 的極淺接面Mex中，必需實現圖4所示的箱形的雜質分佈 (profile)，即，必需實現極淺接面Mex區域内的雜質濃 201018755 J250Upit 度的均⑽與邊界上的陡M的變化狀態。圖3所示的極淺 接面MeX，疋指鄰接於以符號Mos所示的MOSFET的源 極Ms'及極Md ’且自基板表面算起的深度（接面深度）In the annealing step of Transist^' MOSFET, it is a higher temperature and shorter time annealing than the previous rta. The reason for this is that in the extremely shallow junction Mex shown in FIG. 3, it is necessary to realize the box-shaped impurity profile shown in FIG. 4, that is, it is necessary to realize the impurity concentration in the extremely shallow junction Mex region 201018755 J250Upit degree. The mean state of (10) and the steep M on the boundary. The extremely shallow junction MeX shown in Fig. 3, the finger is adjacent to the source Ms' and the pole Md' of the MOSFET indicated by the symbol Mos and the depth (join depth) from the substrate surface
Xi淺至20 nm左右的雜質擴散區域。即，高溫、短時間的 退火如上所述是為了藉由較高的加熱溫度來將注入的雜質 充分活化崎低電阻，㈣，藉由較短的域時間來抑制 雜質的不必要的擴散，以避免已活化的雜質發生失活 (deactination )而進行。 如此，為了實現45 nm節點（hp65)所要求的低於20 nm的接面深度Xi，而進行FLA或lsa等。fla中，將 b曰曰圓預先升溫至大於等於4_則、於等於6W：的初始 :皿，再使用Xe閃光燈等的短波長的絲對日日日圓整個面 進打光照射，以毫料位賴處理時間來僅將晶圓極表層 急速加熱、驟冷至90代〜13贼左右為止。以中將 晶圓於熱板上預絲熱至4G(rc〜6⑽。⑽初始溫度再照 射連續振1雷射來對晶圓進行光點掃描，藉此以微秒至毫 秒的熱處理時間來將晶圓急速加熱、驟冷至大於等於膽 C且為矽的熔點附近為止。 μ A中，選擇可實現維持光晕狀㈤。）的 =濃度》佈特性，減少接面⑽，抑制閘極舰，降低 源極、沒極的寄生電阻，亦抑侧極的空乏化的處理條件。 於設為如上所述的條件的FLA中，在執 ^生的内部應力將達到5〇〜15G Mpa的位準（_『)。如 此’於對晶®整個面同時進行加細FLA巾可如此般計 201018755 算出内部應力。相對地，於藉由雷射照射來對晶圓進行局 部加熱的LSA中，由於為局部加熱以及是進行雷射掃描^ 加熱位置為移動，因而難以準確地計算出内部應力。田 於FLA中產生的溫度差主要是晶圓厚度方向。與此相 對，當然於LSA中產生的溫度差除了晶圓厚度方向以外， 亦產生在所照射的雷射點的周圍，即，亦產生在晶圓面内 方向。因而可認為，於LSA中，熱處理時晶圓所產生的内 φ 部應力大於FLA的情況。 因而，於LSA中，必需進一步防止破裂發生。 而且，於LSA中獲得如下結果，^當雷射照射位置 到達晶圓緣部附近時，易發生破裂。 本案發明者等人找到了在矽晶圓的製造步驟中可防 止如此之晶圓破裂發生的對策。 在本發明的矽晶圓中，在上述矽晶圓端面、以及自上 述石夕晶圓背面最外周部朝向晶圓直經方向中心為3聰以 _範时，大小大於等於2輝的咖，!、於等於1〇個。 藉由具有該構成的本發明的砍晶圓，可實現根據提供上述 石夕晶圓的半導體元件製程中的上述掃描雷射照射型熱處理 步驟而要求的、可防止破裂發生的晶圓緣部狀態。 本發_上述〜日日_氧濃度〇i可設為大於等於& 10 atoms/cm 且小於等於 2〇xl〇17at〇ms/cm3(〇id.AsTM)。 而且’本發明的梦晶圓的製造方法，是將石夕晶圓進行 f面加工之後’提供給具有掃描雷射照射型熱處理步驟的 半導體元件製程的梦晶圓的製造方法，該掃描雷射照射型 11 201018755 熱處理步敲設為最⑼度大料於UGGt：且小於等於 =的熔點並且處理時間為i微秒至i⑻毫秒左右為止的條 仵。 ^明的梦晶圓的製造方法中，將在上述掃插雷射照 射里‘、、、處理步财成切晶圓破裂發生的大於等於 10㈣的劃痕，在上述發晶圓端面、以及上述發晶圓背 /面中的自最外周部朝向晶圓直徑方向中心的距離與晶圓直 徑尺寸之比為〇〜3/300以内的範圍中予以排除。藉由該 成’於直徑300 mm的矽晶圓中，可製造即使 ❿ LSA步驟的元件製造步驟亦可防止晶圓破裂發生的^ 圓。具體而言’於提供給元件步驟的前階段的研磨步驟中， 對處理條件進行設定以成為上述的晶圓緣部狀態，藉此能 製造可防止晶圓破裂發生的梦晶圓。 而且，亦可適應於除此以外的口徑的晶圓，例如亦可 適應於直徑450 mm的晶圓。 而且，在上述矽晶圓端面、以及上述矽晶圓背面中的 自最外周部朝向晶圓直徑方向中心的距離與晶圓直捏尺寸 ❿ 之比為0〜3/300以内的範圍中，大小大於等於2 "爪的 LPD可小於等於10個。藉由可該構成，可實現根據上述 掃描雷射照射型熱處理步驟而要求的、可防止破裂發生的 晶圓緣部狀態。上述掃描雷射照射型熱處理步驟是提供矽 晶圓的半導體元件製程所具有的步驟。 ^ 本發明的矽晶圓的製造方法，是將矽晶圓進行鏡面加 工之後，提供給具有掃描雷射照射型熱處理步驟的半導體 12 201018755 元件製程的矽晶圓的製造方法，該掃描雷射照射型熱處理 步驟是設為最高溫度大於等於11〇〇〇C且小於等於矽的熔 點並且處理時間為1微秒至100毫秒左右為止的條件。 本發明的矽晶圓的製造方法包括： 晶圓準備步驟，由單晶進行切片並進行表面處理； 緣部狀態設定步驟，對晶圓緣部狀態進行設定；Xi is as shallow as about 20 nm. That is, the high-temperature, short-time annealing is as described above in order to sufficiently activate the injected impurities by the higher heating temperature, and (4) suppress the unnecessary diffusion of impurities by a short domain time. It is carried out by avoiding the deactivation of activated impurities. Thus, FLA or lsa is performed in order to achieve a junction depth Xi of less than 20 nm required at the 45 nm node (hp65). In fla, the b曰曰 circle is preheated to 4 or more, and is equal to 6W: the initial: dish, and then the short-wavelength wire such as Xe flash is used to illuminate the entire surface of the Japanese yen. Based on the processing time, only the surface layer of the wafer is rapidly heated and quenched to about 90 to 13 thieves. The wafer is pre-wired to 4G on a hot plate (rc~6(10). (10) The initial temperature is further irradiated to the continuous-laser 1 laser to perform spot scanning on the wafer, thereby taking a heat treatment time of microseconds to milliseconds. The wafer is rapidly heated and quenched to a temperature equal to or higher than the gallbladder C and is near the melting point of the crucible. In μ A, the selection can be achieved to maintain the halo shape (five), the concentration of the fabric, reduce the junction (10), and suppress the gate ship. It reduces the parasitic resistance of the source and the immersion, and also suppresses the treatment conditions of the side electrode. In the FLA set as described above, the internal stress of the actuator will reach the level of 〇5 to 15G Mpa (_『). Therefore, the FLA towel can be thinned at the same time on the entire surface of the wafer. 201018755 Calculate the internal stress. In contrast, in an LSA in which the wafer is locally heated by laser irradiation, it is difficult to accurately calculate the internal stress because the local heating and the laser scanning are performed at the heating position. The temperature difference generated by the field in the FLA is mainly the wafer thickness direction. Conversely, of course, the temperature difference generated in the LSA is generated around the irradiated laser spot in addition to the thickness direction of the wafer, that is, also in the in-plane direction of the wafer. Therefore, it can be considered that in the LSA, the internal φ stress generated by the wafer during heat treatment is larger than that of the FLA. Therefore, in the LSA, it is necessary to further prevent the occurrence of cracking. Moreover, the following result is obtained in the LSA, and when the laser irradiation position reaches the vicinity of the edge of the wafer, cracking easily occurs. The inventors of the present invention have found a countermeasure against the occurrence of such wafer cracking in the manufacturing process of the germanium wafer. In the tantalum wafer of the present invention, the end face of the tantalum wafer and the coffee from the outermost peripheral portion of the back surface of the Shihua wafer toward the center of the wafer straight direction are 3 or more. !, is equal to 1〇. According to the chopped wafer of the present invention having such a configuration, it is possible to realize a wafer edge state which is prevented from occurring in accordance with the scanning laser irradiation type heat treatment step in the semiconductor element manufacturing process of the above-described day-night wafer. . The present invention may be set to be equal to or greater than & 10 atoms/cm and less than or equal to 2〇xl〇17at〇ms/cm3 (〇id.AsTM). Further, the method for manufacturing the dream wafer of the present invention is a method for manufacturing a dream wafer which is supplied to a semiconductor device having a scanning laser irradiation type heat treatment step after performing a f-plane processing on the stone substrate, the scanning laser Irradiation type 11 201018755 The heat treatment step is set to the maximum (9) degree of the UGGt: and the melting point of less than or equal to = and the treatment time is from i microseconds to i (8) milliseconds. In the method for manufacturing a dream wafer, in the above-described scanning laser irradiation, a scratch of 10 (four) or more is generated in the wafer rupture, and the wafer end surface and the above The ratio of the distance from the outermost peripheral portion toward the center of the wafer diameter direction to the wafer diameter dimension in the wafer back/face is excluded within a range of 〇3/300. By forming the wafer in a 300 mm diameter germanium wafer, it is possible to manufacture a wafer which prevents wafer breakage even if the component manufacturing step of the LSA step is performed. Specifically, in the polishing step provided in the previous stage of the element step, the processing conditions are set so as to be in the above-described wafer edge state, whereby a dream wafer capable of preventing wafer breakage can be produced. Moreover, it is also applicable to wafers of other diameters, for example, to wafers having a diameter of 450 mm. Further, in the range of 0 to 3/300, the ratio of the distance from the outermost peripheral portion toward the center of the wafer diameter direction in the end face of the tantalum wafer and the back surface of the tantalum wafer is 0 to 3/300 or less. The LPD greater than or equal to 2 "claws may be less than or equal to 10. According to this configuration, it is possible to realize the state of the edge portion of the wafer which is required to prevent cracking, which is required in accordance with the above-described scanning laser irradiation type heat treatment step. The above scanning laser irradiation type heat treatment step is a step of providing a semiconductor device process for a germanium wafer. The method for manufacturing a tantalum wafer according to the present invention is a method for manufacturing a tantalum wafer which is subjected to mirror processing of a tantalum wafer and then supplied to a semiconductor 12 201018755 device having a scanning laser irradiation type heat treatment step, the scanning laser irradiation The heat treatment step is a condition in which the maximum temperature is 11 〇〇〇C or more and the melting point is less than or equal to 矽 and the treatment time is about 1 microsecond to 100 milliseconds. The method for manufacturing a tantalum wafer of the present invention includes: a wafer preparation step of slicing and performing surface treatment from a single crystal; and a margin state setting step of setting a wafer edge state;
檢查步驟，對石夕晶圓端面以及背面所存在的劃痕進 檢查；以及 刊疋步驟 〜、------…你工延揿笪步驟的結果中，將滿足下述判 定基準^晶圓判定為合格，將不滿足的晶圓判定為不合格。 判定基準是，在上述石夕晶圓端面、以及上述石夕晶圓背 ，中的自最外周部朝向晶圓直徑方向中^的距離與晶圓直 寸之比為0〜3/300以内的範圍中，大於等於10㈣ 、Ji痕已被排除。如此，由檢查步驟的結果來判定合格、 H，並將不滿足基耗晶圓料去除，藉此可提供具 驟導體70件製財的上述_雷射騎型熱處理步 t求的、可防止破裂發生的晶圓緣部狀態时晶圓。 處理^可、汲極擴散區域_f注人後的退火 且將因㈣ί 丁使至梦晶圓的雜質得到電性活化，並 亦即，在可實結晶缺陷予以去除的熱處理。 件下，===雜質分佈相近的狀態的條 ::緣部發生破裂的可能性較高的二 13 201018755 ^ζ^ουριι 進而’在上述檢查步驟中，當在上述矽晶圓端面、以 及上述矽晶圓背面中的自最外周部朝向晶圓直徑方向中心 的距離與晶圓直徑尺寸之比為0〜3/300以内的範圍中，大 小大於等於2 //m的LPD小於等於1〇個時，可判定為滿 足上述判定基準。藉由如此之判定，可判別能防止上述破 裂的晶圓。 而且，於表面成膜有矽磊晶層的磊晶晶圓在磊晶成長 過程中，晶圓與環（ring)狀的晶座的接觸不可避免。由 於該接觸，晶圓與晶座緊貼，從而局部性地導致反應氣體 流動因此而固著。於磊晶成長後，自晶座抬起晶圓時，該 固著有時會剝落’從而導入劃痕（Crack，裂紋）。在本發 明的上述晶圓準備步驟包括使矽磊晶層成膜的磊晶成膜步 驟的情況下， 於上述磊晶成膜步驟中，晶座對上述矽晶圓的支持位 置可設定為，自上述矽晶圓背面最外周部朝向晶圓直徑方 向中心的距離與晶圓直徑尺寸之比成為15/3〇〇〜6/3⑻的 範圍的位置。藉由該構成，可防止上述劃痕成為上述LSA 步驟中的破裂原因。 曰具體而言，於使磊晶層成膜時，矽晶圓被載置於與該 晶圓呈同心狀且直徑尺寸小於晶圓的可視為環的晶座上， 而進行磊晶成膜處理的加熱。該晶座所接觸的範圍被設為 設定上述支持位置的範圍。 於本發明中’包括將發晶圓背面的研磨裕度設為大於 於1 且小於等於3 的研磨步驟。藉由該研磨 201018755 步驟’即使於蟲晶層成膜時導入有劃痕的情況下，亦可去 除該劃痕而排除其影響，從祕LSA步驟中可防止晶圓破 裂的發生。 於本發明中，可將上述石夕晶圓的氧濃度〇i設定為大 於等於 5xl017 atoms/cm3 且小於等於 2〇χ1〇17 at〇ms/cm3 (Old-ASTM)。 本發明的石夕晶圓可藉由上述的任一項所述之梦晶圓 0 的製造方法而製造。 [發明之效果] 根據本發明，可提供一種在具有LSA等的掃描雷射照 射型熱處理步驟的半導體元件製程中能防止破裂發生的矽 晶圓。 為讓本發明之上述特徵和優點能更明顯易懂，下文特 舉實施例，並配合所附圖式作詳細說明如下。 【實施方式】 以下，根據圖式說明本發明的矽晶圓及其製造方法的 參 第一實施形態。 圖1是表示本實施形態的矽晶圓及其製造方法的流程 圖。 本實施形態的矽晶圓的製造方法是將矽晶圓進行鏡 面加工之後，提供給具有掃描雷射照射型熱處理步驟的半 導體元件製程的梦晶圓的製造方法，該掃描雷射照射型熱 處理步驟疋設為最南溫度為大於等於ll〇〇〇C且小於等& 矽的熔點並且處理時間為1微秒至100毫秒左右為止的條 15 201018755 件。本實施形態的矽晶圓的製造方法如圖1所示，包括具 有研磨步驟S12的晶圓準備步驟S1 ;緣部狀態設定步驟 S2 ;檢查步驟S3 ;判定步驟S4 ;以及具有Lsa等的熱處 理步驟S52的元件製造步驟S5。 圖1所示的晶圓準備步驟S1是藉由柴氏 (Czochralski，CZ)法，自砍溶液拉製石夕單晶，並將該石夕 單晶藉由切片（slice)加工以及倒稜、研削、研磨、清洗 等的表面處理而準備矽晶圓的步驟。該晶圓準備步驟S1 具有作為精加工的研磨步騍S12。 ® 於該晶圓準備步驟S1的矽單晶拉製時，將石夕晶圓的 氧濃度Oi設疋為大於等於5xl017 atoms/cm3且小於等於20 xlO17 atoms/cm3 (Old · ASTM)。矽晶圓的氧濃度〇i更好 的是大於等於7xl〇17 atoms/cm3且小於等於ΐ5χι〇η atoms/cm3 ° 圖1所示的緣部狀態設定步驟S2是對晶圓緣部狀態 進行設錢㈣，該晶®緣雜態是根據提供晶®準備步 驟S1中所準備的石夕晶圓的後步驟的、半導體元件製造步 ❹ 驟S5中的LSA等的掃描雷射照射型熱處理步驟S52而要 求。掃描雷射照射型熱處理步驟S52中的、供經過鏡面加 工的石夕晶圓的熱處理的具體條件是設為，最高溫度大於等 於1100 C且小於等於石夕的熔點，並且處理時間為i微妙至 100毫秒左右為止的條件。在賴處理步驟 S52中，對可 狀雜ί晶_部的狀態進行設定。該晶圓緣部的 〜、 吕是，在上述掃描雷射照射型熱處理步驟中成 16 201018755 為發晶圓破裂發生原因的大於等於10 ym的劃痕被排除 的狀態。具體而言，如圖6所示，在上述矽晶圓w的端面 wt及上述矽晶圓背面Wr中的自最外周部Wrt朝向晶圓直 徑方向Wo中心的距離r、與圖6中以符號2R所示的晶圓 直板尺寸之比為0〜3/300以内的範圍中，大於等於1〇以 111的劃痕被排除。 此處’矽晶圓可適應直徑尺寸直徑大於等於3〇〇 mm φ 且小於等於45〇mm左右的梦晶圓。 再者，本實施形態中，在緣部狀態設定步驟S2中， 於設為對象的熱處理步驟S52中，進行圖3所示的對源 極、汲極擴散區域Mex的雜質注入後的退火處理。該退火 處理是在同時實現使注入的雜質得到電性活化與去除因雜 質的注入而產生的結晶缺陷的條件下進行。 所謂電性活化，是指成為導電率提高的狀態。通常， 如圖5之（a)所示，藉由離子注入而佈植的雜質僅無規地 (random)存在於矽結晶中，而成為電性非活性的 ® 率。所謂電性活化，是指藉由退火處理來賦予熱能量，藉 此由該電性非活性的狀態轉變成如圖5之（b)所示般，雜 質移動至晶格點的位置而得到電性活化，從而導電率得到 提高的狀態。 而且，如圖5之（a)所示，當雜質被注入時，原本 矽原子呈規則性排列的單晶矽因注入的能量而成為具有原 子的規則性排列被打亂的晶格缺陷的狀態。所謂去除因雜 質的注入而產生的結晶缺陷，是指藉由退火處理來賦予熱 17 201018755 如圖5之(b)所示，矽原子重新排列而成為無 ”、、生洩漏電流的原因的結晶缺陷的狀態。 ’’、 前者的雜質的活化時，雜質到達矽的晶格點為止 動距離較短’為在原子間（晶格間）_移_程度，、活 =耗的時間雜短即可，但需要峰值溫度超過1嶋。C的 尚溫。即，高溫而時間常數較小。 、 與此相對’後者时單晶排列的時間常數較大。Inspect the steps to check the scratches on the end face and back of the Shixi wafer; and the results of the steps ~, ------...the steps of your work delay, the following criteria will be met. The circle was judged to be acceptable, and the wafer that was not satisfied was judged to be unacceptable. The criterion is that the ratio of the distance from the outermost peripheral portion toward the wafer diameter direction to the wafer straightness in the above-mentioned Shixi wafer end face and the above-mentioned Shihua wafer back is 0 to 3/300 or less. In the range, greater than or equal to 10 (four), Ji marks have been excluded. In this way, the result of the inspection step is judged as pass, H, and the base loss wafer material is not removed, thereby providing the above-described _laser riding type heat treatment step for securing 70 pieces of the sudden conductor, which can be prevented. The rupture occurs when the wafer is in the edge state of the wafer. The treatment can be performed after the annealing of the drain diffusion region _f and the impurities of the dream wafer are electrically activated, that is, the heat treatment for removing the solid crystal defects. Under the condition, the === state in which the impurity distribution is similar: the possibility that the edge is broken is higher. 13 13 201018755 ^ζ^ουριι Further, in the above inspection step, when the above-mentioned silicon wafer end face, and the above In the range from 0 to 3/300 in the ratio of the distance from the outermost peripheral portion toward the center of the wafer diameter direction to the wafer diameter dimension in the back surface of the wafer, the LPD having a size of 2 // m or more is less than or equal to 1 LP At this time, it can be determined that the above criterion is satisfied. By such a determination, it is possible to discriminate the wafer which can prevent the above-mentioned cracking. Moreover, in an epitaxial wafer in which a germanium epitaxial layer is formed on the surface, contact between a wafer and a ring-shaped crystal seat is unavoidable during epitaxial growth. Due to the contact, the wafer is in close contact with the crystal holder, thereby locally causing the reaction gas to flow and thus being fixed. After the epitaxial growth, when the wafer is lifted from the crystal holder, the fixation may peel off and introduce scratches (cracks). In the above-described wafer preparation step of the present invention, the epitaxial film formation step of forming a germanium epitaxial layer into a film, in the epitaxial film formation step, the support position of the crystal pad to the germanium wafer can be set to The ratio of the distance from the outermost peripheral portion of the back surface of the tantalum wafer toward the center in the wafer diameter direction to the wafer diameter size is in the range of 15/3 〇〇 to 6/3 (8). With this configuration, it is possible to prevent the above-mentioned scratch from being the cause of the breakage in the LSA step described above. Specifically, when the epitaxial layer is formed into a film, the germanium wafer is placed on a crystal seat that is concentric with the wafer and has a diameter smaller than that of the wafer, and is subjected to epitaxial film formation. Heating. The range in which the crystal holder is in contact is set to a range in which the above-described support position is set. In the present invention, 'the grinding step of setting the polishing margin on the back side of the wafer to be greater than 1 and less than or equal to 3. By the polishing 201018755 step ' even if scratches are introduced when the insect crystal layer is formed, the scratches can be removed to eliminate the influence, and the occurrence of wafer breakage can be prevented from the secret LSA step. In the present invention, the oxygen concentration 〇i of the above-mentioned Shihua wafer can be set to be greater than or equal to 5xl017 atoms/cm3 and less than or equal to 2〇χ1〇17 at〇ms/cm3 (Old-ASTM). The Shiyue wafer of the present invention can be produced by the method of manufacturing the Dream Wafer 0 according to any of the above. [Effects of the Invention] According to the present invention, it is possible to provide a ruthenium wafer capable of preventing cracking from occurring in a semiconductor device process having a scanning laser irradiation type heat treatment step of LSA or the like. The above described features and advantages of the present invention will become more apparent from the description of the appended claims. [Embodiment] Hereinafter, a first embodiment of a tantalum wafer and a method of manufacturing the same according to the present invention will be described with reference to the drawings. Fig. 1 is a flow chart showing a tantalum wafer and a method of manufacturing the same according to the embodiment. The method for manufacturing a tantalum wafer according to the present embodiment is a method for manufacturing a dream wafer which is subjected to mirror processing of a tantalum wafer and then supplied to a semiconductor device having a scanning laser irradiation type heat treatment step, and the scanning laser irradiation type heat treatment step疋 is set to a strip 15 201018755 where the southernmost temperature is greater than or equal to ll 〇〇〇 C and less than the melting point of & 并且 and the processing time is from 1 microsecond to 100 milliseconds. As shown in FIG. 1, the method for manufacturing a tantalum wafer according to the present embodiment includes a wafer preparation step S1 having a polishing step S12, an edge portion setting step S2, an inspection step S3, a determination step S4, and a heat treatment step having Lsa or the like. The component manufacturing step S5 of S52. The wafer preparation step S1 shown in FIG. 1 is a method of drawing a stone single crystal from a chopping solution by a Czochralski (CZ) method, and processing the stone bed by slice processing and chamfering, The step of preparing a silicon wafer by surface treatment such as grinding, polishing, and cleaning. This wafer preparation step S1 has a polishing step S12 as a finishing. When the germanium single crystal is drawn in the wafer preparation step S1, the oxygen concentration Oi of the Shihua wafer is set to be 5xl017 atoms/cm3 or more and 20xlO17 atoms/cm3 (Old · ASTM). The oxygen concentration 〇i of the germanium wafer is more preferably 7x1〇17 atoms/cm3 or more and less than or equal to χ5χι〇η atoms/cm3°. The edge state setting step S2 shown in FIG. 1 is to set the edge state of the wafer. (4), the crystal edge impurity state is a scanning laser irradiation type heat treatment step S52 of the LSA or the like in the semiconductor element manufacturing step S5 according to the subsequent step of providing the crystal wafer preparation step prepared in the step S1 of the crystal preparation step S1. And ask. The specific condition for the heat treatment of the mirror-processed Shi Xi wafer in the scanning laser irradiation type heat treatment step S52 is such that the maximum temperature is 1100 C or more and less than or equal to the melting point of Shi Xi, and the processing time is i subtle to The condition is about 100 milliseconds. In the processing step S52, the state of the visible portion is set. In the scanning laser irradiation type heat treatment step, the scratches of the wafer edge portion are in a state of 16 201018755, and the scratches of 10 μm or more for the occurrence of the wafer cracking are excluded. Specifically, as shown in FIG. 6, the distance r from the end surface wt of the tantalum wafer w and the outermost peripheral portion Wrt of the tantalum wafer back Wr toward the center of the wafer diameter direction Wo, and the symbol in FIG. In the range of the wafer straight plate size indicated by 2R being 0 to 3/300 or less, scratches of 1 or more and 111 are excluded. Here, the wafer can be adapted to a dream wafer having a diameter of 3 〇〇 mm φ or more and a diameter of 45 〇 or less. In the edge portion state setting step S2, the annealing process after the impurity implantation of the source and drain diffusion regions Mex shown in Fig. 3 is performed in the target heat treatment step S52. This annealing treatment is carried out under the conditions of simultaneously achieving electrical activation of the implanted impurities and removal of crystal defects caused by the injection of impurities. The term "electrical activation" refers to a state in which the conductivity is improved. Generally, as shown in (a) of Fig. 5, impurities implanted by ion implantation are only randomly present in the ruthenium crystal, and become an electrically inactive ® ratio. The term "electrical activation" refers to the application of thermal energy by an annealing treatment, whereby the electrically inactive state is changed to a position as shown in FIG. 5(b), and the impurity is moved to the position of the lattice point to obtain electricity. Sexual activation, whereby the conductivity is improved. Further, as shown in (a) of FIG. 5, when impurities are implanted, the single crystal germanium in which the original germanium atoms are regularly arranged becomes a state of lattice defects in which the regular arrangement of atoms is disturbed due to the energy of the implantation. . The removal of the crystal defects caused by the implantation of the impurities refers to the crystallization of the cause of the leakage current by the annealing treatment to impart heat 17 201018755 as shown in FIG. 5( b ). The state of the defect. '', the activation of the former impurity, the short distance of the impurity reaching the lattice point of the ' 'is between the atoms (between the crystal lattices) _ shift _ degree, the life = the time of consumption is short However, it is required that the peak temperature exceeds 1 嶋. The temperature of C is high, and the time constant is small. In contrast, the time constant of the single crystal arrangement is large.
在於，規則性排列被破壞的原子移動至重新排列為止的 == 且，再結晶化須耗費較長時間，因此結晶缺 陷的去除需要低溫長時間的退火。 教虎it用於同時控制時間常數不同的現象的熱處理即 S52的條件較為嚴格。當以雜質活化為優先而 度必需使處時，為了將雜赚抑制為最小限In other words, the atom whose regular arrangement is destroyed moves to == after realignment, and recrystallization takes a long time, so the removal of the crystal defect requires annealing at a low temperature for a long time. The conditions for heat treatment, that is, S52, which teaches tigers to simultaneously control phenomena with different time constants, are more stringent. When it is necessary to give priority to the activation of impurities, in order to minimize the miscellaneous profit
t作為結果結晶缺陷的去除並不充分，M0SFETt as a result of the removal of crystalline defects is not sufficient, MOSFET
= 時另一方面’當以結晶缺陷去除為優先 長時’雖缺陷得到復原（_㈣而結 復’⑽質擴散變得劇烈，易引起短通道效應 Uhort channel effect)。 作用即^理步驟S52要求同時滿足如此之二個相反的 接面M 祕有高雜㈣度與淺舰深度的極淺 S52的二二:間常數不同的二個熱現象。熱處理步驟 S52的條件與先前的RTA相比， 局，與賴處轉 18 201018755 進而’晶圓緣部狀態設定步驟中的緣部狀態是如後述 的實施例般，設定為當處理溫度（峰值溫度）為1100乞時， 在端面上無大於10 Am的劃痕的狀態。且上述緣部狀態 是設定為，當最高到達溫度（處理溫度）為12〇〇〇c時，在 端面及自背面最外周算起徑方向1/300的範圍内不存在大 於10 /zm的劃痕的狀態。且上述緣部狀態是設定為，當 最南到達溫度（處理溫度）為1300°C時，在端面及自背面 Φ 最外周算起徑方向3/30〇的範圍内不存在大於10 //m的 劃痕的狀態。且上述緣部狀態是設定為，當最高到達溫度 (處理溫度）為1100。(：時，在端面及自背面最外周算起徑 方向1/300的範圍内不存在大於30 的劃痕的狀態。 且上述緣部狀態是設定為，當最高到達溫度（處理溫度） 為1200°C時，在端面及自背面最外周算起徑方向3/3⑻的 範圍内不存在大於30 的劃痕的狀態。且上述緣部狀 態是設定為，當最高到達溫度（處理溫度）為13〇〇π時， 在端面及自背面最外周算起徑方向3/300的範圍内不存在 ® 大於30 Mm的劃痕的狀態。 再者，當最高到達溫度（處理溫度）為1〇8〇它時，即 使存在大於10 am的劃痕亦不會發生破裂。而且，在lsa 的情況下，在自背面最外周算起大於徑方向11/300的範 圍，即，在自背面最外周算起較徑方向11/300的範圍更靠 晶圓的中心側即使存在劃痕亦不會發生破裂。因此 ，該些 條件可由晶圓緣部狀態設定而除外。 圖1所示的檢查步驟S3是對矽晶圓端面及背面上存 19 201018755 在的劃痕進行檢查的步驟。具體而言，檢查步驟S3是對 上述梦晶圓端面、以及上述晶圓背面中的自最外周部朝向 晶圓直徑方向中心的距離與晶圓直徑尺寸之比為〇〜3/3〇〇 以内的範圍中，大小大於等於2 /£111的1^1)是否小於等 於10個進行檢查的步驟。作為檢查方法’可使用利用雷射 的晶片缺陷檢測裝置（KLA_Tencor製造，SP4等）或藉 由CCD相機的稱為圖像檢查法的檢查方法。On the other hand, 'when the removal of crystal defects is prioritized, the defect is restored. (_(4) and the combination is repeated. (10) The mass diffusion becomes severe, which is likely to cause a short channel effect). The action step S52 is required to satisfy two thermal phenomena in which the two opposite junctions M have a high miscellaneous (four) degree and a very shallow S52 of the shallow ship depth: the two constants are different. The condition of the heat treatment step S52 is set to be the processing temperature (peak temperature) as in the embodiment described later, compared with the previous RTA, and the edge state in the wafer edge state setting step. When it is 1100 ,, there is no scratch of more than 10 Am on the end face. And the edge state is set such that when the highest reaching temperature (processing temperature) is 12 〇〇〇c, there is no more than 10 /zm in the range of the end face and the 1/300 in the radial direction from the outermost periphery of the back surface. The state of the mark. And the edge state is set such that when the southernmost reaching temperature (processing temperature) is 1300 ° C, there is no more than 10 //m in the range of the end face and the outermost circumference of the back surface Φ from the radial direction of 3/30 起. The state of the scratch. And the above edge state is set such that the highest reaching temperature (processing temperature) is 1100. (: When there is no more than 30 scratches in the range of 1/300 in the radial direction from the outermost circumference of the outermost surface of the back surface, and the above-mentioned edge state is set to be 1200 when the maximum reaching temperature (processing temperature) is 1200. At °C, there is no scratched state of more than 30 in the range of the end face and the outermost circumference of the back surface by 3/3 (8). The edge state is set to be the highest reaching temperature (processing temperature) of 13 When 〇〇π, there is no scratch of more than 30 Mm in the range of the end face and 3/300 in the radial direction from the outermost periphery of the back. Further, when the maximum reaching temperature (processing temperature) is 1〇8〇 In this case, even if there is a scratch of more than 10 am, cracking does not occur. Moreover, in the case of lsa, it is larger than the outermost circumference of the back surface by 11/300 in the radial direction, that is, from the outermost circumference of the back surface. The range of 11/300 in the radial direction is not broken even if there is a scratch on the center side of the wafer. Therefore, these conditions can be excluded by setting the edge state of the wafer. The inspection step S3 shown in Fig. 1 is矽 wafer end face and back side storage 19 201018755 Specifically, the inspection step S3 is that the ratio of the distance from the outermost peripheral portion toward the center of the wafer diameter direction to the wafer diameter dimension in the end face of the dream wafer and the wafer back surface is In the range of 〇~3/3〇〇, 1^1) whose size is greater than or equal to 2/£111 is less than or equal to 10 steps for checking. As the inspection method, a wafer defect detecting device using laser light (manufactured by KLA_Tencor, SP4, etc.) or an inspection method called an image inspection method by a CCD camera can be used.
圖1所不的判定步驟S4是將檢查步驟S3的結果滿足 判定基準⑴的晶_定為合格，*料滿足上述基準的 晶圓判定為不合格的步稀。 判定基準⑴：在上述砍晶圓端面、以及上述發晶圓 背/面中的自最外周部朝向晶圓直徑方向中心的距離與晶圓 直徑尺寸之比為〇〜3/3〇〇以内的範圍中大於等於⑺ m的劃痕已被排除。 βThe determination step S4 shown in Fig. 1 is a step of determining that the result of the inspection step S3 satisfies the determination criterion (1), and that the wafer that satisfies the above criterion is judged to be unqualified. The criterion (1) is that the ratio of the distance from the outermost peripheral portion toward the center of the wafer diameter direction to the wafer diameter dimension in the end face of the chopped wafer and the wafer back surface is less than 3/3 〇〇 Scratches greater than or equal to (7) m in the range have been excluded. β
當在判定步驟S4中舰為不合格時返回晶圓準令 步驟S1的研磨步竭si2，胳m t α 除而復原直至上述基準二晶圓/*面、端面的劃痕側 S3、判定步驟S4。為止，藉此，再次到達檢查步塌 中判定為合格時，將矽晶圓提供至 當在判定步驟S4 元件製造步驟S5。 ㈣行切晶圓上製作45 S5具有LSA等的熱處理步元件製造步 在圖所不的熱處理步驟s52中，利用圖7所示的 20 201018755 射瞬間退火（LSA)裝置來進行瞬間退火。該LSA裝置可 利用微秒〜毫秒級（order)的照射而升溫至1350°C。 作為該雷射瞬間退火（LSA)裝置，可使用作為用於 形成半導體元件的源極/沒極區域或延伸（extension)區域 的矽晶圓基板的瞬間退火處理裝置而使用的、束徑為1〜 50 mm左右的雷射瞬間退火裝置。 該雷射瞬間退火（LSA)裝置1並非對晶圓W整個面 進行加熱。具體而言，如圖7所示，對於光源使用連續振 盪型雷射2 ’經由鏡面6、光束整形光學系統7，對藉由 XY掃描平台3而受到XY掃描的晶圓W局部性地在還原 性氣體、稀有氣體、氮氣環境下進行加熱。此時，在由衰 減器4所控制的雷射輸出中，利用高溫計（pyr〇meter ) 5 來監視（monitor)峰值溫度，由晶圓的掃描速度來決定加 熱時間。再者’圖7中’符號8表示功率計（power meter) 8 ° 本實施形態中所用的LSA裝置1的雷射波長及輸出通 常是採用藉由連續振盪準分子雷射：KrF (波長248nm)、 Nd: YAG雷射（l〇64nm)、二氧化碳雷射（波長1〇 ym) 等振盪介質的平均輸出為0.1 W〜50 KW左右的非熔化雷 射瞬間退火（non melt Laser Spike Annealing )。 LSA裝置1的雷射光束照射時間可設為大於等於〇 〇1 微秒且小於10秒，更好的是設為大於等於〇1微秒（A s) 且小於等於0.8毫秒（ms )。 於上述處理中，可將雷射點（sp〇t)的面積設為數平 21 201018755 方厘米（cm2)的級別（order)，並且在直徑300 mm的晶 圓的情況下’將每1片晶圓的處理時間設為大於等於1分 鐘且小於等於10分鐘。 而且’此時的晶圓照射溫度（最高到達溫度）在晶圓 表面上的雷射點照射部分附近較好的是大於等於125〇。〇 且小於等於140(TC，尤其好的是大於等於13〇〇。(：且小於等 於 1350°C。 而且，石夕晶圓的LSA退火可在氫（H2)、氨（NH3) 等的還原性氣體環境中，氦（He)、氬（Ar)、氖（Ne)等 ® 的稀有氣體環境中，氮氣環境中，或者該些氣體中的大於 等=二種的混合氣體環境中進行。尤其可使用氫氣或者氫 與里*乳的體積混合比為1 : 1〜1 : 2〇的混合氣體環境。而 且，該些環境中的處理壓力可在大於等於1〇T〇rr左右的減 壓下且小於等於大氣壓中實施。 在LSA裝置1的χγ掃描平台3上，設有將晶圓w 固定於移動的平台3上的晶圓支持構件（夾盤（chuck)) 10。 夾盤10如圖8所示般支持由裙套（skirt) 500所包圍 的晶圓W。夾盤10可藉由使大量的熱自晶圓的表面移動 而將BS圓維持為固定的背景（backgr〇und )溫度。為了 達成該功能’夾盤1〇是設計成使熱自晶圓表面經由導熱性 加熱器模組（heater module)及絕緣趙層而有效率地移動 至散熱器（heatsink)。 夾盤10具有成為用於以下將說明的各元件的基準的 22 201018755 假想中心軸A1 (圖8)。 夾盤10具有散熱器（冷卻板）2〇。冷卻板2〇具有相 向的上下表面22、24、周邊部26以及本體（熱容（thermal mass)) 30 °冷卻板20包含形成於本體3〇内的冷卻路徑 32。冷卻路徑32支持冷卻流體（水等）自經由冷卻管線 42而動作性地連結於冷卻路徑的冷卻單元開始在本體 30内的流動。於一實施形態中，冷卻板2〇具有約15吋 的厚度T1。本實施形態中’冷卻板20是由鋁等的良好的 _ 導㈣構成。 夾盤10更包含具有相向的上下表面1〇2、1〇4的絕緣 體層100。絕緣體層1〇〇是配置成，下表面〗〇4與冷卻板 20的上表面22熱連結（例如，緊貼或接觸）。本實施形態 中，絕緣體層100具有相對較低的導熱性、較低的重量密 度、優異的熱衝擊抵抗性。 本實施形態中，絕緣鱧層1〇〇是由石英構成。在絕緣 體層具有較低的重量的情況下，掃描時容易達成夾盤的較 ❹ 高的加速率。 絕緣體層100在加熱器模組150與冷卻板之間維持實 質上固定的熱梯度（thermal gradient)。根據絕緣體層的導 熱性’以藉由電加熱器而將晶圓始終維持為固定溫度的方 式來決定移動至散熱器的熱。 本實施形態中’絕緣體層100具有約〇·5时的厚度 T2。絕緣體層100的厚度T2是藉由經驗分析來決定，^ 或藉由導熱性模型化（modeling)來決定，該導熱性模型 23 201018755 325()ϋριί 化疋為了在即使最大雷射輸出入射至基板時亦可保證維持 所期望的動作溫度所需的電力供給而設為必需。本實施形 態中，絕緣體板100為圓形，上下表面以具有大於等於〇2 以111且小於等於0.3 /zm的表面精加工的約5以瓜的平坦 性經機械加卫，與加熱！!模組及冷卻板具有良好的熱接觸: 失盤10亦包含具有相向的上下表面152、154、周邊 部156以及導熱性本體158的加熱器模組15〇。加熱器模 組150是配置成，下表面154與絕緣體層1〇〇的上表面ι〇2 熱連接。加熱器模組150包含嵌入本體158中的加熱單元 ❹ I60，並且可供給4.2 kW的熱。加熱器模組15〇亦經由絕 緣體層100而與冷卻板20熱連結，但並不與冷卻板2〇 理接觸。 加熱單元160包含嵌入本體158中的絕緣電阻性的加 熱元件164。於一實施形態中，加熱元件164為由與上表 面152平行的面所捲成的螺旋狀。加熱單元16〇是構成為， 每單位表面積（上表面152的面積）生成均勻量的熱。但 周邊部156為例外。由於周邊部156的熱損失較大‘，'故^ ❹ 與其成比例地需要高單位面積的受熱。 加熱器模組150的本體158是由鋁等的良好的導熱體 構成。加熱器模組150的本體158被缚造於加熱元件^64 的周圍’在（本實施形態中具有不鏽鋼的外側夾套（jacket) 的）加熱元件與加熱器模組的本體之間可獲得良好的熱連 結。加熱單元160包含連接於可變電源單元（電源）‘”18〇 的導線170。電源18〇將可變量的電力供給至加熱單元 24 201018755 160，以將加熱器模組雄持為固定的背景溫度TC。於一實 施形態中，加熱器模組150具有約〇·5〜約125对的厚度 Τ3。 ❹ ❹ 本實施形態中，例如，設為熱電偶或熱阻器 (thermistor)的溫度探頭19〇在大於等於i個位置上嵌入 加熱器模組150的本體158中’或者與本體I%熱連結。 於一實施形態中，大於等於1個溫度探頭19〇連結於夾盤 控制器200，該夾盤控制器200接收與在加熱器模組的不 同位置上測定出的溫度對應的大於等於丨個溫度信號 TS。如以下詳細說明般，控制器200亦動作性地連 卻單元4〇a可變電源單元180，（例如藉由軟體（s〇ftware) 的動作命令來）控制該些單元的動作。 爽盤10包含具有相向的上下表面302、304、周邊部 306及本體308的上部板300。上部板3〇〇是配置成下表 面304與加熱器模組150的上表面152熱連結（例如， 貼或接觸）。 ' 本實施形態中，上部板300具有約〇25〜約〇5 厚度T4。 . 4 上部板的上表面302支持晶圓We晶圓w 的表背面·、wr與外側邊緣（edge)(端面）。於一 實施形態巾，上部板防止因構成加熱輯組15〇的材 料而使晶圓W受到污染。當晶圓w切晶圓時 部板300的材料，可列舉熔解二氧化矽、矽、; 至少-種。本實施形態中，上部板綱包含分，於上表面 25 201018755When it is determined in the determination step S4 that the ship is unqualified, it returns to the polishing step si2 of the wafer command step S1, and the mt α is restored until the reference second wafer/* surface, the scratch side S3 of the end surface, and the determination step S4. . Therefore, when it is determined that the inspection step is successful again, the defective wafer is supplied to the component manufacturing step S5 in the determination step S4. (4) Fabrication of 45 S5 heat treatment step element having a LSA or the like on the line-cut wafer In the heat treatment step s52 shown in Fig. 7, the instantaneous annealing is performed by using the 20 201018755 shot annealing (LSA) device shown in Fig. 7. The LSA device can be heated up to 1350 ° C using microsecond to millisecond order illumination. As the laser instantaneous annealing (LSA) device, a beam diameter of 1 can be used as a transient annealing treatment device for forming a germanium wafer substrate of a source/demagnet region or an extension region of a semiconductor device. A laser instant annealing device of ~ 50 mm or so. The laser instantaneous annealing (LSA) device 1 does not heat the entire surface of the wafer W. Specifically, as shown in FIG. 7, the continuous oscillation type laser 2' is used for the light source. The wafer W subjected to XY scanning by the XY scanning platform 3 is locally restored via the mirror 6 and the beam shaping optical system 7. Heating is carried out under the atmosphere of a gas, a rare gas or a nitrogen gas. At this time, in the laser output controlled by the attenuator 4, a pyrometer (meter) 5 is used to monitor the peak temperature, and the heating time is determined by the scanning speed of the wafer. Further, 'the symbol 8 in Fig. 7 indicates a power meter 8 °. The laser wavelength and output of the LSA device 1 used in the present embodiment are generally employed by a continuous oscillation excimer laser: KrF (wavelength 248 nm). Nd: YAG laser (l〇64nm), carbon dioxide laser (wavelength 1〇ym) and other oscillating media have an average output of 0.1 W~50 KW non-melting laser spoke Annealing. The laser beam irradiation time of the LSA device 1 can be set to be greater than or equal to 微 1 microsecond and less than 10 seconds, and more preferably set to be greater than or equal to 〇1 microsecond (A s) and less than or equal to 0.8 milliseconds (ms). In the above process, the area of the laser spot (sp〇t) can be set to a level of 21 201018755 square centimeter (cm 2 ), and in the case of a wafer having a diameter of 300 mm, 'every piece of crystal The processing time of the circle is set to be greater than or equal to 1 minute and less than or equal to 10 minutes. Further, the wafer irradiation temperature (the highest arrival temperature) at this time is preferably 125 Å or more in the vicinity of the laser spot irradiation portion on the wafer surface. 〇 and less than or equal to 140 (TC, especially preferably greater than or equal to 13 〇〇. (: and less than or equal to 1350 ° C. Moreover, the LSA annealing of Shi Xi wafer can be reduced in hydrogen (H2), ammonia (NH3), etc. In a gaseous environment, in rare earth environments such as helium (He), argon (Ar), neon (Ne), etc., in a nitrogen atmosphere, or in a mixed gas atmosphere of these gases, which is greater than or equal to two. It is possible to use a mixed gas atmosphere of hydrogen or a volume ratio of hydrogen to lysine of 1: 1 to 1: 2 Torr. Moreover, the treatment pressure in these environments can be reduced under a pressure of about 1 〇 T 〇 rr or more. The χγ scanning platform 3 of the LSA device 1 is provided with a wafer supporting member (chuck) 10 for fixing the wafer w to the moving platform 3. The chuck 10 is as shown in the figure. The wafer W surrounded by the skirt 500 is supported as shown in Fig. 8. The chuck 10 maintains the BS circle at a fixed background temperature by moving a large amount of heat from the surface of the wafer. In order to achieve this function, the chuck 1 is designed to heat from the surface of the wafer via a thermal conductivity heater. The heater module and the insulating layer are efficiently moved to the heat sink. The chuck 10 has a 22 201018755 imaginary central axis A1 ( FIG. 8 ) which serves as a reference for each element to be described below. There is a radiator (cooling plate) 2〇. The cooling plate 2〇 has opposing upper and lower surfaces 22, 24, a peripheral portion 26, and a body (thermal mass) 30 ° The cooling plate 20 includes cooling formed in the body 3〇 Path 32. The cooling path 32 supports a flow of cooling fluid (water, etc.) from the cooling unit operatively coupled to the cooling path via the cooling line 42 to begin flow within the body 30. In one embodiment, the cooling plate 2 has approximately 15 The thickness T1 of the crucible. In the present embodiment, the cooling plate 20 is made of a good (four) aluminum or the like. The chuck 10 further includes an insulator layer 100 having opposing upper and lower surfaces 1〇2 and 1〇4. The insulator layer 1 The crucible is configured such that the lower surface 〇4 is thermally coupled (eg, in close contact or in contact with) the upper surface 22 of the cooling plate 20. In the present embodiment, the insulator layer 100 has a relatively low thermal conductivity and a low weight. Density, excellent Impact resistance. In the present embodiment, the insulating germanium layer 1 is made of quartz. When the insulator layer has a low weight, it is easy to achieve a relatively high acceleration rate of the chuck during scanning. Maintaining a substantially fixed thermal gradient between the heater module 150 and the cooling plate. According to the thermal conductivity of the insulator layer, the movement is determined by maintaining the wafer at a constant temperature by the electric heater. Heat of the heat sink. In the present embodiment, the insulator layer 100 has a thickness T2 of about 〇·5. The thickness T2 of the insulator layer 100 is determined by empirical analysis, or is determined by thermal conductivity modeling 23 201018755 325() 疋ρι 疋 疋 in order to be incident on the substrate even at the maximum laser output It is also necessary to ensure the power supply required to maintain the desired operating temperature. In the present embodiment, the insulator plate 100 is circular, and the upper and lower surfaces are mechanically reinforced by the flatness of about 5 melons having a surface of greater than or equal to 〇2 of 111 and less than or equal to 0.3/zm. The module and the cooling plate have good thermal contact: The loss plate 10 also includes a heater module 15A having opposing upper and lower surfaces 152, 154, a peripheral portion 156, and a thermally conductive body 158. The heater module 150 is configured such that the lower surface 154 is thermally coupled to the upper surface ι 2 of the insulator layer 1A. The heater module 150 includes a heating unit ❹ I60 embedded in the body 158 and can supply 4.2 kW of heat. The heater module 15 is also thermally coupled to the cooling plate 20 via the insulating body layer 100, but is not in operative contact with the cooling plate 2. Heating unit 160 includes an insulating resistive heating element 164 that is embedded in body 158. In one embodiment, the heating element 164 is spirally wound from a surface parallel to the upper surface 152. The heating unit 16A is configured to generate a uniform amount of heat per unit surface area (area of the upper surface 152). However, the peripheral portion 156 is an exception. Since the heat loss of the peripheral portion 156 is large, it is required to receive heat in a high unit area in proportion thereto. The body 158 of the heater module 150 is made of a good heat conductor such as aluminum. The body 158 of the heater module 150 is bound to the periphery of the heating element 64. The heating element between the heating element (with the outer jacket of stainless steel in this embodiment) and the body of the heater module is well obtained. Hot link. The heating unit 160 includes a wire 170 connected to a variable power supply unit (power source) 18". The power supply 18 〇 supplies variable power to the heating unit 24 201018755 160 to hold the heater module at a fixed background temperature In one embodiment, the heater module 150 has a thickness Τ3 of about 〇5 to about 125 pairs. ❹ ❹ In the present embodiment, for example, a temperature probe 19 of a thermocouple or a thermistor is used. The 〇 is embedded in the body 158 of the heater module 150 at or above the i position or is thermally coupled to the body I%. In one embodiment, one or more temperature probes 19 〇 are coupled to the chuck controller 200, The chuck controller 200 receives the temperature signal TS equal to or greater than the temperature measured at different positions of the heater module. As will be described in detail below, the controller 200 is also operatively coupled to the unit 4A. The variable power supply unit 180 controls the operations of the units (for example, by an action command of a software). The sizzling plate 10 includes an upper plate 300 having opposing upper and lower surfaces 302, 304, a peripheral portion 306, and a body 308. . The upper plate 3 is configured such that the lower surface 304 is thermally coupled (eg, attached or contacted) to the upper surface 152 of the heater module 150. In the present embodiment, the upper plate 300 has a thickness T4 of about 25 to about 〇5. The upper surface 302 of the upper plate supports the front and back surfaces of the wafer We wafer w, wr and the outer edge (end surface). In one embodiment, the upper plate prevents the material constituting the heating set 15〇. The wafer W is contaminated. When the wafer w is wafer-cut, the material of the portion plate 300 is fused with cerium oxide, lanthanum, or at least one type. In the present embodiment, the upper plate contains the upper surface. 25 201018755
302上設有氧化物或氮化物的塗層（c〇ating)。 本實施形態中’冷卻板20、絕緣體層10〇、加熱器模 組150藉由螺栓（bolt)而如上所述般保持，上部板藉由 真空而固定於加熱器模組。 夹盤ίο的主要作用之一是管理LSA時的熱平衡(heat balance) ’以使得不管LSA步驟中是否有雷射光束照射於 晶圓，背景晶圓溫度TC均維持為固定及均勻。進行該功 能時的夹盤10的動作將在以下進行詳細說明。A coating of oxide or nitride is provided on 302. In the present embodiment, the cooling plate 20, the insulator layer 10, and the heater module 150 are held by bolts as described above, and the upper plate is fixed to the heater module by vacuum. One of the main functions of the chuck ίο is to manage the heat balance of the LSA so that the background wafer temperature TC is maintained constant and uniform regardless of whether or not a laser beam is incident on the wafer in the LSA step. The operation of the chuck 10 when performing this function will be described in detail below.
在未有雷射光束照射於晶圓時，例如，在將雷射光束 照射於晶圓之前’為了使晶圓的摻雜劑（dGpant)活化等 的退火製程變得容易，而使晶圓w的溫度上升至背景溫度 TC為止。 虽未藉由雷射光束來進行加熱時，電源180必需將充 力86G供給至加熱器模組15G，以將模組及晶圓加 : 景《π·度TC夾盤控制器2〇〇為了經由溫度探頭 190 熱f模組150的溫度，並達成及維持所期望的固 ❿ =背景溫度TC，對供給至加熱器模組的電力_的 订控制。 損失束來對晶81供給熱時，來自夾盤的 知失的主要原因疋，經由晶圓上表面 經由絕緣體層1GG向冷卻被2G7放射及對抓 動推卻板2〇的冷卻流體（水等）的 動進仃控制，以促進冷卻板的熱消散。 寻Μ 如上所述，絕緣體層100在自上表面102中的固定 26 201018755When no laser beam is irradiated onto the wafer, for example, before the laser beam is irradiated onto the wafer, the annealing process for the activation of the dopant (dGpant) of the wafer is facilitated, and the wafer w is made. The temperature rises to the background temperature TC. Although the laser beam is not heated by the laser beam, the power source 180 must supply the charging force 86G to the heater module 15G to add the module and the wafer: π·degree TC chuck controller 2 Through the temperature probe 190 heats the temperature of the module 150, and achieves and maintains the desired solid state = background temperature TC, the control of the power supplied to the heater module. When the loss beam supplies heat to the crystal 81, the main cause of the loss from the chuck is that the cooling fluid (water, etc., which is radiated by the cooling layer 2G7 via the insulator layer 1GG and the gripping plate 2 is passed through the upper surface of the wafer. The movement of the enthalpy is controlled to promote the heat dissipation of the cooling plate. Looking up, as described above, the insulator layer 100 is fixed from the upper surface 102 26 201018755
背景溫度TC (例如，約400〇c)至下矣 的溫度(例如，20t;) 面104中的非常低 碑朝冷卻板2G的放射性的熱移動，但允 許自加熱||模_向冷卻板的傳導性的熱移動。 本實施形態中’加熱器模組15()為了在晶 ❿The background temperature TC (for example, about 400 〇c) to the temperature of the lower jaw (for example, 20t;) the very low monument in the face 104 moves toward the radioactive heat of the cooling plate 2G, but allows self-heating||mode_to the cooling plate The thermal transfer of conductivity. In the present embodiment, the heater module 15() is used in the crystal
2射時將晶圓維持為40(rc的固定的背景溫度TC，而 而要約3.4 kW的電力860。 當晶圓被雷射光束照射時，雷射光束對晶圓賦予約3 娜的能量’因放射及對流造成的能量損失為約μ =匕時將3kW的能量放出至冷卻板，並自電源18〇將〇5 W 6^電力供給至加熱器模組15〇，藉此可獲得平衡。 田雷射光束入射至晶圓表面時，使自電源18〇供給至 力0熱器模組15G的電力與此成比例地減少。為了維持固定 的背景溫度TC的電性鋪，經由絕緣體層丨⑻向冷卻板 的恆定狀態的熱損失必需在少於因放射及對流造成的 損失的範圍内，且必需大於來自雷射光束的最大供給能量。 夾盤10的加熱控制裝置的適應能力可容納雷射的較 ^變化的輸入位準，而帶來晶圓的固定的平均溫度。藉由 掃描雷射光束而供給至晶圓的空間性變化的熱負載因加熱 器模組與上部板的高傳導性而被動地得到補償。而且，晶 圓與上部板以及上部板與加熱器模組之間的較低的熱界面 電阻亦發揮使溫度的空間性的非均勻性減少的作用。 本實施形態的石夕晶圓藉由判定步驟S4,可僅將被判定 27 201018755 JZDOUpiI 為合格㈣晶圓提供給^件製造步驟S5。因而，雖晶圓上 的應力發生或者破裂發生的機制（meehanism)尚未得到 準確闡明，但根據本實施形態，可提供即使在設為使用如 LSA裝置的LSA f的掃描雷射騎型熱處理步 驟S52中亦可防止破裂發生的矽晶圓。 _ft ’可藉由較高的加熱溫度來使注人至晶圓的雜質 ΓΙΠ":而降低電阻。而且，同時，可藉由較短的加 二=來，質的秘要的擴散並且避免已活化的雜質 發生失活（deactlvati〇n)，即使在可實現如圖4所示的 的雜質分佈的熱處理中，亦可抑制晶圓破裂的發生。/ 而且’在固溶氧濃度〇i、氧析出物的大小、密度 加物的碳滚度、氮濃度、作為射氣劑的鱗⑺ ίίΪ:等:斜先前為了抑制或防止滑動錯位的伸展而進 嚴格的熱處理，難以提供防止破裂發生 然而，本實施形態的矽晶圓中， ❹ 謹相當的破歸生程度的條件的嚴格的理 防止破裂發生的矽晶圓。 ，、、慝 了槌供 而且，本實施形態的發晶圓中，在研磨步 =晶圓背:的研磨裕度設為大於等於！…小於等 ”圓的情況時，或者即使在晶圓準備步3 而可於说步称中防止晶圓去破^痕生而排除其影穿，從 28 201018755At 2 shots, the wafer is maintained at 40 (rc's fixed background temperature TC, while about 3.4 kW of power 860. When the wafer is illuminated by a laser beam, the laser beam imparts about 3 nanowatts of energy to the wafer' When the energy loss due to radiation and convection is about μ = 将, 3 kW of energy is discharged to the cooling plate, and 〇5 W 6^ power is supplied from the power source 18 to the heater module 15 〇, thereby achieving balance. When the field beam is incident on the surface of the wafer, the power supplied from the power source 18〇 to the force module 15G is reduced in proportion to this. In order to maintain the electrical temperature of the fixed background temperature TC, via the insulator layer (8) The heat loss to the constant state of the cooling plate must be less than the loss due to radiation and convection, and must be greater than the maximum supply energy from the laser beam. The adaptability of the heating control device of the chuck 10 can accommodate the lightning The relatively constant input level of the shot, resulting in a fixed average temperature of the wafer. The spatially varying thermal load supplied to the wafer by scanning the laser beam is highly conductive due to the heater module and the upper plate. Sexually and passively compensated. Moreover, the lower thermal interface resistance between the wafer and the upper plate and the upper plate and the heater module also serves to reduce the spatial non-uniformity of temperature. In step S4, only the determined 27 201018755 JZDOUpiI is provided to the qualified (four) wafer to the manufacturing step S5. Therefore, although the mechanism of stress occurrence or cracking on the wafer has not been accurately clarified, according to the implementation The form can provide a crucible wafer that can prevent cracking even in the scanning laser riding type heat treatment step S52 set to use LSA f such as an LSA device. _ft ' can be injected to a higher heating temperature to The impurity of the wafer is ΓΙΠ": and the resistance is lowered. Moreover, at the same time, the short diffusion of the second can be used to spread the secret of the substance and avoid the deactivation of the activated impurity, even if it is In the heat treatment for realizing the impurity distribution as shown in Fig. 4, the occurrence of wafer cracking can also be suppressed. / Moreover, the solid solution oxygen concentration 〇i, the size of the oxygen precipitate, the carbon enthalpy of the density additive, and the nitrogen concentration Scale as an ejector (7) LY Ϊ 等 等 等 等 先前 先前 先前 先前 先前 先前 先前 先前 先前 先前 先前 先前 先前 先前 先前 先前 先前 先前 先前 先前 先前 先前 先前 先前 先前 先前 先前 先前 先前 先前 先前 先前 先前 先前 先前 先前 先前 先前 先前 先前 先前 先前 先前 先前 先前 先前 先前In the wafer of the present embodiment, the polishing margin of the polishing step = wafer back: is set to be equal to or greater than the thickness of the wafer. !...when less than the "circle", or even in the wafer preparation step 3, it is possible to prevent the wafer from being broken and to eliminate the shadow in the step by step, from 28 201018755
JL 奉貫施形態的矽晶圓中’將矽晶圓端面 裕度设為大於等於丨⑽且小鱗於3㈣。藉此， 存在欺步驟S4巾被欺料合格的⑦晶圓的情況時， 或者即使在晶圓準備步驟81中被導人有劃痕的情況時， 亦可去除該劃痕而排除其影響，從而可於LS 晶圓破裂的發生。In the JL wafer form, the wafer end face margin is set to be greater than or equal to 丨 (10) and the small scale is at 3 (four). Therefore, when there are 7 wafers in which the step S4 is smeared, or if the guide is scratched in the wafer preparation step 81, the scratch can be removed and the influence can be eliminated. This can cause rupture of the LS wafer.
進而，如圖9所示，在晶圓的表面22上，設有作 平坦面的主面W23以及形成於周緣部的表關倒棱部 W24。而且，在背面Wr上，設有作為平坦面的主面 以及形成有周緣部的背面側倒稜部W28。 表面侧倒稜部W24自其周緣端Wt朝向晶圓半徑方向 内方的方向的寬度A1窄於背面側倒稜部W28的自周緣端 wt朝向晶圓半徑方向内方的方向的寬度A2。表倒 部W24的寬^ A1較好的是大於等於5〇⑽且小於等於 200 /zm的範圍。而且，背面侧倒棱部|28的寬度八之較 好的是大於等於200 /zm且小於等於300 的範圍。 而且，表面側倒稜部W24具有相對於表面Wu的主面 W23而傾斜的第一傾斜面W11，背面側倒稜部W28具有 相對於背面Wr的主面W27而傾斜的第二傾斜面W12。第 一傾斜面W11的傾斜角度Θ1較好的是大於等於1〇。且小 於等於50。的範圍，第二傾斜面W12的傾斜角度較好 的是大於等於10。且小於等於30。的範圍，更好的是設為 Θ 1$ 02。 而且，在第一傾斜面W11與周緣端Wt之間，於表面 29 201018755 最外周Wut設有將第一傾斜面W11與周緣端||予以連接 的第一曲面W13。而且，在第二傾斜面W12與周緣端wt 之間，於背面最外周部Wrt設有將第二傾斜面W12與周緣 端wt予以連接的第二曲面W14。第一曲面wl3的曲率半 徑R1的範圍較好的是大於等於8〇 且小於等於 的範圍，第二曲面W14的曲率半徑R2的範圍較好的 是大於等於100 且小於等於3〇〇以瓜的範圍。 藉由設為上述的端部構成，可減少晶圓操作（wafer handling)時的劃痕產生。 以下，根據圖式說明本發明的矽晶圓及其製造方法的 第二實施形態。 圖2是表示本實施形態的矽晶圓及其製造方法的流程 圖，相對於圖1所示的第一實施形態，不同的是關於磊晶 層成膜的方面。對於同等的構成元件，標註同一符號並省 略其說明。 在本實施形態中，如圖2所示，於晶圓準備步驟S1 中包括蠢晶成膜步驟Sii以及隨後的研磨步驟。 在圖2所示的磊晶成膜步驟S11中，設為於晶圓表面 上使磊晶層成膜，例如，可設為p/p—型（type)。這表示在 P-型晶圓上積層有p型磊晶層的晶圓。此處，就硼（B)濃 度而言，所謂P-型，是指硼（B)濃度為相當於電阻率 Ωαη〜100 Qcm的濃度，所謂p型，是指硼（B)濃度為 相虽於電阻率0.1 Qcin〜〇 〇1 Qcm的濃度。 本實施形態的磊晶成膜步驟S11是在研磨步驟S12之 201018755 j^jKjyjyu. = 置來進行。該氣相成長裝置是逐片地處 理+導體㈤® w的早片式氣相成錢置，如圖1〇所示， 是使磊晶層EP於矽晶圓w的主表面 磊晶晶圓EW的裝置。 該氣相成長裝置E1具備晶座Ε2、反應容器Ε3以及 加熱裝置Ε4。Further, as shown in Fig. 9, on the surface 22 of the wafer, a main surface W23 as a flat surface and a surface chamfered portion W24 formed on the peripheral portion are provided. Further, the back surface Wr is provided with a main surface as a flat surface and a back side chamfer portion W28 on which a peripheral portion is formed. The width A1 of the surface-side chamfered portion W24 from the peripheral edge Wt toward the inside in the wafer radial direction is narrower than the width A2 of the back-side chamfered portion W28 from the peripheral end wt in the direction inward in the wafer radial direction. The width A A1 of the inverted portion W24 is preferably a range of 5 〇 (10) or more and 200 / zm or less. Further, the width of the back side chamfering portion | 28 is preferably a range of 200 / zm or more and 300 or less. Further, the front side chamfered portion W24 has a first inclined surface W11 that is inclined with respect to the main surface W23 of the surface Wu, and the back side chamfered portion W28 has a second inclined surface W12 that is inclined with respect to the main surface W27 of the back surface Wr. The inclination angle Θ1 of the first inclined surface W11 is preferably 1 大于 or more. And less than 50. The range of the inclination of the second inclined surface W12 is preferably 10 or more. And less than or equal to 30. The range is better set to Θ 1$ 02. Further, between the first inclined surface W11 and the peripheral end Wt, a first curved surface W13 that connects the first inclined surface W11 and the peripheral end || is provided on the outermost surface Wut of the surface 29 201018755. Further, between the second inclined surface W12 and the peripheral end wt, a second curved surface W14 that connects the second inclined surface W12 and the peripheral end wt is provided on the rearmost outer peripheral portion Wrt. The range of the radius of curvature R1 of the first curved surface wl3 is preferably a range of greater than or equal to 8 〇 and less than or equal to, and the range of the radius of curvature R2 of the second curved surface W14 is preferably greater than or equal to 100 and less than or equal to 3 〇〇. range. By providing the above-described end portion configuration, it is possible to reduce the occurrence of scratches during wafer handling. Hereinafter, a second embodiment of the tantalum wafer of the present invention and a method of manufacturing the same will be described based on the drawings. Fig. 2 is a flow chart showing a tantalum wafer and a method of manufacturing the same according to the embodiment, and is different from the first embodiment shown in Fig. 1 in terms of film formation of an epitaxial layer. For the same constituent elements, the same reference numerals will be given and the description will be omitted. In the present embodiment, as shown in FIG. 2, a wafer formation step Sii and a subsequent polishing step are included in the wafer preparation step S1. In the epitaxial film formation step S11 shown in Fig. 2, the epitaxial layer is formed on the surface of the wafer, and for example, it can be set to p/p-type. This represents a wafer in which a p-type epitaxial layer is laminated on a P-type wafer. Here, the boron (B) concentration means that the boron (B) concentration is a concentration corresponding to the specific resistance Ωαη to 100 Qcm, and the p-type means that the boron (B) concentration is a phase. The concentration of resistivity is 0.1 Qcin~〇〇1 Qcm. The epitaxial film formation step S11 of the present embodiment is carried out at 201018755 j^jKjyjyu. = in the polishing step S12. The vapor phase growth device processes the +-conductor (f)® w of the early-stage vapor phase into a sheet, as shown in FIG. 1A, which is an epitaxial wafer on which the epitaxial layer EP is deposited on the main surface of the wafer w. EW device. The vapor phase growth apparatus E1 includes a crystal crucible 2, a reaction vessel crucible 3, and a heating device crucible 4.
日日座Ε2疋載置半導體晶圓w的構件，設置於反應容 器E3的内部。晶座E2藉由與旋轉轴现相連的晶座支持 部E34來支持其下表面’藉由旋轉轴Er的獎動來旋轉。 晶座E2的材質並無特別限定，例如較好的是在碳基材的 表面塗佈有S!C被膜的材質。作為將半導體晶圓w搬入晶 座E2的方式、自晶座E2搬出半導體晶圓以的方式，並 無特別限定’例如可列舉使雜氏夾盤（Vemeuilchuck) 並藉由搬送夾具的升降來移載半導體晶圓w的方式，或者 將半導體晶圓w的下表面以銷（pin)來支持並藉由銷的 升降來移載半導體晶圓W的方式等。 反應容器E3在其内部設置有晶座E2，且可向其内部 供給反應氣體地構成。並且，反應容器E3藉由對載置於 晶座E2上的半導體晶圓w供給反應氣體而使磊晶層Ep 於半導體晶圓W的主表面上成長。該反應容器E3具備上 側圓頂（dome) E3卜下侧圓頂E32、圓頂安裝體E33以 及晶座支持部E34。上侧圓頂E3i及下侧圓頂E32是由石 英等的透光性構件所構成，且分別形成為俯視時大致中央 部分自反應容器E3的内部朝向上側及下侧而凹陷的大致 31 201018755The member on which the semiconductor wafer w is placed is placed on the inside of the reaction container E3. The crystal holder E2 supports the lower surface thereof by the pad holder E34 which is now connected to the rotation axis, and is rotated by the medal of the rotation axis Er. The material of the crystal seat E2 is not particularly limited, and for example, a material of an S!C film coated on the surface of the carbon substrate is preferred. There is no particular limitation on the manner in which the semiconductor wafer w is carried into the crystal holder E2 and the semiconductor wafer is carried out from the crystal holder E2. For example, the hybrid chuck is moved by the lifting and lowering of the transport jig. A method of loading the semiconductor wafer w, or a method of supporting the lower surface of the semiconductor wafer w with a pin and transferring the semiconductor wafer W by lifting of the pin. The reaction vessel E3 is provided with a crystal holder E2 inside and can be supplied with a reaction gas to the inside thereof. Further, the reaction container E3 grows the epitaxial layer Ep on the main surface of the semiconductor wafer W by supplying the reaction gas to the semiconductor wafer w placed on the crystal holder E2. The reaction vessel E3 is provided with an upper dome E3, a lower dome E32, a dome mounting body E33, and a holder supporting portion E34. The upper dome E3i and the lower dome E32 are formed of a translucent member such as Shise, and are formed so as to be substantially recessed from the inside of the reaction container E3 toward the upper side and the lower side in a plan view.
凹狀。圓頂安裝體E33是由上方及下方為開放的大致筒狀 構件所構成’利用上方側的開口部分及下方側的開口部分 來支持上側圓頂E31及下側圓頂E32。在該圓頂安裝體E33 的侧面，設有反應氣體供給管E331 ’在與反應氣體供給管 E331相向的圓頂安裝體E33的側面’設有反應氣體排出管 E332。自反應氣體供給管E331將反應氣體供給至反應容 器E3的内部。反應氣艘例如是將SiHCl3的梦源（silicon source)以氫氣稀釋，並在其中微量混合摻雜劑而成。所 供給的反應氣體水平地通過載置於晶座E2上的半導體晶 圓W的主表面之後，自反應氣體排出管E332而排出至反 應容器E3之外。 晶座支持部E34是由石英等的透光性構件所構成，自 反應容器E3的下側圓頂E32的大致中央部分向反應容器 E3的内部突出，將晶座E2以水平狀態支持於反應容器E3 的内部。並且，晶座支持部E34例如是可在藉由控制裝置 (未圖示）的控制下’以旋轉軸ER為中心而旋轉自如地Concave. The dome-shaped mounting body E33 is composed of a substantially cylindrical member that is open at the upper and lower sides. The upper dome E31 and the lower dome E32 are supported by the upper opening portion and the lower opening portion. A reaction gas supply pipe E332' is provided on the side surface of the dome-mounted body E33, and a reaction gas discharge pipe E332 is provided on the side surface of the dome-mounted body E33 facing the reaction gas supply pipe E331. The reaction gas is supplied from the reaction gas supply pipe E331 to the inside of the reaction vessel E3. The reaction gas tank is formed, for example, by diluting a silicon source of SiHCl3 with hydrogen and mixing a dopant therein. The supplied reaction gas passes horizontally through the main surface of the semiconductor wafer W placed on the crystal holder E2, and is discharged from the reaction gas discharge pipe E332 to the outside of the reaction container E3. The holder support portion E34 is made of a light transmissive member such as quartz, and protrudes from the substantially central portion of the lower dome E32 of the reaction container E3 toward the inside of the reaction container E3, and supports the crystal holder E2 in a horizontal state in the reaction container. The interior of E3. Further, the holder support portion E34 can be rotatably rotated around the rotation axis ER, for example, under the control of a control device (not shown).
構成。 加熱裝置E4分觀設於反絲^ E3社方侧及下; 侧’經由反應容器E3的上側圓頂E31及下侧圓頂E32 藉由放射熱來對晶座拉及載置_晶座E2上的半導體』 圓W進行加熱’從叫半導體晶圓W較祕定溫度, 作為^加熱裝置E4，例如可採用㈣燈（halQgen 且’作為加熱裝置E4’除了藉由放射熱《 進订加熱的裝置以外，亦可制藉由㈣加齡對半^ 32 201018755 晶圓w進行加熱的高頻加熱方式。 半導體，不’在晶座E2的上表面，形成有由直徑比 日圓$直徑大的凹部構成的晶圓載置部E21。該 1 曰圓2物1是由第一凹部_以及第二__構 ㈣_凹部E2U是自晶座^的上表面向下侧凹陷的圓 而白笛口。第二凹部E212是以比第一凹部E2u小的直徑 ❹ ❹ 炎-凹。卩E2U的底面向下側凹陷，且，與第一凹部 η铋乂同、的圓形的凹部。而且’在第二凹部E212的外 :道^位置上’形成有以第1部E211的底面來支持 千导體日日圓W的晶圓支持部E213。 半導體晶圓w藉由以晶圓支持部E213來支持而載 於晶圓載置部E21的内側。 第一凹部E211的内徑A大於半導體晶圓w的直徑 B。晶圓支持部E213的沿著第二凹部E212的徑方向的長 度L是設定為半導體晶圓|不會落下至第二Composition. The heating device E4 is disposed on the side of the reverse wire E3 and the lower side; the side 'is pulled and mounted by the radiant heat through the upper dome E31 and the lower dome E32 of the reaction vessel E3_the base E2 The upper semiconductor "heating" is called 'heating from the semiconductor wafer W. As the heating device E4, for example, (4) lamps (halQgen and 'as the heating device E4' except by the radiant heat" In addition to the device, it is also possible to manufacture a high-frequency heating method for heating the wafer w by (4) ageing. The semiconductor is not formed on the upper surface of the crystal holder E2 by a recess having a diameter larger than the diameter of the yen. The wafer mounting portion E21 is composed of a first concave portion _ and a second __ structure (four) _ concave portion E2U which is a circle which is recessed downward from the upper surface of the crystal holder ^ and a white flute. The second concave portion E212 is a circular concave portion which is smaller than the first concave portion E2u and has a diameter smaller than the first concave portion E2U. The bottom surface of the 卩E2U is recessed downward, and the first concave portion η is the same as the circular concave portion. The outer portion of the two concave portions E212 is formed at the position of the first portion E211 to support the crystal of the thousand-conductor Japanese yen W. The circular support portion E213. The semiconductor wafer w is supported inside the wafer mounting portion E21 by being supported by the wafer supporting portion E213. The inner diameter A of the first concave portion E211 is larger than the diameter B of the semiconductor wafer w. Wafer support The length L of the portion E213 along the radial direction of the second recess E212 is set to the semiconductor wafer|will not fall to the second
長度。 J 晶η圓支持部E213的沿著第二凹部E212的徑方向的長 度L (單位為mm)可設定為滿足以下的式（1)。 L= (A—B) + C + D + E<6·.. (1) 於式（1)中，A為晶圓載置部E21的内徑（mm)，B 為半導體晶圓W的直徑（mm) ’ C為半導體晶圓w的凹 槽（notch)的深度（mm)，D為凹槽N的倒稜部分的寬度 (mm)，E為安全係數（mm)。安全係數£是在以加熱& 置E4來對反應容器E3進行加熱時，將半導體晶圓w、的 33length. The length L (unit: mm) of the J-crystal η circular support portion E213 along the radial direction of the second concave portion E212 can be set to satisfy the following formula (1). L=(A—B) + C + D + E<6·.. (1) In the formula (1), A is the inner diameter (mm) of the wafer mounting portion E21, and B is the diameter of the semiconductor wafer W. (mm) 'C is the depth (mm) of the notch of the semiconductor wafer w, D is the width (mm) of the chamfered portion of the groove N, and E is a safety factor (mm). The safety factor is: when the reaction vessel E3 is heated by heating & E4, the semiconductor wafer w, 33
201018755 -S^DOUpiI 熱膨脹引起的變化量考慮在⑽數值，較 更Γ的且日小;;等於2麵。L的上限值較好的是小於= 較好的是大於等於lmn^ 值 當在半導體晶圓W被載置於晶圓載置部切的狀熊 ::晶座E2的上表面低於半導體晶圓w的上表面時，^ 合^會與半導體晶圓料倒稜部分接觸，從而反應氣體 會超過必要地繞至半導艘晶圓w的背面侧。另—方面當 在半導體晶圓w被載置於晶圓載置部E21的狀態下，晶 的上表面與半導體晶圓w的上表面為相同高度時， 與上述情況相比’反應氣體繞至半導體晶® W㈣面側的 ^能性較低。然而，為了提供具有高平坦度且高精度的蟲 晶層Ep的半導體晶圓w，必需使半導體晶圓W的背面上 的磊BB層EP的成長進一步減少。因此，在半導體晶圓w ，載，於晶圓載置部E21的狀態下，使晶座E2的上表面 尚，半導體晶圓W的上表面。根據該構成，可極力降低反 應氣體繞至半導體晶圓W的背面側的可能性。具體而言， 可在半導體晶圓W被載置於晶圓載置部E21的狀態下， 將晶座E2的上表面設定為比半導體晶圓w的上表面高出 大於等於10 //m且小於等於4〇〇 左右。 於蟲晶成膜步驟S11中，晶座對上述矽晶圓的支持位 置是設定為矽晶圓W的端面Wt、以及上述矽晶圓背面Wr 中的自最外周部Wrt朝向晶圓直徑方向Wo中心的距離r 與圖6中以符號2R所示的晶圓直徑尺寸之比成為大於等 34 201018755 於1.5/300到、於等於6/300的範園，較好的 於2/300且小於等於5/300的範圍。即，如圖丨丨所大於等201018755 -S^DOUpiI The amount of change caused by thermal expansion is considered to be (10), which is more ambiguous and smaller; it is equal to 2 faces. The upper limit of L is preferably less than or less than lmn^. When the semiconductor wafer W is placed on the wafer mounting portion, the upper surface of the crystal holder E2 is lower than the semiconductor crystal. When the upper surface of the circle w is in contact with the chamfered portion of the semiconductor wafer, the reaction gas is more than necessary to be wound around the back side of the semiconductor wafer w. On the other hand, when the upper surface of the crystal is at the same height as the upper surface of the semiconductor wafer w in a state where the semiconductor wafer w is placed on the wafer mounting portion E21, the reaction gas is wound to the semiconductor as compared with the above case. The surface energy of the crystal W (four) side is low. However, in order to provide the semiconductor wafer w having the high flatness and high precision of the insect layer Ep, it is necessary to further reduce the growth of the Lei BB layer EP on the back surface of the semiconductor wafer W. Therefore, in the state where the semiconductor wafer w is placed on the wafer mounting portion E21, the upper surface of the crystal holder E2 is placed on the upper surface of the semiconductor wafer W. According to this configuration, the possibility that the reaction gas is wound around the back side of the semiconductor wafer W can be minimized. Specifically, the upper surface of the crystal holder E2 can be set to be higher than or equal to 10 //m and smaller than the upper surface of the semiconductor wafer w in a state where the semiconductor wafer W is placed on the wafer mounting portion E21. It is equal to 4〇〇. In the insect crystal film forming step S11, the support position of the wafer holder for the germanium wafer is set to the end surface Wt of the germanium wafer W and the outer peripheral portion Wrt of the germanium wafer back surface Wr toward the wafer diameter direction Wo. The ratio of the distance r of the center to the diameter of the wafer as indicated by the symbol 2R in Fig. 6 becomes greater than that of 34 201018755 at 1.5/300 to, equal to 6/300, preferably 2/300 and less than or equal to The range of 5/300. That is, as shown in Figure 大于, etc.
直徑300 mm的晶圓的情況時，成為圓形的邊緣的了 持部E213接觸晶圓W的支持值置是設定為自最 Wrt朝向晶圓直徑方向w〇中心的距離^大於等於1 5 ° ° 且小於等於6 mm ’較好的是大於等於2。職且小於: 5 mm。其原因在於，於磊晶成膜步驟sn中晶圓貨^ 因自重而以中央部向下彎曲的方式發生變形，因而實質: 成為邊緣的晶圓支持部E213成為作為環狀的晶座而與曰 圓W接觸並予以支持的狀態。 如上所述’藉由將r/2R設為1.5/3〇〇〜6/3〇〇的範圍， 即使在因晶圓支持部E213與晶圓W的接觸，導致晶圓支 持部E213與晶圓W局部性地固著的部位發生剝落:導入 有劃痕的情況下，藉由在晶圓緣部狀態設定步驟中對緣部 狀態進行設定，亦可防止LSA步驟中的破裂發生。具體^ 後述的實施例所示。 、 如後述的實施例所示，晶圓緣部狀態設定步驟S2A中 的緣部狀態是設定為，當處理溫度（峰值溫度）為12〇〇〇c 時’將晶圓支持位置設為自背面最外周算起徑方向大於等 於1.5/300且小於等於6/300的範圍。而且，晶圓緣部狀態 設定步驟S2A中的緣部狀態是設定為，當最高到達溫度 (處理溫度）為1300°C時，將晶圓支持位置設為自背面最 外周算起徑方向大於等於1.5/300且小於等於6/300的範圍 的狀態。 35 201018755 藉此 裂的緣部狀態的條件 可试疋上述第二實施形態中記載的不會發生破 設為大=在研磨步驟S13中’將碎晶圓背面的研磨裕度 _且小於等於3心根據該構成，即 遙曰成贈t驟S4中被判定為不合格的石夕晶圓、或者在 書^而姑冑su中被導入有劃痕的石夕晶®，亦可去除該 六沾细*除其影響。因而，在使晶11產生與LSA同等的應 力的熱處理步驟中可防止晶®破裂的發生。 再者，該研磨步驟S13與在磊晶成膜步驟S11之前進 订的研磨步驟S12中的研磨裕度（大於等於5㈣且小於 等於10 /zm左右）相比，可設定為極少的切削裕度 (machining allowance )。 [實施例]In the case of a wafer having a diameter of 300 mm, the support value of the contact portion E213 which is a circular edge is in contact with the wafer W. The distance from the Wrt to the center of the wafer diameter direction w〇 is set to be greater than or equal to 15 °. ° and less than or equal to 6 mm' is preferably greater than or equal to 2. Job size and less than: 5 mm. This is because the wafer material is deformed so that the center portion is bent downward due to its own weight in the epitaxial film forming step sn. Therefore, the wafer support portion E213 which becomes the edge is formed as a ring-shaped crystal seat. The state of contact and support. As described above, by setting r/2R to a range of 1.5/3 〇〇 to 6/3 ,, the wafer support portion E213 and the wafer are caused even by the contact of the wafer support portion E213 with the wafer W. W is locally peeled off at the site where the local fixation is performed. When the scratch is introduced, the edge portion state can be set in the wafer edge state setting step, and the occurrence of cracking in the LSA step can be prevented. Specifically, the embodiment described later is shown. As shown in the later-described embodiment, the edge state in the wafer edge state setting step S2A is set to set the wafer support position from the back when the processing temperature (peak temperature) is 12 〇〇〇c. The outermost circumference is calculated to have a range of 1.5/300 or more and a range of 6/300 or less. Further, the edge state in the wafer edge state setting step S2A is set such that when the highest reaching temperature (processing temperature) is 1300 ° C, the wafer supporting position is set to be greater than or equal to the radial direction from the outermost periphery of the back surface. A state of 1.5/300 and a range of 6/300 or less. 35 201018755 The condition of the edge state of the crack can be tested. The above-described second embodiment does not cause breakage to be large = in the polishing step S13, the grinding margin of the back surface of the chip is _ and less than or equal to 3 According to this configuration, the Shihwa wafer which is determined to be unsatisfactory in the step S4 or the Shihwa® which is scratched in the book and the aunt su can be removed. Dim* in addition to its effects. Therefore, the occurrence of cracking of the crystallized® can be prevented in the heat treatment step of causing the crystal 11 to generate the same stress as the LSA. Further, the polishing step S13 can be set to a minimum cutting margin as compared with the polishing margin (greater than or equal to 5 (four) and less than or equal to about 10 /zm) in the polishing step S12 which is ordered before the epitaxial film formation step S11. (machining allowance). [Examples]
以下’對本發明的實施例進行說明。 <實施例1>The following describes the embodiments of the present invention. <Example 1>
背面劃痕大小與處理溫度的影響 由拉製成氧濃度 Oi 為 6xl017 atoms/cm3(〇ld· ASTM) 的直徑300mm的矽單晶錠（ingot) ’藉由切片、雙面研磨 (DSP)而準備（1〇〇)晶圓。 在該矽晶圓的端面及/或背面，根據維氏壓痕法，使用 鑽石壓頭，以不同的荷重，針對每1片晶圓而於一處導入 成為劃痕（Crack ’裂紋）的維氏壓痕。該劃痕的導入位置 為晶圓端面或晶圓外周部背面（最外周〜3 mm)，該位置 示於表1。 36 201018755 [表l] 刻痕狀態 最高到遠溫度（°c) 割痕導入位置 導入的裂紋（Crack) 尺寸（/zm) 1080°C 1100°C 1200°C 1300°C 端面 5.5 〇 〇 〇 〇 最外周〜1 mm 3.1 〇 〇 〇 〇 2 mm 〜3 mm 4.4 〇 〇 〇 5 mm 〜6 mm 5 〇 〇 〇 O 10mm 〜11 mm 5.1 〇 〇 〇. 端面 10.2 〇 X X X 最外周〜1 mm 10.4 〇 〇 X X 2 mm 〜3 nun 11.3 〇 〇 〇 X 5 mm 〜6 mm 10.9 〇 〇 〇 〇 10 mm 〜11 mm 10.6 〇 〇 〇 〇. 端面 36.1 〇 X X X 最外周〜1 mm 35.5 〇 X X X 2 mm 〜3 mm r 37.2 〇 〇 X X 5 mm 〜6 mm 34.8 〇 〇 o o 10 mm 〜11 mm 35.2 r\ · ----1 〇 〇 〇 〇 〇.無破裂發生，X :有破裂發生The effect of the size of the back scratch and the treatment temperature was drawn by a 300 mm diameter 矽 single crystal ingot of oxygen concentration Oi of 6xl017 atoms/cm3 (〇ld· ASTM) by slicing, double-side grinding (DSP) Prepare (1〇〇) wafer. On the end surface and/or the back surface of the tantalum wafer, a diamond indenter is used to introduce a scratch (crack 'crack) dimension in one place for each wafer according to the Vickers indentation method with different loads. Indentation. The introduction position of the scratch is the wafer end surface or the wafer outer peripheral surface (outermost circumference ~ 3 mm), and the position is shown in Table 1. 36 201018755 [Table l] Scratch state up to far temperature (°c) Crack introduced at the cut introduction position (/zm) 1080°C 1100°C 1200°C 1300°C End face 5.5 〇〇〇〇 The outermost circumference ~1 mm 3.1 〇〇〇〇2 mm ~3 mm 4.4 〇〇〇5 mm ~6 mm 5 〇〇〇O 10mm ~11 mm 5.1 〇〇〇. End face 10.2 〇XXX outermost circumference ~1 mm 10.4 〇〇 XX 2 mm 〜3 nun 11.3 〇〇〇X 5 mm 〜6 mm 10.9 〇〇〇〇10 mm 〜11 mm 10.6 〇〇〇〇. End face 36.1 〇XXX outermost circumference ~1 mm 35.5 〇XXX 2 mm 〜3 mm r 37.2 〇〇XX 5 mm ~6 mm 34.8 〇〇oo 10 mm ~11 mm 35.2 r\ · ----1 〇〇〇〇〇. No cracking occurs, X: cracking occurs
利用光學顯微鏡來測定由所導入的劃痕（維氏壓 所產生的劃痕的尺寸，將其大小示於表1。在導入劃 使用:毫秒退火的LSA爐’以不_最高到達溫度來進 退火處理，以實施晶圓破裂測試。初始晶圓溫度為響c。 將結果示於表1。 虚理果可知’在科収邱纽科1丨崎的 藉由提供在二3在：=裂紋亦為同樣。 晶圓，谢LSA步^㈣的綱 37 201018755 ^zjoupu <實施例2> 磊晶成長時的支持位置依存性以及磊晶成長後的研 磨的影響 實施蠢晶成長（蠢晶成膜）的磊晶晶圓在磊晶成長過 程中，晶圓與環狀的晶座的接觸不可避免。因該接觸，晶 ，與晶座緊貼，從而局部性地導致反應氣體流動因此而固 著。於磊晶成長後，自晶座抬起晶圓時，該固著有時會剝 落，從而導入裂紋（Crack) 〇 與實施例1同樣地，準備直徑3〇〇 mm的晶圓，於該 ❹ 晶圓表面實施蠢晶成長（蟲晶成膜），準備好具備p/p_構造 的晶圓。 此時，在磊晶成長中，使用晶圓最外周部〜丨mm以 内為支持位置而呈圓狀與晶座接觸的晶座丨、同樣地支持 位置為自晶圓最外周部算起的15mm的晶座2、同樣地支 持位置為自晶圓最外周部算起的41 mm的晶座3、同樣地 支持位置為自晶圓最外周部算起的58mm的晶座4，使支 持位置在最外周部〜6 mm的範圍内變化。 參 與實施例1同樣地，使用可毫秒退火的LSa爐，以不 ，的最尚到達溫度來進行退火處理，以實施晶圓破裂測 試。初始晶圓溫度為40(TC。將結果示於表2。再者，破裂 發生率疋對各水準的50片晶圓進行處理時發生破裂的比 率。 38 201018755 [表2] 最高到達溫度 晶厓-種類 ^^面研磨量（um) l'〇80°C 1100°C 1200°C 130(TC 晶座-1 0 0% 0% 2% 6% 晶座-2 (1.5 mm支持） 0 0% 0% 0% 0% 晶座-3 (4.1 mm支持） 0 0% 0% 0% 0% 晶座-4 (5.8 mm支持） 0 0% 0% 0% 0% 晶座-1 0.55 0% 0% 0% 2% 晶座-1 ----- 1.1 0% 0% 0% 0% 晶座-1 25 0% 0% 0% 0% 晶座-2 1 0% 0% 0% 0% 晶座-2 2.7 0% 0% 0% 0%An optical microscope was used to measure the size of the scratches caused by the introduced scratches (Vickers pressure, and the size thereof is shown in Table 1. The LSA furnace used in the introduction of the millisecond annealing was advanced or not at the highest temperature. Fire treatment to perform wafer rupture test. The initial wafer temperature is ringing c. The results are shown in Table 1. The imaginary fruit can be known as 'the crack in the collection of Qiu Nuoke 1 丨 藉 在 in the second 3 in: = crack The same is true. Wafer, Xie LSA step ^ (four) of the program 37 201018755 ^zjoupu <Example 2> Support positional dependence during epitaxial growth and the influence of polishing after epitaxial growth to implement stupid crystal growth In the epitaxial growth process of the film), the contact between the wafer and the annular crystal seat is unavoidable. Because of the contact, the crystal is in close contact with the crystal seat, thereby locally causing the reaction gas to flow and thus solid. After the growth of the epitaxial crystal, when the wafer is lifted from the crystal holder, the fixing may be peeled off, and a crack may be introduced. Similarly, in the same manner as in the first embodiment, a wafer having a diameter of 3 mm is prepared. The surface of the wafer is subjected to stray crystal growth (worm crystal film formation), and preparation A wafer having a p/p_ structure. In this case, in the epitaxial growth, a wafer holder that is in contact with the crystal holder in a circular shape from the outermost peripheral portion of the wafer to the support position is used, and the support position is the same. The 15mm crystal seat 2 from the outermost peripheral portion of the wafer is similarly supported by a 41 mm crystal seat 3 from the outermost peripheral portion of the wafer, and the same support position is calculated from the outermost peripheral portion of the wafer. The 58 mm crystal holder 4 is changed in the range of the outermost peripheral portion to 6 mm in the outermost peripheral portion. In the same manner as in the first embodiment, the annealing treatment is performed using the LSa furnace which can be annealed in milliseconds, and the annealing temperature is not reached. Wafer rupture test was performed. The initial wafer temperature was 40 (TC. The results are shown in Table 2. Furthermore, the rupture rate 比率 the rate at which cracks occurred when processing 50 wafers of each level. 38 201018755 [Table 2 ] Maximum Arrival Temperature Crystal Cliff - Type ^^ Surface Grinding Amount (um) l'〇80°C 1100°C 1200°C 130 (TC Crystal Holder-1 0 0% 0% 2% 6% Crystal Holder-2 (1.5 Mm support) 0 0% 0% 0% 0% Crystal Holder-3 (4.1 mm support) 0 0% 0% 0% 0% Crystal Holder-4 (5.8 mm support) 0 0% 0% 0% 0% Crystal Holder -1 0.55 0% 0% 0% 2% Crystal Holder-1 ----- 1.1 0% 0% 0% 0% Crystal Holder-1 25 0% 0% 0% 0% Crystal Holder-2 1 0% 0% 0% 0% Crystal Holder-2 2.7 0% 0% 0% 0%
而且，作為使用晶座1及晶座2來磊晶成長的晶圓， 對於在蠢晶成長後改變晶圓背面的研磨量來進行研磨，將 因與晶座的IU著而導人的劃痕予以去除的晶圓亦實施測 試。將結果示於表2。 生 :田琢π禾可知，又付1 mm更内側而固著裂紋處於 最外周算起1 mm更内侧的晶圓不會發生破裂。另一方 可知，藉由將背面研磨大於等於i _，可抑制破裂的 而且，當支持6mm以内時，因蠢 面沈積(d—ition)，於背面外周蟲晶成== 周部的平坦度（flatness)下降，因而不佳‘” 使 雖然本發明已以實施例揭露如上， 本發明，任何所屬技術領域中具有通、、、、並非用以阳 本發明之精神和範圍内，當可作些 知識者，在不朋 發明之保護範圍當視後附之中請^ 更動與潤飾’故 1靶圍所界定者為准 39 201018755 32560pif 【圖式簡單說明】 態的=表示本發明的珍晶圓的製造方法的第-實施形 態的=表示本發明的發晶圓的製造方法的第二實施形 圖3是表示M0SFET的剖面示意圖。 質分雜質濃度與接面深度的關係中表示箱形的雜Further, as a wafer which is epitaxially grown using the crystal holder 1 and the crystal holder 2, the amount of polishing on the back surface of the wafer is changed after the growth of the stray crystal, and the scratch is caused by the IU of the crystal seat. The wafers to be removed are also tested. The results are shown in Table 2. Health: Tian Hao π Wo knows that the wafer with a 1 mm inner side and a fixed crack at the outermost circumference of 1 mm will not crack. On the other hand, by grinding the back surface by more than or equal to i _, cracking can be suppressed, and when it is within 6 mm, due to the d-ition deposition, the flatness of the outer peripheral worm crystals == circumference ( The present invention has been disclosed in the above embodiments, and the present invention is not intended to be used in the spirit and scope of the present invention. The knowledge person, in the scope of protection of the invention, please refer to the change and refinement of the 'target 1 target definition'. 39 201018755 32560pif [Simple diagram] The state = the representative wafer of the invention The second embodiment of the manufacturing method of the wafer according to the present invention is a cross-sectional view showing the MOSFET. The relationship between the impurity concentration of the impurity and the depth of the junction indicates a box-shaped impurity.
Q 行為小⑴是表示藉由退火_原子及雜質的 圖。圖6是表示本發明㈣晶圓的第—實施形態的平面 圖7,表示LSA裝置的模式圖。 構件)圖：ΪΪ圖7的LSA裝置中所用的夾盤(晶圓支持 是Λ示本發明的的緣部的放大剖面圖。 圖U 二明:曰所用的氣相成長裝置的模式圖。 【主要元件符mr晶座射晶圓㈣係的放大圖。 1 ·雷射瞬間退火裝置 2:連續振盪型雷射 2R :晶圓直徑尺寸 3 : XY掃描平台 4 :衰減器 201018755 5 ·南溫計 6 :鏡面 302 :上表面 304 :下表面The small Q behavior (1) is a graph showing the annealing of atoms and impurities. Fig. 6 is a plan view showing a first embodiment of the wafer of the fourth embodiment of the present invention, showing a schematic view of the LSA device. Fig.: A chuck used in the LSA apparatus of Fig. 7 (wafer support is an enlarged cross-sectional view showing the edge of the present invention. Fig. U is a schematic diagram of a vapor phase growth apparatus used for 曰. Magnification of the main component mr crystallographic wafer (4) 1 · Laser instant annealing device 2: continuous oscillation type laser 2R: wafer diameter size 3 : XY scanning platform 4 : attenuator 201018755 5 · south temperature meter 6: mirror 302: upper surface 304: lower surface
7:光束整形光學系統 8 :功率計 10 :夾盤 20 :冷卻板 22、102、152 24、104、154 26、156、306 :周邊部 30、158、308 :本體 32 :冷卻路徑 40 :冷卻單元 42 :冷卻管線 100 :絕緣體層 150 :加熱器模組 160 :加熱單元 164 :加熱元件 170 :導線 180 :可變電源單元 190 :溫度探頭 200 :夾盤控制器 300 :上部板 500 :裙套 A :内徑 41 201018755 A1 :假想中心轴、寬度 A2、E :寬度 B :直徑 C :深度 E:安全係數 E1 :氣相成長裝置 E2 :晶座 E21 :晶圓載置部 E211 :第一凹部 E212 :第二凹部 E213 :晶圓支持部 E3 :反應容器 E31 :上側圓頂 E32 :下側圓頂 E33 :圓頂安裝體 E34 :晶座支持部 E331 :反應氣體供給管 E332 :反應氣體排出管 E34 :晶座支持部 E4 :加熱裝置 EP :磊晶層 ER :旋轉軸 EW .蠢晶晶圓 L :長度7: Beam shaping optical system 8: power meter 10: chuck 20: cooling plates 22, 102, 152 24, 104, 154 26, 156, 306: peripheral portions 30, 158, 308: body 32: cooling path 40: cooling Unit 42: cooling line 100: insulator layer 150: heater module 160: heating unit 164: heating element 170: wire 180: variable power unit 190: temperature probe 200: chuck controller 300: upper plate 500: skirt A: inner diameter 41 201018755 A1: imaginary central axis, width A2, E: width B: diameter C: depth E: safety factor E1: vapor phase growth device E2: crystal holder E21: wafer mounting portion E211: first concave portion E212 : Second recess E213 : Wafer support portion E3 : Reaction container E31 : Upper side dome E32 : Lower side dome E33 : Dome mounting body E34 : Crystal holder support portion E331 : Reaction gas supply tube E332 : Reaction gas discharge tube E34 :Crystal support portion E4 : Heating device EP : Epitaxial layer ER : Rotation axis EW . Amorphous wafer L : Length
Md :汲極 201018755Md: bungee jumping 201018755
Mex :源極、汲極擴散區域 Mos : MOSFET Ms :源極 r :距離Mex : source, drain diffusion region Mos : MOSFET Ms : source r : distance
Rl、R2 :曲率半徑 Ί1、T2、T3、T4 :厚度 TS :溫度信號 W:半導體晶圓 ® W11 :第-傾斜面 W12 :第二傾斜面 W13 :第一曲面 W14 :第二曲面 W23、W27 :主面 W24 :表面側倒稜部 W28 :背面側倒稜部 Wo :晶圓直徑方向 ❿ Wr ··背面Rl, R2: radius of curvature Ί1, T2, T3, T4: thickness TS: temperature signal W: semiconductor wafer® W11: first-inclined surface W12: second inclined surface W13: first curved surface W14: second curved surface W23, W27 : Main surface W24 : Surface side chamfered portion W28 : Back side chamfered portion Wo : Wafer diameter direction ❿ Wr ·· Back surface
Wrt :最外周部 Wt :端面 Wu :表面 Wut :表面最外周 Xi :接面深度 43Wrt : outermost peripheral part Wt : end surface Wu : surface Wut : outermost surface of the surface Xi : joint depth 43
Claims (1)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2008250776 | 2008-09-29 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TW201018755A true TW201018755A (en) | 2010-05-16 |
| TWI417431B TWI417431B (en) | 2013-12-01 |
Family
ID=42059521
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW98133034A TWI417431B (en) | 2008-09-29 | 2009-09-29 | Silicon wafer and its manufacturing method |
| TW102138135A TWI535901B (en) | 2008-09-29 | 2009-09-29 | Silicon wafer and manufacturing method thereof |
Family Applications After (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW102138135A TWI535901B (en) | 2008-09-29 | 2009-09-29 | Silicon wafer and manufacturing method thereof |
Country Status (3)
| Country | Link |
|---|---|
| JP (1) | JP5569392B2 (en) |
| TW (2) | TWI417431B (en) |
| WO (1) | WO2010035510A1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9631297B2 (en) | 2012-08-09 | 2017-04-25 | Sumco Corporation | Method of producing epitaxial silicon wafer and epitaxial silicon wafer |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106298625B (en) * | 2016-08-22 | 2019-06-28 | 沈阳拓荆科技有限公司 | A kind of hierarchic structure ceramic ring |
| JP7332398B2 (en) | 2019-09-04 | 2023-08-23 | キオクシア株式会社 | semiconductor wafer |
Family Cites Families (20)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04356917A (en) * | 1991-06-03 | 1992-12-10 | Matsushita Electric Ind Co Ltd | Laser anneal apparatus |
| JPH08195366A (en) * | 1995-01-13 | 1996-07-30 | Mitsubishi Materials Shilicon Corp | Wafer polished on both sides and manufacture thereof |
| JP3935977B2 (en) * | 1995-05-16 | 2007-06-27 | Ｓｕｍｃｏ Ｔｅｃｈｘｉｖ株式会社 | Notched semiconductor wafer |
| JPH09251934A (en) * | 1996-03-18 | 1997-09-22 | Hitachi Ltd | Manufacturing method of semiconductor integrated circuit device and semiconductor wafer |
| JP2000114329A (en) * | 1998-09-29 | 2000-04-21 | Yuhi Denshi Kk | Method and device for inspecting ground edge section of substrate |
| JP4109371B2 (en) * | 1999-01-28 | 2008-07-02 | Ｓｕｍｃｏ Ｔｅｃｈｘｉｖ株式会社 | Semiconductor wafer |
| TW513772B (en) * | 2000-09-05 | 2002-12-11 | Komatsu Denshi Kinzoku Kk | Apparatus for inspecting wafer surface, method for inspecting wafer surface, apparatus for judging defective wafer, method for judging defective wafer and information treatment apparatus of wafer surface |
| JP4218253B2 (en) * | 2001-05-10 | 2009-02-04 | パナソニック株式会社 | Cross-flow fan for air conditioner |
| JP4123861B2 (en) * | 2002-08-06 | 2008-07-23 | 株式会社Ｓｕｍｃｏ | Manufacturing method of semiconductor substrate |
| JP3960911B2 (en) * | 2002-12-17 | 2007-08-15 | 東京エレクトロン株式会社 | Processing method and processing apparatus |
| JP2005311025A (en) * | 2004-04-21 | 2005-11-04 | Naoetsu Electronics Co Ltd | Manufacturing method of silicon wafer, and the silicon wafer manufactured thereby |
| JP2006064975A (en) * | 2004-08-26 | 2006-03-09 | Olympus Corp | Microscope and thin plate edge inspection apparatus |
| JP2006128440A (en) * | 2004-10-29 | 2006-05-18 | Renesas Technology Corp | Semiconductor manufacturing equipment and method of manufacturing semiconductor device |
| DE102005034120B4 (en) * | 2005-07-21 | 2013-02-07 | Siltronic Ag | Method for producing a semiconductor wafer |
| JP2007210875A (en) * | 2005-07-29 | 2007-08-23 | Nuflare Technology Inc | Vapor phase deposition apparatus and vapor phase deposition method |
| JP5135743B2 (en) * | 2005-09-28 | 2013-02-06 | 富士通セミコンダクター株式会社 | Manufacturing method of semiconductor device |
| JP2007305968A (en) * | 2006-04-14 | 2007-11-22 | Covalent Materials Corp | Silicon wafer, method of manufacturing the same, and silicon wafer for semiconductor device |
| JP2007303853A (en) * | 2006-05-09 | 2007-11-22 | Nikon Corp | End inspection device |
| JP2008153442A (en) * | 2006-12-18 | 2008-07-03 | Renesas Technology Corp | Method of manufacturing semiconductor device |
| JP2008294397A (en) * | 2007-04-25 | 2008-12-04 | Toshiba Corp | Method of manufacturing semiconductor device |
-
2009
- 2009-09-29 TW TW98133034A patent/TWI417431B/en active
- 2009-09-29 WO PCT/JP2009/005001 patent/WO2010035510A1/en active Application Filing
- 2009-09-29 TW TW102138135A patent/TWI535901B/en active
- 2009-09-29 JP JP2010530752A patent/JP5569392B2/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9631297B2 (en) | 2012-08-09 | 2017-04-25 | Sumco Corporation | Method of producing epitaxial silicon wafer and epitaxial silicon wafer |
Also Published As
| Publication number | Publication date |
|---|---|
| TWI417431B (en) | 2013-12-01 |
| JPWO2010035510A1 (en) | 2012-02-23 |
| TWI535901B (en) | 2016-06-01 |
| WO2010035510A1 (en) | 2010-04-01 |
| JP5569392B2 (en) | 2014-08-13 |
| TW201425664A (en) | 2014-07-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR101272711B1 (en) | Silicon wafer and method of manufacturing same | |
| TW200806830A (en) | Monocrystalline semiconductor wafer comprising defect-reduced regions and method for producing it | |
| TWI482224B (en) | Method for surface treatment of semiconductor substrates | |
| US20110227199A1 (en) | Method for producing semiconductor substrate, semiconductor substrate, method for manufacturing electronic device, and reaction apparatus | |
| TW201203445A (en) | Methods and apparatus for deposition processes | |
| TW201025453A (en) | Silicon wafer and method of manufacturing the same | |
| EP2478553A1 (en) | Methods of solid phase recrystallization of thin film using pulse train annealing method | |
| JP6163442B2 (en) | Semiconductor manufacturing apparatus and semiconductor device manufacturing method | |
| KR102138949B1 (en) | Method for producing sos substrates, and sos substrate | |
| TW201018755A (en) | Silicon wafer and manufacturing method thereof | |
| JP2011029429A (en) | Method for heat treatment of silicon wafer | |
| JP2018190903A (en) | Semiconductor wafer manufacturing method and semiconductor wafer | |
| JP2011171377A (en) | Method of manufacturing silicon wafer | |
| JP2003077855A (en) | Heat treatment apparatus and method | |
| JP5517354B2 (en) | Heat treatment method for silicon wafer | |
| TWI331772B (en) | Wafer processing method, semiconductor device manufacturing method, and wafer processing apparatus | |
| TW200818321A (en) | Semiconductor on insulator structure made using radiation annealing | |
| JP2015154045A (en) | Semiconductor device manufacturing method | |
| JP2004055694A (en) | Manufacturing method for semiconductor substrate including insulated silicon single crystal layer | |
| JP7084805B2 (en) | Method for Manufacturing Group III Nitride Single Crystal Substrate and Group III Nitride Single Crystal Laminate | |
| Skorupa et al. | Advanced thermal processing of semiconductor materials in the msec-range | |
| WO2016053629A1 (en) | Surface photovoltage calibration standard | |
| JP2011061015A (en) | Heat treatment method, and heat treatment apparatus | |
| JPS6340791A (en) | Laser annealing method | |
| JP2003224082A (en) | Silicon ring for holding silicon wafer in light irradiation thermal treatment equipment |