JP2008294397A - Method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device that can conduct heat treatments, while reducing wafer cracking. <P>SOLUTION: A method of manufacturing a semiconductor device that involves a heat treatment of a semiconductor substrate 11; removes a superficial layer from an upper surface 34 of an edge part of the semiconductor substrate 11, bevel surfaces 32 and 33 of the edge part of the semiconductor substrate and a side surface 31 of the edge part of the semiconductor substrate 11; and conducting the heat treatment of the semiconductor substrate 11, by irradiating the semiconductor substrate 11 with a light having a pulse width range of 0.1 ms to 100 ms from a light source, after the superficial layer is removed. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device in which a semiconductor substrate is heated by a high-density light source.

  Conventionally, in order to improve performance of a large scale integrated circuit (LSI), it has been promoted to increase the degree of integration of elements, that is, to miniaturize elements constituting the LSI.

  In order to miniaturize this element, it is necessary not only to reduce the area of the impurity diffusion region, but also to make the diffusion region in the depth direction shallower. Therefore, for example, when forming an impurity diffusion region such as a source / drain region or a functional region such as a channel region immediately below the gate insulating film, heat treatment (annealing) for ion implantation and subsequent electrical activation of the impurity is performed. It is important to optimize.

  As impurity ions to be ion-implanted, boron (B) ions, phosphorus (P) ions, or arsenic (As) ions are mainly used. These impurity ions have a large diffusion coefficient in silicon (Si). Therefore, in RTA (Rapid Thermal Anneal) using a halogen lamp, inward diffusion and outward diffusion of impurity ions occur, and it becomes increasingly difficult to form a shallow impurity diffusion region.

  This inward diffusion and outward diffusion can be suppressed by lowering the annealing temperature. However, when the annealing temperature is lowered, the activation rate of impurity ions is greatly reduced. For this reason, the electrical resistance value of the impurity diffusion region is increased, and the characteristics of the semiconductor element are significantly deteriorated. Therefore, it is difficult to form an impurity diffusion region with a low shallow resistance even if a technique of lowering the annealing temperature is employed.

  As described above, it is difficult to form a low resistance and shallow (20 nm or less) impurity diffusion region by the RTA process using a conventional halogen lamp.

  In recent years, therefore, an annealing method using a flash lamp in which a rare gas such as xenon (Xe) is sealed has been studied as a means for improving the activation rate in a very short time. The 1/2 pulse width of the flash lamp is about 10 milliseconds. Therefore, in annealing using a flash lamp, the time during which the wafer upper surface is kept at a high temperature is extremely short. Therefore, the annealing using the flash lamp can activate the impurities while suppressing the diffusion of the impurities implanted into the upper surface of the wafer.

  However, the annealing method (FLA: Flash Lamp Annealing) using a flash lamp has the following problems.

  That is, in the FLA, the wafer is previously heated to about 500 ° C. by a heater. In this heated state, the flash lamp is irradiated with light, and the upper surface of the wafer is heated to a high temperature of 1100 ° C. or higher in a short time of about 1 to 10 milliseconds.

  As a result, the temperature of the upper surface of the wafer instantaneously rises from around 500 ° C. to 1100 ° C. or more. A temperature difference is generated between the upper surface side and the lower surface side of the wafer, and thermal stress increases inside the wafer. Due to the large thermal stress inside the wafer, crystal defects and cracks may occur in the outer peripheral portion and inside of the wafer, for example, in a depth range of about 30 to 50 μm.

  Further, due to the difference in heat radiation efficiency between the inner and outer peripheral portions of the wafer, a large thermal stress can be generated between the inner side and the outer side of the wafer. In particular, a large number of crystal defects may occur at the edge of the outer periphery of the wafer due to concentration of large thermal stress. In addition, since a force for deforming the wafer is exerted by the thermal stress inside the wafer, the wafer moves on the processing table, and the end of the wafer collides with the side wall of the stage, and cracks and scratches are likely to occur.

  In addition, the outer peripheral edge of the wafer is already gripped by the transfer arm in the process of passing through the previous various processes before the FLA process, and the trace that has touched the wafer holding jig in the processing apparatus, etc. There are many contact marks (scratches).

  Here, as a conventional method for manufacturing a semiconductor device, there is a method for removing a surface layer on a lower surface of a semiconductor substrate that is in contact with a holder when performing high-temperature heat treatment (see, for example, Patent Document 1).

Thereby, in the conventional method for manufacturing a semiconductor device, dislocations that can be generated by subsequent heat treatment due to damage or dislocations due to contact of the holder or the like are reduced.
JP 2002-134521 A

  An object of this invention is to provide the manufacturing method of the semiconductor device which can heat-process, reducing a wafer crack.

A method for manufacturing a semiconductor device according to one embodiment of the present invention includes:
In a method for manufacturing a semiconductor device including a step of heat-treating a semiconductor substrate,
Removing the upper surface of the end portion of the semiconductor substrate, the bevel surface of the end portion of the semiconductor substrate and the surface layer portion of the side surface of the end portion of the semiconductor substrate;
After the surface layer portion is removed, the semiconductor substrate is subjected to heat treatment by irradiating the semiconductor substrate with light having a pulse width of 0.1 ms to 100 ms.

A method for manufacturing a semiconductor device according to another aspect of the present invention includes:
In a method for manufacturing a semiconductor device including a step of heat-treating a semiconductor substrate,
The semiconductor substrate is heated by irradiating the semiconductor substrate with light having a pulse width of 0.1 ms to 100 ms,
After the heat treatment of the semiconductor substrate, the upper surface of the end portion of the semiconductor substrate, the bevel surface of the end portion of the semiconductor substrate, and the surface layer portion on the side surface of the end portion of the semiconductor substrate are removed.

A method for manufacturing a semiconductor device according to still another aspect of the present invention includes:
In a method for manufacturing a semiconductor device including a step of heat-treating a semiconductor substrate,
Removing the lower surface of the end portion of the semiconductor substrate and the surface layer portion of the lower bevel surface of the end portion of the semiconductor substrate;
After the surface layer portion is removed, the semiconductor substrate is subjected to heat treatment by irradiating the semiconductor substrate with light having a pulse width of 0.1 ms to 100 ms.

  According to the method for manufacturing a semiconductor device of one embodiment of the present invention, heat treatment can be performed while reducing wafer cracking.

  When a wafer having the damage (crystal defects and cracks) existing in the prior art is present at the end, the thermal stress inside the wafer is increased again when the wafer is subjected to a heat treatment process after FLA. Even if the increase in thermal stress is moderate, the wafer is easily cracked starting from the damage because the mechanical strength of the wafer is reduced at the damaged portion.

  As described above, the damage generated at the outer peripheral edge of the wafer impairs the productivity of the semiconductor device.

  In addition, crystal defects may occur at the outer peripheral edge of the wafer in a high-temperature heat treatment process before the FLA process.

  The scratches and crystal defects at the outer peripheral edge part impair the strength of the wafer and have low resistance to internal or external forces.

  When such a wafer is subjected to FLA processing, the internal thermal stress rapidly increases, and the wafer may be cracked based on scratches or crystal defects at the outer peripheral edge.

  Since the degree of scratches and crystal defects varies depending on the wafer, the frequency of wafers to be broken during FLA processing also varies, but for example, about one crack in several hundreds may occur. When a wafer is cracked with a frequency of about one in every hundred, a hundreds of wafers are processed every day in a factory that mass-produces ICs, resulting in a problem of reduced productivity.

  Due to the damage caused by the FLA process as described above, there are a problem that the wafer breaks in the subsequent process and a problem that the wafer breaks during the FLA process due to the damage caused in the previous process.

As one of the countermeasures, it is conceivable to lower the light irradiation energy density by reducing the power of the FLA treatment, but in that case, sufficient activation of impurities cannot be expected.

  However, the above prior art (see, for example, Patent Document 1) does not reduce crystal defects or cracks that are problematic by FLA processing using a flash lamp or the like in consideration of damage at the wafer outer peripheral portion (near the bevel portion). Absent.

  According to the method for manufacturing a semiconductor device of one embodiment of the present invention, before the heat treatment step of heating the semiconductor substrate by irradiating light, the outer peripheral portion (the upper surface of the end, the bevel surface, the side surface) of the semiconductor substrate. Remove damage existing on the surface layer. This widens the process window of the heat treatment step, and greatly reduces the frequency with which the substrate breaks during the heat treatment.

  According to the method for manufacturing a semiconductor device of one embodiment of the present invention, after the thermal process of irradiating light to heat the semiconductor substrate, the outer peripheral portion (the upper surface of the end portion, the bevel surface, the side surface) of the semiconductor substrate. Remove damage existing on the surface layer. As a result, the frequency with which the semiconductor substrate breaks in the subsequent heat treatment step is greatly reduced.

  Embodiments to which the present invention is applied will be described below with reference to the drawings.

  A method for manufacturing a semiconductor device according to this example will be described. In the following, for the sake of simplicity, description will be given focusing on the configuration of one MOS transistor.

  1A to 1D are schematic views showing respective steps of a semiconductor device manufacturing method according to Example 1 which is an aspect of the present invention. FIG. 2 is an enlarged schematic view showing a cross section of the end region of the wafer after polishing in FIG. 1C.

  First, as shown in FIG. 1A, an element isolation region 11, a gate insulating film 12a, and a gate electrode 12b are formed on a semiconductor substrate 10 such as silicon by a known method. As the wafer 10, for example, a bulk single crystal silicon wafer, an epitaxial wafer, an SOI wafer, or the like is selected.

  Next, as shown in FIG. 1B, impurity ions 14a are implanted into the source / drain extension regions 14b on the upper surface of the wafer 10 by an ion implantation method using a gate electrode 12b and a resist film 13b formed in a desired pattern shape by a photolithographic method as a mask. Injected. After the ion implantation step, the resist film 13b is peeled off and removed.

  Next, as shown in FIG. 1C, the upper surface, the bevel surface, and the surface layer portion of the side surface of the wafer 10 are polished to remove about 30 μm to 100 μm. Thereby, defects, cracks and the like formed in the surface layer portion at the end of the wafer 10 can be removed. In FIG. 1C, a dotted line 15 represents the surface position of the end portion of the wafer 10 before polishing (removal of the surface layer portion). Further, the solid line 21 represents the surface position of the end portion of the wafer 10 after polishing (removal of the surface layer portion).

  The method for polishing the edge of the wafer 10 may be a generally known method. For example, the wafer 10 is vacuum chucked from the lower surface and fixed on the substrate. Then, the wafer 10 is brought into pressure contact with the polishing pad while rotating the wafer 10 together with the base material. Then, a polishing liquid in which fine abrasive grains are dispersed is supplied to the contact portion between the polishing pad and the wafer 10. Thereby, the surface layer part of the edge part of the wafer 10 which is in contact with the polishing pad can be removed by polishing.

  Further, the thickness of the polished portion of the wafer 10 can be estimated based on the processing time obtained by measuring the correspondence between the polishing time and the amount of shaving in advance and determining the conditions. The amount of shaving during the condition setting can be estimated by observing the shape change of the wafer cross section before and after polishing using an electron microscope or the like.

  Here, as shown in FIG. 2, a side surface 31, a bevel surface 32, and a bevel surface 33 are formed at the end of the wafer 10.

  In FIG. 2, the shaded portion represents the surface layer portion at the end of the wafer 10 removed by polishing. In the present embodiment, as described above, the thickness of the upper surface 34 at the end of the wafer 10, the bevel surfaces 32 and 33, and the surface layer portion from which the side surface 31 is removed is in the range of 30 μm to 100 μm.

  As a result, damage such as scratches, cracks, crystal defects, and the like that may exist on the upper surface 34, the bevel surfaces 32 and 33, and the side surface 31 at the end are also removed at the same time. Therefore, the FLA process can be performed while avoiding the deterioration of the strength of the wafer 10 due to these damages.

  Note that, for example, an extremely minute linear pattern may exist on the surface of the end portion of the polished wafer 10. However, this is a trace of polishing abrasive grains, and such a trace is a groove having a very shallow depth, so that it is considered that the strength of the wafer 10 is not affected.

  Further, as shown in FIG. 2, the lower surface of the end portion of the wafer 10 may be further polished. Thereby, damages such as scratches, cracks and crystal defects on the lower surface of the end portion of the wafer 10 can be removed.

  Here, FIG. 3 is a diagram showing an observation result by X-ray topography for a wafer heat-treated with a high-density light source.

  As shown in FIG. 3, it is considered that the slip dislocation generation region generated in the vicinity of the bevel tends to concentrate in the range of 1 mm to 3 mm inward from the boundary between the upper surface of the wafer and the bevel surface.

  That is, as shown in FIG. 2, the surface layer portion of the upper surface 34 at the end of the wafer 10 is removed from the boundary 35 between the upper surface 34 at the end of the wafer 10 and the bevel surface 32. Thereby, generation | occurrence | production of the slip dislocation near a bevel can be suppressed.

  Next, the FLA process is performed using a flash lamp annealing apparatus.

  As illustrated in FIG. 1D, the flash lamp annealing apparatus includes a hot plate 16 and a flash lamp light source 17.

  The hot plate 16 is a metal plate incorporating a resistance heater. The temperature of the hot plate 16 is controlled by a thermocouple thermometer embedded inside.

  The flash lamp light source 17 is provided with a plurality of lamps facing the wafer 10. The lamp is, for example, a lamp in which a rare gas such as Xe gas is sealed.

The flash lamp light source 17 emits light 18 having a pulse width of 0.1 to 100 milliseconds. The energy density of the light 18 emitted from the flash lamp light source 17 is, for example, 25 J / cm ² on the upper surface of the wafer 10.

  As shown in FIG. 1D, in the heat treatment in the FLA process, first, the wafer 10 is placed on the hot plate 16, and the wafer 10 is preliminarily heated to about 300 ° C. to 600 ° C. With the wafer 10 preheated, the wafer 10 is heated from above by the light 18 emitted from the flash lamp light source 17. The wafer 10 is irradiated with light 18 in an atmosphere of an inert gas such as nitrogen gas or argon gas, and the upper surface of the wafer 10 is heated.

  By the heat treatment, the impurity of the ion implantation layer is activated, and the impurity diffusion layer 19 is formed.

  Here, the effect when this embodiment is applied will be examined by comparing conventional examples.

  FIG. 4 is a graph showing a process margin for wafer cracking in the FLA process of the semiconductor device manufacturing method according to the first embodiment.

  On the other hand, FIG. 5 is a graph showing a process margin for wafer cracking in the FLA process of the conventional method for manufacturing a semiconductor device.

  As shown in FIGS. 4 and 5, the present example has a higher irradiation energy density and preheating temperature that can be processed without cracking the wafer than the conventional example. That is, in the present embodiment, it can be seen that the process window is wide.

  During the FLA process, the upper surface of the wafer instantaneously becomes high temperature, and the temperature on the lower surface side does not follow the temperature of the upper surface. For this reason, the upper surface side expands, and a stress to be deformed acts. However, since the lower surface side has a smaller thermal expansion force than the upper surface, it cannot follow the thermal expansion. As a result, the stress inside the wafer is increased, and when the wafer edge is damaged and the strength is reduced as in the conventional example, it is considered that the wafer is destroyed.

  In the present embodiment, the reduction in the strength of the wafer is suppressed by polishing and removing the surface layer portion where damage is present on the bevel surface and side surface of the wafer. As a result, as shown in FIG. 4, it is considered that the process window of the method for manufacturing the semiconductor device according to the present embodiment is widened.

  As described above, according to the method of manufacturing a semiconductor device according to this embodiment, the FLA process can be performed while reducing wafer cracking.

  As described above, in Example 1, before the heat treatment process of irradiating light to heat the semiconductor substrate, it exists in the surface layer portion of the outer peripheral portion (upper surface, bevel surface, side surface) of the semiconductor substrate. An example of a method for removing damage to be performed has been described.

  In this embodiment, an example of a method for removing damage existing on the surface layer portion of the outer peripheral portion (the upper surface of the end portion, the bevel surface, and the side surface) of the semiconductor substrate after the thermal process of heating the semiconductor substrate by irradiating light. Is described.

  6A to 6J are schematic views showing each step of the method for manufacturing a semiconductor device according to the second embodiment which is an aspect of the present invention. 6A to 6J, the same reference numerals as those in FIGS. 1A to 1D indicate the same configurations as those in the first embodiment. Note that the steps from FIG. 6A to FIG. 6D are the same as the steps from FIG. 1A to FIG. 1D.

  First, as shown in FIG. 6A, as in the first embodiment, an element isolation region 11, a gate insulating film 12a, and a gate electrode 12b are formed on a semiconductor substrate 10 such as silicon by a known method. .

  Next, as shown in FIG. 6B, in the same manner as in the first embodiment, impurities are formed in the source / drain extension region 14b on the upper surface of the wafer 10 using the gate electrode 12b and the resist film 13b formed in a desired pattern shape by the photolithography method as a mask. Ions 14a are implanted by an ion implantation method. After the ion implantation step, the resist film 13b is peeled off and removed.

  Next, as shown in FIG. 6C, as in Example 1, the upper surface, the bevel surface, and the surface layer portion of the side surface of the wafer 10 are polished to remove about 30 μm to 100 μm. Thereby, defects, cracks and the like formed in the surface layer portion at the end of the wafer 10 can be removed.

  Next, the FLA process is performed using a flash lamp annealing apparatus.

  As shown in FIG. 6D, as in the first embodiment, in the heat treatment in the FLA process, first, the wafer 10 is placed on the hot plate 16, and the wafer 10 is preliminarily heated to about 300 ° C. to 600 ° C. The With the wafer 10 preheated, the wafer 10 is heated from above by the light 18 emitted from the flash lamp light source 17. The wafer 10 is irradiated with light 18 in an atmosphere of an inert gas such as nitrogen gas or argon gas, and the upper surface of the wafer 10 is heated.

  By the heat treatment, the impurity of the ion implantation layer is activated, and the impurity diffusion layer 19 is formed. Note that this heat treatment step may be a heat treatment such as RTA.

  Next, as shown in FIG. 6E, a gate sidewall insulating film (spacer) 20 is formed by a known method. Thereafter, impurity ions 14c are implanted into the upper surface of the wafer 10 using the gate sidewall insulating film 20, the gate electrode 12b, and the resist film 13e formed in a desired pattern shape by photolithography as a mask. After the ion implantation step, the resist film 13e is peeled off and removed. A region 14d into which impurities are implanted is formed by ion implantation, which finally becomes a source / drain region.

  Next, as in Example 1, as shown in FIG. 6F, about 30 μm to 100 μm are removed by polishing the upper surface, the bevel surface, and the surface layer portion of the side surface of the wafer 10. Thereby, for example, defects, cracks, and the like formed in the surface layer portion of the end portion of the wafer 10 by the heat treatment shown in FIG. 6D or the like can be removed.

  In FIG. 6F, a dotted line 15a (corresponding to the solid line 21 described above) represents the surface position of the end portion of the wafer 10 before polishing (removal of the surface layer portion). Further, the solid line 21a represents the surface position of the end portion of the wafer 10 after polishing (removal of the surface layer portion).

  Next, as shown in FIG. 6G, the wafer 10 is heated by the FLA method, similarly to the step shown in FIG. 6D. As a result, the impurity ions 14 c implanted into the portion 14 d to be the source / drain region are activated, and the source / drain region 22 is formed on the upper surface of the wafer 10.

  Next, as in Example 1, as shown in FIG. 6H, the upper surface, the bevel surface, and the surface layer portion of the side surface of the wafer 10 are polished to remove about 30 μm to 100 μm. Thereby, for example, defects, cracks, and the like formed in the surface layer portion of the end portion of the wafer 10 by the heat treatment shown in FIG. 6G or the like can be removed.

  In FIG. 6H, a dotted line 15b (corresponding to the solid line 21a described above) represents the surface position of the end portion of the wafer 10 before polishing (removal of the surface layer portion). Further, the solid line 21b represents the surface position of the end portion of the wafer 10 after polishing (removal of the surface layer portion).

  Next, as shown in FIG. 6I, an interlayer insulating film 23 is deposited on the entire surface of the wafer by a CVD method or the like. Thereafter, contact holes 24 are opened in the source / drain regions and the gate region by a known method.

  Subsequently, a metal film 25 such as cobalt (Co) is deposited on the upper surface of the wafer by sputtering or the like. In this state, annealing treatment (silicidation annealing) is performed in an inert gas atmosphere such as nitrogen at a temperature of about 450 ° C. to 550 ° C. for 30 seconds to 60 seconds using RTA or the like.

  By performing this silicidation annealing, as shown in FIG. 6I, a low-resistance metal silicide layer 26 is formed on the upper surfaces of the source / drain region and the gate region opened by the contact holes.

  Thereafter, the unreacted metal film is removed by, for example, a method of immersing in an acidic solution. Then, a plug 27 is formed by filling a metal such as tungsten in the contact hole on the metal silicide layer. Thereby, electrical connection to the source / drain region and the gate region becomes possible.

  As described above, by polishing the upper surface, the bevel surface, and the surface layer portion of the side surface of the wafer after the FLA processing (FIG. 6H), damage caused during the FLA processing is also removed, so that the strength of the wafer is increased. Almost never decreases.

  Therefore, in the thermal process after the FLA process, it is possible to receive a process without deteriorating the resistance against the thermal stress generated inside the wafer. Thereby, the frequency with which the wafer breaks can be greatly reduced.

  As described above, in this embodiment, the surface layer portion at the edge of the wafer is removed (FIGS. 6C and 6F) before the two heat treatments (FIGS. 6D and 6G). . For example, when the second heat treatment is set to a higher temperature than the first heat treatment, the surface layer portion of the edge of the wafer is removed after the first heat treatment and before the second heat treatment. (FIG. 6F) is particularly important because it reduces damage to the edge of the wafer during the second heat treatment.

  Here, FIG. 7 is a graph showing the frequency of cracking in the silicidation annealing process for the wafer processed by this embodiment and the conventional method for manufacturing a semiconductor device.

  FIG. 7 shows the RTA processing pass rate through which the wafer passes without breaking when 240 wafers are processed by the semiconductor device manufacturing method of this embodiment and the RTA processing of the silicidation annealing process is performed. ing. Further, as a comparative example, when the RTA process is performed on 240 wafers without removing the wafer side surface or the bevel surface layer after the FLA process, the wafer passes through the RTA process without breaking. Shows the rate.

  As shown in FIG. 7, when the wafer side surface and the beveled surface layer portion were not removed after the FLA process as in the conventional example, the rate of RTA processing without cracking the wafer was about 80%. .

  On the other hand, in the method of manufacturing a semiconductor substrate according to this example, no wafer cracking occurred.

  Thus, it can be said that the wafer cracking frequency in the thermal process after the FLA process is drastically suppressed by the manufacturing method of the semiconductor device according to this example.

  As described above, according to the method of manufacturing a semiconductor device according to this embodiment, the FLA process can be performed while reducing wafer cracking.

  As described above, in Example 1, before the heat treatment process of irradiating light to heat the semiconductor substrate, it exists in the surface layer portion of the outer peripheral portion (upper surface, bevel surface, side surface) of the semiconductor substrate. An example of a method for removing damage to be performed has been described.

  Therefore, in this embodiment, after the thermal process of irradiating light to heat the semiconductor substrate, the damage existing on the surface layer portion of the outer peripheral portion (at least the lower surface of the end portion and the lower bevel surface) of the semiconductor substrate is removed. An example of the method to do is described.

  A method for manufacturing a semiconductor device according to this example will be described. In the following, for the sake of simplicity, description will be given focusing on the configuration of one MOS transistor.

  8A to 8D are schematic views showing each step of the method for manufacturing a semiconductor device according to Example 3, which is an aspect of the present invention. FIG. 9 is a schematic diagram showing an enlarged cross section of the edge region of the wafer after polishing in FIG. 8C. In the figure, the same reference numerals as those in the first embodiment indicate the same configurations as those in the first embodiment.

  First, as shown in FIG. 8A, an element isolation region 11, a gate insulating film 12a, and a gate electrode 12b are formed on a semiconductor substrate 10 such as silicon by a known method. As the wafer 10, for example, a bulk single crystal silicon wafer, an epitaxial wafer, an SOI wafer, or the like is selected.

  Next, as shown in FIG. 8B, impurity ions 14a are implanted into the source / drain extension regions 14b on the upper surface of the wafer 10 by an ion implantation method using the gate electrode 12b and a resist film 13b formed in a desired pattern shape by a photolithography method as a mask. Injected. After the ion implantation step, the resist film 13b is peeled off and removed.

  Next, as shown in FIG. 8C, the lower surface of the end portion of the wafer 10 and the surface layer portion of the lower bevel surface are polished, for example, from the boundary 36 between the lower bevel portion and the lower surface toward the inside of the wafer. An area of about 100 μm to 400 μm (250 μm in FIG. 9) is removed. At this time, the surface layer portion is scraped in the depth direction by at least 10 μm or more (preferably about 30 μm to 100 μm as in the above-described embodiment).

  In FIG. 8C, a dotted line 15 represents the surface position of the end portion of the wafer 10 before polishing (removal of the surface layer portion). Further, the solid line 21c represents the surface position of the end portion of the wafer 10 after polishing (removal of the surface layer portion).

  Thereby, defects, cracks and the like formed on the lower surface of the end portion of the wafer 10 and the surface layer portion of the lower bevel surface can be removed.

  The method for polishing the end portion of the wafer 10 may be a generally known method as in the above-described embodiments. For example, the wafer 10 is vacuum chucked from the lower surface and fixed on the substrate. Then, the wafer 10 is brought into pressure contact with the polishing pad while rotating the wafer 10 together with the base material. Then, a polishing liquid in which fine abrasive grains are dispersed is supplied to the contact portion between the polishing pad and the wafer 10. Thereby, the surface layer part of the edge part of the wafer 10 which is in contact with the polishing pad can be removed by polishing.

  Further, the thickness of the polished portion of the wafer 10 can be estimated based on the processing time obtained by measuring the correspondence relationship between the polishing time and the amount of shaving in advance and determining the conditions. The amount of shaving during the condition setting can be estimated by observing the shape change of the wafer cross section before and after polishing using an electron microscope or the like.

  Here, as shown in FIG. 9, a side surface 31, a bevel surface 32, and a bevel surface 33 are formed at the end of the wafer 10.

  In FIG. 9, the shaded portion represents the surface layer portion at the end of the wafer 10 removed by polishing.

  As a result, damage such as scratches, cracks, crystal defects, and the like that may be present on the lower surface of the end portion and the lower bevel surface 33 are also removed at the same time. Therefore, the FLA process can be performed while avoiding the deterioration of the strength of the wafer 10 due to these damages.

  Note that, for example, an extremely minute linear pattern may exist on the surface of the end portion of the polished wafer 10. However, this is a trace of polishing abrasive grains, and such a trace is a groove having a very shallow depth, so that it is considered that the strength of the wafer 10 is not affected.

  Next, the FLA process is performed using a flash lamp annealing apparatus.

  As shown in FIG. 8D, the flash lamp annealing apparatus includes a hot plate 16 and a flash lamp light source 17.

  The hot plate 16 is a metal plate incorporating a resistance heater. The temperature of the hot plate 16 is controlled by a thermocouple thermometer embedded inside.

  The flash lamp light source 17 is provided with a plurality of lamps facing the wafer 10. The lamp is, for example, a lamp in which a rare gas such as Xe gas is sealed.

The flash lamp light source 17 emits light 18 having a pulse width of 0.1 to 100 milliseconds. The energy density of the light 18 emitted from the flash lamp light source 17 is, for example, 25 J / cm ² on the upper surface of the wafer 10.

  As shown in FIG. 8D, in the heat treatment in the FLA process, first, the wafer 10 is placed on the hot plate 16, and the wafer 10 is preliminarily heated to about 300 ° C. to 600 ° C. With the wafer 10 preheated, the wafer 10 is heated from above by the light 18 emitted from the flash lamp light source 17. The wafer 10 is irradiated with light 18 in an atmosphere of an inert gas such as nitrogen gas or argon gas, and the upper surface of the wafer 10 is heated.

  By the heat treatment, the impurity of the ion implantation layer is activated, and the impurity diffusion layer 19 is formed.

  Here, the effect when this embodiment is applied will be examined by comparing conventional examples.

  During the FLA process, the upper surface of the wafer instantaneously becomes high temperature, and the temperature on the lower surface side does not follow the temperature of the upper surface. For this reason, the upper surface side expands, and a stress to be deformed acts. However, since the lower surface side has a smaller thermal expansion force than the upper surface, it cannot follow the thermal expansion. As a result, the stress inside the wafer is increased, and when the wafer edge is damaged and the strength is reduced as in the conventional example, it is considered that the wafer is destroyed.

  In this embodiment, since the surface layer portion where the damage is present on the lower surface of the end portion of the wafer and the lower bevel surface is removed by polishing, a decrease in strength of the wafer is suppressed.

  As described above, according to the method of manufacturing a semiconductor device according to this embodiment, the FLA process can be performed while reducing wafer cracking.

  In each of the embodiments described above, the case where the surface layer portion at the edge of the wafer is removed by polishing has been described. However, the surface layer portion at the edge of the wafer may be removed by etching or cutting with an acid or alkali solution.

In each of the above-described embodiments, the case where a xenon flash lamp is used as a light source of FLA that is heat-treated with light having a pulse width of 0.1 msec to 100 msec has been described. However, the present invention is not limited to this, and can be applied to a light source such as a flash lamp using other rare gas, mercury, and hydrogen, or an arc discharge lamp. Further, the present invention can also be applied to a light source such as a laser having a wavelength of 500 nm to 11 μm, such as an excimer laser, an Ar laser, an N ₂ laser, a YAG laser, a titanium sapphire laser, a CO laser, and a CO ₂ laser.

It is a schematic diagram which shows the process of the manufacturing method of the semiconductor device which concerns on Example 1 which is 1 aspect of this invention. It is a schematic diagram which shows the process of the manufacturing method of the semiconductor device which concerns on Example 1 which is 1 aspect of this invention. It is a schematic diagram which shows the process of the manufacturing method of the semiconductor device which concerns on Example 1 which is 1 aspect of this invention. It is a schematic diagram which shows the process of the manufacturing method of the semiconductor device which concerns on Example 1 which is 1 aspect of this invention. It is a schematic diagram which expands and shows the cross section of the area | region of the edge part of the wafer after grinding | polishing in FIG. 1C. It is a figure which shows the observation result by the X-ray topograph with respect to the wafer heat-processed by the high-density light source. 6 is a graph showing a process margin for wafer cracking in the FLA process of the semiconductor device manufacturing method according to Example 1; It is a graph which shows the process margin with respect to the wafer crack in the FLA process of the manufacturing method of the conventional semiconductor device. It is a schematic diagram which shows the process of the manufacturing method of the semiconductor device which concerns on Example 2 which is 1 aspect of this invention. FIG. 6D is a schematic diagram showing a process of the semiconductor device manufacturing method following FIG. 6A. FIG. 6D is a schematic diagram showing a process of the semiconductor device manufacturing method following FIG. 6B. FIG. 6D is a schematic diagram showing a process of the semiconductor device manufacturing method following FIG. 6C. FIG. 6D is a schematic view showing a process of the semiconductor device manufacturing method following FIG. 6D. FIG. 6D is a schematic diagram showing a process of the semiconductor device manufacturing method following FIG. 6E. FIG. 6D is a schematic diagram illustrating a process of the semiconductor device manufacturing method following FIG. 6F. FIG. 6G is a schematic diagram showing a process of the semiconductor device manufacturing method following FIG. 6G. FIG. 6D is a schematic diagram illustrating a process of the semiconductor device manufacturing method following FIG. 6H. FIG. 6D is a schematic diagram showing a process of the semiconductor device manufacturing method following FIG. 6I. It is a graph showing the frequency of the crack in the silicidation annealing process with respect to the wafer processed with the manufacturing method of the present Example and the conventional semiconductor device. It is a schematic diagram which shows the process of the manufacturing method of the semiconductor device which concerns on Example 3 which is 1 aspect of this invention. It is a schematic diagram which shows the process of the manufacturing method of the semiconductor device following FIG. 8A. FIG. 8D is a schematic diagram illustrating a process of the semiconductor device manufacturing method following FIG. 8B. FIG. 8D is a schematic diagram illustrating a process of the semiconductor device manufacturing method following FIG. 8C. It is a schematic diagram which expands and shows the cross section of the area | region of the edge part of the wafer after grinding | polishing in FIG. 8C.

Explanation of symbols

10 Wafer 11 Element isolation region
12a Gate insulating film 12b Gate electrode 13b Resist 13e Resist 14a, 14c Impurity ion 14b Impurity implanted layer 14d Impurity implanted layers 15, 15a, 15b Surface position of wafer edge before removal of surface layer portion (dotted line)
16 Hot plate 17 Flash lamp light source 18 Light 19 Impurity diffusion layer (source / drain extension region)
20 Gate sidewall insulating film (spacer)
21, 21a, 21b, 21c Surface position of wafer edge after removal of surface layer portion (solid line)
22 Impurity diffusion layer (source / drain region)
23 Interlayer insulating film 24 Contact hole 25 Metal film 26 Metal silicide layer 27 Plug 31 Side surface 32, 33 Bevel surface 34 Upper surface 35 of wafer edge 36 Boundary between upper surface of wafer edge and bevel surface 36 Lower surface of wafer edge and bevel surface Border with

Claims (6)

In a method for manufacturing a semiconductor device including a step of heat-treating a semiconductor substrate,
Removing the upper surface of the end portion of the semiconductor substrate, the bevel surface of the end portion of the semiconductor substrate and the surface layer portion of the side surface of the end portion of the semiconductor substrate;
After the surface layer portion is removed, the semiconductor substrate is heat-treated by irradiating the semiconductor substrate with light having a pulse width of 0.1 ms to 100 ms. A method for manufacturing a semiconductor device, comprising: In a method for manufacturing a semiconductor device including a step of heat-treating a semiconductor substrate,
The semiconductor substrate is heated by irradiating the semiconductor substrate with light having a pulse width of 0.1 ms to 100 ms,
After the heat treatment of the semiconductor substrate, the upper surface of the end portion of the semiconductor substrate, the bevel surface of the end portion of the semiconductor substrate, and the surface layer portion of the side surface of the end portion of the semiconductor substrate are removed. Production method.   3. The method of manufacturing a semiconductor device according to claim 1, wherein a thickness of the surface layer portion to be removed is in a range of 30 μm to 100 μm.   4. The surface layer portion on the upper surface of the end portion is removed with respect to a range of 3 mm from the boundary between the upper surface of the end portion and the bevel surface of the semiconductor substrate. Semiconductor device manufacturing method. In a method for manufacturing a semiconductor device including a step of heat-treating a semiconductor substrate,
Removing the lower layer of the end portion of the semiconductor substrate and the surface layer portion of the lower bevel surface of the end portion of the semiconductor substrate;
After the surface layer portion is removed, the semiconductor substrate is heat-treated by irradiating the semiconductor substrate with light having a pulse width of 0.1 ms to 100 ms. A method for manufacturing a semiconductor device, comprising:   6. The method of manufacturing a semiconductor device according to claim 1, wherein the light source is a xenon flash lamp or a laser having a wavelength of 500 nm to 11 [mu] m.

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