200818321 九、發明說明： 【發明所屬之技術領域】 本發明係關於使用改良處理過程以製造半導體在絕緣 體上(SOI)結構之系統，方法以及產物，該改良處理過程包 含輻射退火，以及特別是雷射退火作為修整半導體層。 【先前4支彳标】 θ 至目前，在半導體在絕緣體上結構中最常使用半導體 材料為石夕。在文獻中該結構稱為矽在絕緣體上結構以及簡 稱為’’SOI”。SOI技術對於紐能薄膜電晶體，太陽能電池， 影像感測器，以及顯示器例如為主動陣列顯示器持續地變 為重要的。SOI結構包含薄層厚度單晶石夕(通常〇· 〇5—〇· 3微 米(50-300nm))，但是在一些情況下，厚度可高達2〇微米（ 20000nm)於絕緣材料上。 為了容易呈現出，下列說明係關於半導體在絕緣體 (SOI)上結構。以該特別型式S0I結構作說明將使本發明解 釋變為容易以及並不預期以及視為對本發明任何情況之限 制。在此簡稱SOI —般係指半導體在絕緣體上結構，包含非 限制性之石夕在絕緣體上結構。同樣地簡稱為Si〇Q 一般係 才曰半導體在玻璃上結構，包含非限制性之石夕在玻璃上結構 。SiOG名詞預期亦包含半導體在玻璃陶瓷上，包含非限制 性之石夕在玻璃陶瓷上結構。簡稱S0I包含Si〇G結構。 達成soi結構之各種方法包含⑴外延成長Si於晶格相 匹配之基板上;（2)黏接單晶矽晶片至另一矽晶片上，在該 矽晶片上成長出Si〇2氧化層，接著拋光或餘刻上部晶片向 200818321 下至例如0· 05至〇· 3微米（50—30_層單晶矽;以及⑶離 子植入法，其帽子(例如錢絲離子)雛人，在氧離子 植々it財將形成例如埋喪氧化物層於被Si覆蓋之石夕晶片 中，在氫離子植入情況中由石夕晶片分離(外延)薄的&層作 為黏接至具有氧化物層之另一 Si晶片。 先前兩種方法外延成長以及晶片一晶片黏接並未產生 有關費用及/或雜強度以及耐久性令人滿意、之結構。包 含離子植入後者方法已受到關切，以及特別地離子植入已 視為有細，目為所f要植人通常小於祕子植入所需要 能量之50%以及所需要量劑約為低於2個數量等級。 美國第5374564號專利揭示出一種使用熱處理過程之 處理步驟崎解晶_騰絲上。具有平雖表面石夕 晶片進行下驟:⑴藉由產生一層氣態微小氣泡植入之 離子轟擊矽晶片表面的植入，其界定出石夕晶片下部區域以 及構成薄的矽薄膜上側區域;（ii)矽晶片平坦平面接觸堅 硬的材料層(例如絕緣氧化物材料);以及(i i i)在高於進行 離子轟擊溫度下熱處理矽晶片及絕緣材料之組件第三階段 。第二階段採用溫度足以黏接薄的矽薄膜及絕緣材料在一 起以在微小氣泡中產生壓力效果，以及促使石夕晶片其餘質 篁及薄的矽薄膜之間分離。（由於高溫步驟所導致，該處理 過程並不與低價格玻璃或玻璃陶兗基板相匹配）。 美國第2004/0229444號公告專利揭示出製造Si〇G結構 之處理過程。麵包含··⑴齡晶片表面暴露於氣離子植 入以產生黏接表面;（i i)將晶片黏接表面與玻璃基板接觸； 200818321 (i i i)對晶片及玻璃勤反施力口壓力，溫度以及電壓以促使黏 接至上面變為谷易，以及（iv)冷卻結構使玻璃基板以及石夕 薄層由矽晶片分離變為容易。 在外延後產生SOI結構呈現出過度表面粗糙度(例如10 nm或更大)，過度石夕層厚度(甚至於層視為”薄的”），不想要 氳離子，以及對矽晶體層產生植入損壞(例如由於形成非晶 吳石夕層所致）。由於SiOG材料一項主要優點在於薄膜單晶 特性，該晶格損壞必需加以回復以及加以去除。其次，在黏 接處理過程由於植入之氫離子並不完成地去除，以及由於 虱原子為導電活性的，其應該由表面去除以確保裝置穩定 操作。最後，分裂矽層之作用遺留下粗糙表面，其已知產生 不良的電晶體操作，目而在裝置製造出之前應該減小表面 粗糙度至小於lnra Ra。 這些問題應該分別地處理。例如，厚的(5〇〇nm)矽薄膜 初始地轉移至玻璃。頂部420nm藉由拋光去除以回復表面 修整以及消除石夕之頂部受損區域。殘餘石夕薄膜再在刪它 高溫爐中退火歷時小時以擴散出殘餘之氫。 人們已建議在薄的石夕薄膜由矽材料晶片外延出後使用 化學機械拋光(CMP)以更進一步處理s〇I結構。不過不利地 ，在抛光過程巾CMP處理過程無法在整個薄石夕雜表面均勻 地去除材料。一般表面不均勻（標準偏差/平均去除厚度） 為半導體薄膜3-5%範圍内。當更多矽薄膜厚度被去除，相 對地薄膜厚度變化變為較差。 ’ 上述CMP處理過程之缺點對於-麵在玻璃上應用將 200818321 成特別的問題，在一些情況夂高達300—4〇〇nm材料需要加 以去除以得到所需要石夕薄膜厚度。例如，在薄的薄膜電晶 體(TFT)製ϋ處獨針，賴麟度需制^⑽咖範圍内 。除此，TFT結構需要低的表面粗糙度。 CMP處理過程另外一項問題在於當長方形s〇I結構(例 如具有尖銳的角)被拋光時，其呈現出特別不良的結果。確 貝地，與soi結構中央比較，先前所提及在s〇I結構之角落處 不均勻將被放大|§。當考慮大的S〇i結構(例如作為光伏打 應用）時，所形成長方形S〇I結構對於一般Qjp裝置為太大（ 其通常設計作為30Gmra鮮晶片尺寸）。價格亦為观結構 商業化應用之重要考慮因素。不過，CMP處理過程費用與時 間及設備費用相關。假如需要非傳統CMp機器以配合大型 SOI結構尺寸，費用問題將顯著地擴大。 除此，可使用高溫爐退火(FA)以去除任何殘餘氫。不 過，南溫退火無法與低價格玻璃或玻璃陶瓷基板相匹配。 較低溫度退火(小於700。〇需要長時間以去除殘餘氮，以及 無法有效地修補由於植入導致之晶體受損。除此，CMp及高 溫爐退火增加費用以及降低製造產量。因而，在退火前需 要將氳部份地移除，使得退火步驟時間能夠減少。 因而，預期可能合併高溫爐退火以達到與CMp相匹配或 更佳之結果，但是沒有CMP以及高溫爐退火以及其相關之缺 點。 【發明内容】 依據本發明一項或多項實施例，形成半導體在絕緣體 200818321 上結構之系統，方法以及裝置包含將半導體在絕緣體上結 構至少，^個未修整表面施以輕射退火處理。依據—^項實施 例，輪射退火處理過程包含雷射退火處理過程。依m 明另一項實施例，輕射退火處理過程包含微波退火處理過 程。 依據本發明一項或多項實施例，形成半導體在絕緣體 上結構之系統，方法以及裝置包含:將晶質施體半導體晶片 之植入表面施以離子植入處理以在施體半導體晶片中產生 外延層;黏接外延層之植入表面至絕緣體基板;由施體半導 體晶片分離外延層，因而暴露出至少一個分裂表面；以及將 至少一個分裂表面施以輻射退火處理。 輻射退火處理加熱至少部份石夕層至接近或高過退火點 ’允許至少部份被捕獲氫氣釋出，以及當材料冷卻時使晶格 損壞恢復。除此，在初始表面中任何粗經度將由於高溫下 原子增加移動性或材料加熱至液態由於表面張力而導致減 小。因而，關於先前所提及CMP結合高溫爐退火(FA)之缺點 ’使用依據本發明之輪射退火例如藉由使用準分子雷射退 火(ELA)或微波退火，其有可能克服op之缺點以及減小氫 加熱去除所需要之退火時間。 至少一個分裂表面包含晶質施體半導體晶片之第一分 裂表面以及外延層之第二分裂表面。雷射退火處理適用於 外延層之第二分裂表面及/或施體半導體晶片之第一分裂 表面。 雷射退火處理包含將至少一個分裂施以準分子雷射。 第9 頁 200818321 例如，準分子雷射包含增益介質或確實受激二聚物，或激合 體例如為XeCl。能舰職他般介仅雷概輻射光源 某種程度_僻分子，轉娜絲顿射產生充 份功率以產生所需要之效果。優先地每一脈衝或每一照 射之輪射能量密度應該相當大足以溶融部份半導體層，但 是不應該完全地溶融半導體層。依據本發明處理過程之特 定實施例，處理之表面首先施以第一雷射輻射，接著施以第 二雷射輻射，其具有較低密度而低於第一雷射輻射。 選擇輻射波長而能夠部份炫融半導體層。不過，要求 結晶底部並不熔融。因而光線進入半導體材料之穿透深度 ，與半導體層厚度比較，不應太大。如底下參考範例數據說 明，當結晶矽半導體層厚度約為5〇〇nm時，以波長約為3〇8nm (XeCl雷射)下高於800mJ/平方公分底限之每一脈衝能量密 度促使可觀察到表面粗糙度結晶品質之改善。半導體組成 份及厚度之每一組合預期具有其本身之能量低限，在該低 P艮下將達成所需要之效果。因而，使用越薄之石夕半導體層 將減小能量低限至低於800mJ/平方公分，同時保持其他參 數為固定的。 輻射及雷射業界熟知此技術者能夠選擇輻射光源以及 雷射在半導體材料中具有適當的穿透深度以及符合最低能 量低限，同時在相當低功率值下操作雷射以防止破壞或完 全地熔融半導體層。同樣地，可想像可能使用不同增益介 質多個並聯或串聯輻射光源或雷射以達成所需要之結果。 人們了解施體半導體晶片可包含單晶施體半導體晶片 第1〇 頁 200818321 之部份結構以及可附加上地包含外延半導體層沉積於施體 半導體晶片上。外延層(例如黏接至絕緣體驗之層以及 由施體半導體曰曰曰結構分離)因而可由單晶施體半導 材料形成。可加以變化，外延層可實質上由外延半^声 形成(以及其亦包含部份單晶施體半導體晶片材料）。曰 先前所提及雷射退火處理可適用於外延層，不論其是 否由單晶石夕施體半導體晶片材料或由外延半導體層开》成。 在一項或多項實施例中，黏接步驟包含:加熱至少一個 絕緣體基板以及施體半導體晶片；促使絕緣體基板直接或 間接地接觸施體半導體晶片之外延層；以及施力口電壓於絕 緣體基板與施體半導體晶片兩端以產生黏接。絕緣體基板 以及施體半導體晶片之溫度可提高至絕緣體基板應變點之 150°C内。絕緣體基板及施體半導體晶片之溫度可提高至 不同的數值。絕緣體基板與施體半導體晶片兩端之電壓約 為100至10000伏特。產生應力，使得在外延層處發生破裂 。加熱以及離子缺陷相與外圍之晶片之不同的熱膨脹係數 促使外延層在氳缺陷相處分裂。結果為矽薄膜黏接至絕緣 在閱讀詳細技術說明以及現存SiOG處理步驟後將最佳 地了解本發明優點。儘管如此，本發明一項或多項實施例 包含:較薄的矽薄膜之轉移;具有較高結晶品質更均勻之石夕 薄膜;較快速製造產量;改良製造產量;減少污染；以及容易 擴充至大的基板。 可加以變化，厚的矽薄膜被轉移至絕緣體基板，以及再 第11頁 200818321 抛光以去除損壞之表面。對於非常薄的薄膜，該處理 之控制為®難的。祕在本發喊理触巾並無材^ ^ 除，薄的矽薄膜能夠直接地加以轉移。 ’1 均勻薄膜為需要的。再次地由於在處理過程中並無 材料被去除，矽薄膜厚度均勻度藉由離子植入決定出X…、 已顯示出為十分均勻的，其標準偏差約為lnm。加以比車^ 拋光通常產生薄膜厚度偏差約為去除數量之5%。 又， 改良製造產量亦對浪費以及費用減少亦為重要的。藉 由-個步驟替代兩種處理過程步驟，整體製造產量預期= 善。假如該拋光處理過程具有低產量步驟如預期情況，該 情況為翻地真實的。雖然非晶質石夕薄膜之準分子雷射奸 晶已知為具有低產量，在該特別情況中相反情況為真實的， 其由於石夕單晶石夕特性所致。處理窗預期為大的，目為薄膜 結晶特性，以及因而產量預期為高的。 、 、由於半導體靈敏性特性，污染會負面地影響性能，因而 減少污染為高度地需要的。雷射處理比利用研磨泥聚抛光 為乾淨的。除此，與較長熱退火處理過程比較，在快速雷射 脈衝過程中污染擴散將減小。當製造電子裝置時，此為重 要的考慮因素。 處理過程容易地擴大至大面積。目前顯示器製造商將 準分子雷射退火施用於尺寸高達73〇mmx92〇fflm(第四代)基 板。由於基板在雷射光束下掃瞄，基板尺寸能夠容易地增 加。當客戶基板尺寸規格增加時，此擴充性可能延伸產品 哥命。加以比較，對於較大基板尺寸，表面拋光以及高溫爐 第12 頁 200818321 退火將增加困難度。 熟知此技術者參考本發_圖及在此詳細綱將清楚 地了解本發明其他項目，特性，優點。 【實施方式】 除非另有說明，在說明書及申請專利範圍巾所使用特 似力份之重討分比所有以大 約^的數目賴加轉化。人們了解在綱#及申請專 利乾圍中所使職確之數目形成本發日月附加之實施例。已 作嘗試以確保範例巾所揭示數目續確性。任何量測之數 值能夠本質性地含有特定誤差，其由於在各別針报術中 所產生之標準偏差。 所謂’’晶質半導體材料”係指材料為完全結晶或實質上 結晶的，亥|應也或非刻魏或意外地加入缺陷及/或摻雜劑 在其中。目而其&含⑴财絲材料，半導體或非半導體 等以幵v成具有半導特性墙料，以及⑹藉由例如摻雜前 ，物材料形半賴之材料。晶質轉珊料可為單 f曰或多晶材料。確實地，半導性材料通常含有至少一些内 2或表面缺陷或麻地加上例如晶躲陷細粒邊界。所 明實貝上結晶’’亦反應出特定摻雜劑會扭曲或影響半導體 材料之晶體結構。 一參考附圖，其中相同的參考數字代表相同的元件，圖工 顯不出依據本發明一項或多項實施例之s〇I結構1〇〇。關於 、固’ SOI、纟。構1〇〇可以SiOQ為範例。siQQ結構可包含坡 璃基板102,以及半導體層1〇4。Si0G結構100可使用於製造 第13 頁 200818321 薄膜電晶體OFT)作轴示朗，桃含彳體 (0LED)顯示器以及液晶顯示器⑽)，積體線路，光伏打裝 置等。 作為說明用途，假設半導體層104由石夕所構成。不過人 們了解半導體潘可為料主之半導體雜何其他形式之 半導體，例如為IIM，III-IV等種類之半導體。這些材料 之範例包含:Si，SiGe，SiC, Ge，GaAs，GaP，及 InP。 玻璃基板102可由氧化物玻璃或氧化物玻璃陶瓷形成 。雖然並不要求，在此所說明實施例可包含氧化物玻璃或 玻璃陶兗，其應變點呈現出小於l〇〇〇°C。如傳統玻璃製造 業界，應變點溫度為玻璃或玻璃陶竟黏滯係數為1014>6泊 (10 Pa· S)之溫度。由於在氧化物玻璃或氧化物玻璃陶 竟之間，玻璃具有較為簡單製造之優點，因而使得玻璃更廣 泛地利用以及較為便宜。 例如，玻璃基板102可由含有鹼土金屬離子之玻璃& 形成，例如為由本公司玻璃編號1737及Eagle 2000形成之 基板。這些玻璃材料具有其他用途，特別是例如製造液晶 顯示器。 玻璃基板厚度在0· 1mm至10刪範圍内，例如在〇· 5咖至3 咖範圍内。對於一些SOI結構，厚度大於或等於丄微米(例如 為〇· 001mm或lOOOnm)之絕緣層為需要的以防止寄生電容效 應，當具有Si/Si(VSi構造之標準SOI結構在高頻率下操作 時將產生該效應。過去難以達成該厚度。依據本發明，具 有絕緣層厚度大於1微米之SOI結構可單純地使用厚度大於 第14 頁 200818321 或專於1微米之玻璃基板102立即地達成。破璃基板i〇2厚 度之下限約為1被米，即lOOOnm。儘管如此，為了得到最終 結構為高機械強度，基板厚度需要大於1〇微米。在特定實 施例中，要求玻璃基板厚度為大於30微米(基於例如商業用 途）。 通常，玻璃基板102厚度應該在整個黏接處理步驟中以 及在SiOG結構100進行後續處理過程中足以支撐半導體層 104。雖然玻璃基板102厚度並無理論之上限，超越支撐功 能需求之厚度或最終SiOG結構1〇〇所需要厚度並非有益的 因為玻璃基板102厚度越大，越難以在形成Si〇G結構1〇〇中 完成至少一些處理步驟。 氧化物玻璃或氧化物玻璃陶瓷1〇2可為石夕石為主的。 因而，在氧化物玻璃或氧化物玻璃陶瓷中Si〇2莫耳百分比 可大於30%莫耳比以及可大於權莫耳比。在玻璃陶兗情況 中，晶相能夠為莫來石，堇青石，鈣長石，尖晶石或其他業界 熟知之玻璃陶瓷晶相。非矽石為主之玻璃或玻璃陶兗可使 用於實施本發明一項或多項實施例，但是通常為較不有益 的，因為其較高價格及/或不良性能特性。 同樣的，對於一些應用例如採用非石夕石為主之半導體 材料的SOI結構，需要非氧化物為主例如非氧化物玻璃之玻 璃基板，但是通常並非有益的，因為其價格較高。如底下更 詳細说明，在一項或多項實施例中，玻璃或玻璃陶瓷基板1〇2 設計成與一種或多種半導體材料(例如Si，Ge等)層1〇4之熱 膨脹係數相匹配，該層直接地或間接地黏接至基板。熱膨 第15頁 200818321 脹係數相匹配確保在沉積處理加熱循環過程中所需要之機 械特性。 對於特定應用，例如顯示器應用或太陽能電池應用，玻 璃或玻璃陶究1〇2在可見光，近紫外線，及/或紅外線波長範 圍内為透明的，例如玻璃或玻璃陶兗1〇2在35〇nm至2微米波 長範圍内為透明的。 雖然玻璃絲1G2可由單-綱或玻璃喊層所構成， 假如需要情況下可使用疊層結構。當使用疊層結構時，最 接近半導體層1G4之疊層具有在此所賴由單—玻璃或玻 璃陶瓷所構成玻璃基板丨〇2之特性。遠離半導體層1〇4之層 亦具有這些特性，但是可具有較為緩和特性，因為其並不直 接地與半導體層1G4減個。在後者情況巾，當玻璃施 1〇2不再滿足玻璃基板102特定特性時，玻璃基板1〇2視為無 法再使用。 參考圖2-6。圖2顯示出進行處理步驟以製造出圖i之 SiOG結構1〇〇(及/或在此所揭示之其他實施例)，同時圖3—6 可實_ 2處理過程形成。在圖3中，箭 頭表不離子流(例如氫離子)以及當植入時之一般方向。在 圖2中，參考數字具有下列意義： 202:處理施體半導體晶片之表面； 204 ·將把體半導體晶片施以離子植入處理過程； 206 ··將施體半導體晶片施以中度氧化； 208:形成陽極黏接於外延層與玻璃之間； 210:由施體半導體晶片分離玻璃層/外延層；以及 第16 頁 200818321 2i2:將施體半導體晶片或外延層施以雷射退火處理。 首先參考圖2及3,在步驟中，施體半導體晶片12〇之 植入表φ 121藉由拋光，清理等方式處理以產生 及均勻植入表面121而適合作為黏接至玻璃或玻璃陶絲 板。植入處_® 121將形成半導體層1〇4之底侧。作為說 明目的，半導體晶片120可為單晶石夕晶片，然而可採用上述Π 所說明任何適當之半導體材料。 在步驟204中，外骑122藉由將植入表面121施以一種 或多種離子植入處理過程以產生弱化區域於施體半導體晶 片120级入表面121底下。雖然本發日月實施例並不受^ == 彡办_ 122 —種物方法要她、 -曰曰片120讀入表面121施以氫離子植入處理過程以 至少啟始形成外_ 122於施體半導體晶片12〇中。 植入能量使用傳統技術加以調整以達成適當厚度之外 延層122。例如，可採用氫離子植入，雖然可採用其他離子 =種離子’例如戰氦+氫，或其他外延讀中已知 、子。任何其他已知的或在此發展適合形成外_122 2技術可加以採用而並不會脫離本發明續神及範二例 子ί使Z束離Γ植入，電漿浸潰離子植入(ριπ)以及離 冷’匕3使用單-離子種類或多種離子種類。 在說明於底下範例數據區段之言礙中，外延層122严声 f 00測，但是由於異於去除情況之雷射退火再分配質量子又 1=可形成如所需要及/或可實施為薄的。除此，假 汗1 D SOI之半導體層需要雷射退火(例如比所需要厚)，在 第17頁 200818321 雷射退火修整表面之前，去除離子可使用已知的方法例如 CMP或拋光以減小層之厚度。不過使用質量去除步驟將使 整體製造處理過程之時間及費用增加。 在步驟206中，施體半導體晶片120可加以處理以減少 植入表面121i上之氫離子濃度。例如，施體半導體晶片 可進行洗滌以及清理，以及外延層122之離子植入表面121 施以中度氧化。中度氧化處理可包含在氧電漿中處理，臭 氧處理，利用過氧化氩，過氧化氳與氨，過氧化氯與酸處理 或這些處理過程之組合。預期在這些處理過程中，終端氫 表面基氧化為氫氧基，其因而亦使石夕晶片表面為親水性。 氧電漿可在室溫下進行處理以及氨或酸處理可在25—150 〇C溫度下進行處理。 參考圖2及4,在步驟208中玻璃基板1〇2可黏接至外延 層122。適當的黏接處理過程已說明於美國第2_/〇22944 4號公告專利中，該專利之說明在此加入作為參考。部份該 處理過程已知為陽極黏接，其將說明愉底下。在陽極黏接 處理過程中，可進行玻璃基板102(以及外延層122，假如尚 未完成)適當的表面清理。因而中間結構可促使直接或間 接接觸以達成如圖4示意性所顯示之排列。 在接觸之前或之後，由施體半導體晶片12〇，外延層122 ’ 102所構成之結齡不同溫度梯度下加熱。 玻璃紐102可加熱至較高溫度而高於施體半導體晶片12〇 以及外骑122。例如，玻璃紐102與施體半導體晶片120 (以及外延層122)㈤福度紐至傾1°C，賴差值可高 第頁 200818321 達10(TC至150°C。溫度差值對於熱膨脹係數與施體半導體 晶片120相匹配(與矽熱膨脹係數相匹配)之玻璃為需要的， 因為其將使後續之外延層122由半導體晶片120分離變為容 易，其由於熱應力所導致。玻璃基板102及施體半導體晶片 120溫度可在玻璃&反1〇2應變點150°C内。 一旦玻璃基板102與施體半導體晶片120間之溫度差值 為穩定的，施加機械應力於中間組件。其壓力在1至5〇psi 範圍内。施加較高壓力例如壓力高於l〇〇psi會導致玻璃基 板102破裂。 其次，電壓施力口於中間組件兩端例如施體半導體晶片 120為正極以及玻璃基板1〇2為負極。施加電壓促使玻璃基 板102中驗金屬或鹼土金屬離子由半導體/玻璃界面移動離 開而更進一步進入玻璃基板102。此完成兩種功能:⑴產 生無鹼金屬或鹼土金屬離子之界面；以及(i i i)玻璃基板 101變為非常反應性以及強固地黏接至施體半導體晶片12〇 之外延層122。 參考圖2及，在步驟21〇中，在中間組件保持在上述條件 下一段時間後(例如大約1小時或更少)，移除電壓以及使中 間組件冷卻至室溫。而後分離施體半導體晶片12〇與玻璃 基板102,假如尚未變為完全獨立，其可包含一些剝離以得 到玻璃基板102具有相當薄的外延層丨22,其由黏接至其上 ⑽辭導體材料碱。雜可藉由熱 m力122之分裂喊成。可加以變化或附加 上使用機械應力，例如雜或化學侧使分離變為容易。 第19 頁 200818321 ^圖5所示’分離後所形成結構包含玻璃魏脱及黏 处至，、上面之半導體材料外延層122。在外延作用後，观 :構之刀4表面123呈現出過度表面_造度(顯示於圖5中） ’過度的矽層厚度，以及矽層之植入損壞122A(例如由於氫 離子導致以及形成非晶質石夕層）。不過，如在圖中確認， 當使用雷射退火時，夕卜延層122可由開始製造出為非常薄， 因為受損满聰並不滅絲，關帛餘退火處理加 以修補。 作為說明用途，假設半導體層1〇4之最終厚度應該低於 1祕米（即lOOOnm)，例如小於2〇〇恤，例如即卿或更小。因而 ，產生具有所需要厚度適當薄的外延層122。過去，非晶質 矽層厚度約為5(H5Gnm，以及蚁纖人能量以及植入時 間，外延層122厚度約為300-500nm。不過，利用雷射退火， 可產生較薄的外延層122,其具有非晶質石夕層必需為相當薄 的。 因而，參考圖2,步驟212及圖6,分裂表面123施以後級 處理，其包含將分裂表面123施以雷射退火處理。大塊石夕之 試驗已顯示出雷射退火處理能夠加熱石夕表面高於其熔融溫 度(1685K)歷時數十奈秒。在SiOG情況中，假如尖峰溫度超 過1685K，以及假如在薄膜中存在未溶融晶種，薄膜由於冷 卻將結晶，以及預期為接近完美之晶體。在照射後，先前受 損矽表面呈現出非常少之缺陷而少於大塊石夕晶片中缺陷。 額外的雷射退火亦能夠使多晶薄膜以及大塊石夕表面光滑。 參考圖6,雷射退火處理可使用準分子雷射150進行，其 第20 頁 200818321 利用輻射155照射分裂表面123。如圖6所顯示，在分裂表面 123上可看見許多大的不規則122B。雷射退火處理(以及因 而材料124再分配以及表面粗糙度變為光滑)藉由一種或多 種雷射組成份，雷射波長，輻射功率，照射時間，及照射脈衝 數目加以控制。當材料124所需要數量被再分配後，產生退 火表面123A，終止雷射退火處理。與圖6不細彳122B比較， 少數，相當少不規則122C可在退火表面;[23A上看到，其顯示 於圖7中。 雖然該說明係指輻射光源為雷射，因為其為優先實施 例，輻射光源並不需要為雷射。具有類似雷射效應之輕射 光源將滿足需要。作為目前驗，輻射絲某種程度具有 類似雷射效果，其符合三種規格:1)彳既如其具有適當的（高） 月匕里禮度，2 )假如其能夠控制進入半導體材料之輻射穿透 深度;以及3)其能夠控制照射期間(例如藉由使用脈衝光源 )°特別地與雷射對比，輻射光源並不需要為同調的。決定 於設計及材料參數，可贼娜絲例如丨微 發射出微波輕射。 ’ 任何雷射或一般輻射光源可使用於本發明中，某種程 度輻射光源能夠組構為將半導體層1〇4退火，其主要地決定 於SOI結構100參數例如材料，厚度等。關於此方面，不但關 於輕射光源，㈤時關於娜方法選擇續造變化有許多例 如脈衝透射與連續波(CW)透射，及掃目苗照射與充份照射。 一般所謂雷射係指輻射受激發射之光線放大。雷射亦 表不經由魏發紐生嚷絲。雷概、騎常包含三個 200818321 在許，，式之雷射。_常由已知為雷 、、厂之增贫介質種類表示，。增益介質能夠為氣體，蒸汽 ，液體固體或半導體。 氬及氦-氖之氣體魏為最觀魏主射見光紅色 ^細内之輕射線。另—範例為瓜雷射，其發射紅外線 能量以及使用作為切割堅硬材料。 蒸汽雷射為汽化金屬作為增益介質。受激通常經由電 子電荷例如_崎祕金觀雜奴。在He-Cd，He-200818321 IX. INSTRUCTIONS OF THE INVENTION: TECHNICAL FIELD OF THE INVENTION The present invention relates to systems, methods, and products for fabricating semiconductor-on-insulator (SOI) structures using improved processing processes, including radiation annealing, and particularly Ray The shot annealing is performed as a trimming semiconductor layer. [The previous four targets] θ Up to now, the semiconductor material most commonly used in semiconductor-on-insulator structures is Shi Xi. In the literature, this structure is called the on-insulator structure and is simply referred to as ''SOI'. SOI technology continues to become important for neon thin film transistors, solar cells, image sensors, and displays such as active array displays. The SOI structure consists of a thin layer of single crystal (usually 〇·〇5—〇·3 μm (50-300 nm)), but in some cases, the thickness can be as high as 2 μm (20000 nm) on the insulating material. It is easy to show that the following description relates to the structure of a semiconductor on a insulator (SOI). The description of this particular type of S0I structure will make the explanation of the invention easy and not intended and is considered to be a limitation of any aspect of the invention. SOI generally refers to the structure of a semiconductor on an insulator, including a non-limiting structure on the insulator. Similarly, it is simply referred to as Si〇Q. The general structure of the semiconductor is on the glass, including the unrestricted stone on the glass. Structure. The SiOG term is also intended to include semiconductors on glass ceramics, including non-limiting structures on glass ceramics. S0I for short includes Si〇G structure. Various methods for forming a soi structure include (1) epitaxially growing Si on a lattice-matched substrate; (2) bonding a single crystal germanium wafer to another germanium wafer, and growing an Si〇2 oxide layer on the germanium wafer, followed by Polishing or engraving the upper wafer down to 200818321 to eg 0. 05 to 〇 3 micron (50-30 层 monocrystalline 矽; and (3) ion implantation, its hat (eg Qiansi ion) chick, in oxygen ion The 々 々 财 财 形成 形成 形成 财 々 々 々 々 々 々 々 々 々 々 々 々 々 々 々 々 々 々 々 々 々 々 々 々 々 々 々 々 々 々 々 々 々 々 々 々 々 々 々 々 Another Si wafer. The previous two methods of epitaxial growth and wafer-to-wafer bonding have not produced structures with satisfactory cost and/or impurity strength and durability. The latter method involving ion implantation has been concerned, and Ion implantation has been considered to be fine, and it is usually less than 50% of the energy required for the implantation of the scorpion and the required amount of the dosage is less than two. The US Patent No. 5,374, 564 discloses A processing step using a heat treatment process Sakae crystallization _ 腾丝上. With a flat surface, the ceremonial wafer is subjected to the next step: (1) by implanting a layer of gaseous microbubbles implanted by ion bombardment of the surface of the wafer, which defines the lower area of the shixi wafer and constitutes a thin The upper side region of the tantalum film; (ii) the flat planar surface of the tantalum wafer contacts a hard material layer (such as an insulating oxide material); and (iii) the third stage of heat treatment of the tantalum wafer and the insulating material at a temperature higher than the ion bombardment temperature. The second stage uses a temperature sufficient to bond the thin tantalum film and the insulating material together to create a pressure effect in the microbubbles, and to separate the remaining tantalum film and the thin tantalum film (due to the high temperature step, The process is not matched to low-priced glass or glass ceramic substrates. U.S. Patent No. 2004/0229444 discloses a process for fabricating a Si〇G structure. The surface includes: (1) the surface of the wafer is exposed to the gas ion implantation to produce the bonding surface; (ii) the bonding surface of the wafer is in contact with the glass substrate; 200818321 (iii) the pressure on the wafer and the glass, the temperature and The voltage is changed to promote adhesion to the top, and (iv) the cooling structure makes it easy to separate the glass substrate and the thin layer from the tantalum wafer. The SOI structure produced after epitaxy exhibits excessive surface roughness (for example, 10 nm or more), excessive thickness of the layer (even as the layer is considered "thin"), does not want erbium ions, and produces plants for the yttrium crystal layer. Into the damage (for example due to the formation of amorphous Wu Shi Xi layer). Since one of the main advantages of SiOG materials is the properties of the thin film single crystal, the lattice damage must be recovered and removed. Secondly, since the implanted hydrogen ions are not completely removed during the bonding process, and since the germanium atoms are electrically active, they should be removed by the surface to ensure stable operation of the device. Finally, the effect of splitting the ruthenium layer leaves a rough surface that is known to produce poor transistor operation, and should reduce the surface roughness to less than lnra Ra before the device is fabricated. These issues should be dealt with separately. For example, a thick (5 〇〇 nm) ruthenium film is initially transferred to the glass. The top 420 nm is removed by polishing to restore the surface finish and eliminate the damaged area at the top of the stone. The residual stone film was annealed in a high temperature furnace for a period of time to diffuse residual hydrogen. It has been suggested to use chemical mechanical polishing (CMP) to further process the 〇I structure after the thin shier film is epitaxially grown from the ruthenium material wafer. Disadvantageously, however, the CMP process during the polishing process does not remove the material evenly throughout the surface of the spar. Generally, surface unevenness (standard deviation / average removal thickness) is in the range of 3-5% of the semiconductor film. When more ruthenium film thickness is removed, the film thickness change becomes relatively poor. The disadvantages of the above CMP process are particularly problematic for the application of the surface to the glass. In some cases, up to 300-4 nm material needs to be removed to obtain the desired thickness of the film. For example, in the thin film electro-optic (TFT) system, the single needle, Lai Lin degree needs to be manufactured within the range of (10) coffee. In addition to this, the TFT structure requires a low surface roughness. Another problem with the CMP process is that it exhibits particularly undesirable results when the rectangular structure (e.g., having sharp corners) is polished. Indeed, compared to the center of the soi structure, the previously mentioned unevenness at the corner of the s〇I structure will be magnified|§. When considering large S〇i structures (for example, as photovoltaic applications), the resulting rectangular S〇I structure is too large for a typical Qjp device (which is typically designed as a 30Gmra fresh wafer size). Price is also an important consideration for the commercial application of the structure. However, the cost of the CMP process is related to time and equipment costs. If non-traditional CMp machines are required to accommodate large SOI structural sizes, the cost issue will increase significantly. In addition, high temperature furnace annealing (FA) can be used to remove any residual hydrogen. However, South Temperature Annealing does not match low-priced glass or glass-ceramic substrates. Lower temperature annealing (less than 700. 〇 takes a long time to remove residual nitrogen, and can not effectively repair crystal damage caused by implantation. In addition, CMp and high temperature furnace annealing increase the cost and reduce the manufacturing yield. Therefore, in the annealing It is necessary to partially remove the germanium before, so that the annealing step time can be reduced. Thus, it is expected that the furnace annealing may be combined to achieve a better match with CMp, but there is no CMP and high temperature furnace annealing and its associated disadvantages. SUMMARY OF THE INVENTION In accordance with one or more embodiments of the present invention, a system, method and apparatus for forming a structure of a semiconductor on an insulator 200818321 includes subjecting a semiconductor to at least an unstructured surface to a light shot annealing treatment. In an embodiment, the laser annealing process comprises a laser annealing process. According to another embodiment, the light annealing process comprises a microwave annealing process. According to one or more embodiments of the invention, the semiconductor is formed in an insulator. The system, method and apparatus of the upper structure comprise: a crystalline donor semiconductor wafer Implanting the surface to perform an ion implantation process to create an epitaxial layer in the donor semiconductor wafer; bonding the implant surface of the epitaxial layer to the insulator substrate; separating the epitaxial layer from the donor semiconductor wafer, thereby exposing at least one split surface; And applying at least one splitting surface to a radiation annealing treatment. The radiation annealing treatment heats at least a portion of the layer to near or above the annealing point to allow at least a portion of the captured hydrogen to be released, and to recover the lattice damage when the material cools. In addition, any coarse longitude in the initial surface will decrease due to increased mobility of the atoms at high temperatures or heating of the material to a liquid state due to surface tension. Thus, regarding the shortcomings of the previously mentioned CMP combined high temperature furnace annealing (FA) With the use of the radiation annealing according to the invention, for example by using excimer laser annealing (ELA) or microwave annealing, it is possible to overcome the disadvantages of op and to reduce the annealing time required for hydrogen heating removal. At least one split surface contains crystal Applying a first split surface of the semiconductor wafer and a second split surface of the epitaxial layer. Laser annealing treatment is suitable for epitaxy a second splitting surface and/or a first splitting surface of the donor semiconductor wafer. The laser annealing process includes applying at least one split to the excimer laser. Page 9 200818321 For example, an excimer laser contains a gain medium or is indeed subject to The excimer, or the excimer, is, for example, XeCl. It can only be used to cover a certain degree of radiance, and the Nassian shot produces sufficient power to produce the desired effect. The pulse or energy intensity of each shot should be relatively large enough to melt a portion of the semiconductor layer, but should not completely melt the semiconductor layer. According to a particular embodiment of the process of the invention, the treated surface is first applied with a first laser radiation Then, a second laser radiation is applied which has a lower density and is lower than the first laser radiation. The radiation wavelength is selected to partially scatter the semiconductor layer. However, it is required that the crystal bottom does not melt. Therefore, the penetration depth of light into the semiconductor material should not be too large compared to the thickness of the semiconductor layer. As shown in the sample data below, when the thickness of the crystalline germanium semiconductor layer is about 5 〇〇 nm, the energy density per pulse is higher than the bottom limit of 800 mJ/cm 2 at a wavelength of about 3 〇 8 nm (XeCl laser). An improvement in surface roughness crystal quality was observed. Each combination of semiconductor composition and thickness is expected to have its own energy low limit at which the desired effect will be achieved. Thus, the thinner the Si-Ni Semiconductor layer will reduce the energy limit to less than 800 mJ/cm 2 while keeping the other parameters fixed. Those skilled in the radiation and laser industry are familiar with the ability of the radiation source to have a suitable penetration depth in the semiconductor material and to meet the minimum energy threshold while operating the laser at relatively low power values to prevent damage or complete melting. Semiconductor layer. Similarly, it is conceivable to use multiple gain sources or multiple parallel or series radiation sources or lasers to achieve the desired result. It is understood that the donor semiconductor wafer may comprise a portion of the structure of the single crystal donor semiconductor wafer, and may additionally comprise an epitaxial semiconductor layer deposited on the donor semiconductor wafer. The epitaxial layer (e.g., the layer bonded to the insulating experience and separated by the donor semiconductor germanium structure) can thus be formed from a single crystal donor semiconductor material. Alternatively, the epitaxial layer can be formed substantially by epitaxial habit (and it also includes a portion of the single crystal donor semiconductor wafer material).激光 The previously mentioned laser annealing treatment can be applied to an epitaxial layer, whether or not it is formed from a single crystal semiconductor wafer material or an epitaxial semiconductor layer. In one or more embodiments, the bonding step includes: heating at least one of the insulator substrate and the donor semiconductor wafer; causing the insulator substrate to directly or indirectly contact the extended layer of the donor semiconductor wafer; and applying a voltage to the insulator substrate and Both ends of the semiconductor wafer are applied to create a bond. The temperature of the insulator substrate and the donor semiconductor wafer can be increased to within 150 °C of the strain point of the insulator substrate. The temperature of the insulator substrate and the donor semiconductor wafer can be increased to different values. The voltage across the insulator substrate and the donor semiconductor wafer is about 100 to 10,000 volts. Stress is generated such that cracking occurs at the epitaxial layer. The difference in thermal expansion between the heating and the ion-defective phase and the peripheral wafer causes the epitaxial layer to split at the defect phase. The result is that the tantalum film is bonded to the insulation. The advantages of the present invention will be best understood after reading the detailed description and the existing SiOG processing steps. Nonetheless, one or more embodiments of the present invention comprise: transfer of a thinner tantalum film; a more uniform crystalline quality of the stone film; faster manufacturing yield; improved manufacturing yield; reduced contamination; The substrate. It can be varied, a thick tantalum film is transferred to the insulator substrate, and polished on page 11 200818321 to remove the damaged surface. For very thin films, the control of this process is difficult. The secret is that there is no material in the hair call. ^ ^ In addition, the thin film can be transferred directly. A '1 uniform film is needed. Again, since no material is removed during processing, the uniformity of the thickness of the tantalum film is determined to be very uniform by ion implantation, which has been shown to be very uniform with a standard deviation of about 1 nm. Polishing compared to the car usually results in a film thickness deviation of about 5% of the removed amount. Also, improving manufacturing output is also important for waste and cost reduction. By replacing the two process steps with one step, the overall manufacturing output is expected to be good. If the polishing process has a low yielding step as expected, the situation is true. Although the excimer laser spectroscopy of the amorphous stellite film is known to have a low yield, the opposite is true in this particular case, which is due to the celestial characteristics of the singular single crystal. The processing window is expected to be large, with the crystallization characteristics of the film, and thus the yield expected to be high. Due to the sensitivity characteristics of semiconductors, pollution can negatively affect performance, and thus reducing pollution is highly desirable. The laser treatment is cleaner than using a grinding mud. In addition, contamination diffusion will decrease during fast laser pulses as compared to longer thermal annealing processes. This is an important consideration when manufacturing electronic devices. The process is easily extended to a large area. Currently, display manufacturers apply excimer laser annealing to substrates up to 73〇mmx92〇fflm (fourth generation). Since the substrate is scanned under a laser beam, the substrate size can be easily increased. This expandability may extend the product's life when the customer's substrate size increases. To compare, for larger substrate sizes, surface finishes, and high temperature furnaces, the annealing will increase the difficulty. Those skilled in the art will be able to clearly understand other items, features, and advantages of the present invention with reference to the present invention. [Embodiment] Unless otherwise stated, the weights of the similarities used in the specification and the scope of the patent application are more than the total number of the weights. It is understood that the number of positions made in the scope of the application and the application of the patents constitutes an embodiment attached to the date of the issue. Attempts have been made to ensure the continuation of the number disclosed in the sample towel. Any measured value can inherently contain a specific error due to the standard deviation produced in the individual needles. By 'crystalline semiconductor material' is meant that the material is completely crystalline or substantially crystalline, and that defects and/or dopants are added to or indirectly. a wire material, a semiconductor or a non-semiconductor, etc., which has a semi-conductive material, and (6) a material which is shaped by a material, for example, before doping. The crystal transfer material may be a single f- or polycrystalline material. Indeed, semiconducting materials usually contain at least some inner 2 or surface defects or numbness plus, for example, crystal-clearing fine grain boundaries. The crystals on the shells also reflect the specific dopants that can distort or affect the semiconductor material. BRIEF DESCRIPTION OF THE DRAWINGS Referring to the drawings, wherein like reference numerals refer to the like elements, the drawings illustrate the structure of the 〇I structure according to one or more embodiments of the present invention.构 〇〇 〇〇 〇〇 。 si si si si si si si si si si si si si si si si si si si si si si si si si si si si si si si si si si si si si si si si si si si si si si si si si si si si si si 0LED) display and LCD display (10)), integrated circuit, photovoltaic device, etc. For illustrative purposes, it is assumed that the semiconductor layer 104 is composed of Shi Xi. However, it is known that semiconductors can be semiconductors of other types of semiconductors, such as IIM, III. Examples of semiconductors such as -IV, etc. Examples of such materials include: Si, SiGe, SiC, Ge, GaAs, GaP, and InP. The glass substrate 102 may be formed of an oxide glass or an oxide glass ceramic. Although not required, The illustrated embodiment may comprise an oxide glass or a glass ceramic pottery having a strain point exhibiting less than 10 ° C. As in the conventional glass manufacturing industry, the strain point temperature is glass or glass, and the viscosity coefficient is 1014 > 6 poise ( The temperature of 10 Pa·S). Because of the advantages of relatively simple manufacturing of glass between oxide glass or oxide glass, the glass is more widely used and cheaper. For example, the glass substrate 102 may contain alkaline earth metals. The ionic glass & is formed, for example, as a substrate formed by our company's glass number 1737 and Eagle 2000. These glass materials have other uses, particularly examples. Such as the manufacture of liquid crystal displays. The thickness of the glass substrate is in the range of 0·1mm to 10, for example, in the range of 〇·5 coffee to 3 咖. For some SOI structures, the thickness is greater than or equal to 丄 micron (for example, 〇· 001mm or lOOOnm) The insulating layer is needed to prevent parasitic capacitance effects, which will occur when there is Si/Si (the standard SOI structure of the VSi structure operates at high frequencies. It has been difficult to achieve this thickness in the past. According to the present invention, the thickness of the insulating layer is greater than A 1 micron SOI structure can be achieved immediately using a glass substrate 102 having a thickness greater than that of page 14 200818321 or exclusively for 1 micron. The lower limit of the thickness of the glass substrate i〇2 is about 1 meter, that is, 100om. Nevertheless, in order to obtain a final structure with high mechanical strength, the substrate thickness needs to be greater than 1 μm. In a particular embodiment, the glass substrate thickness is required to be greater than 30 microns (based on, for example, commercial use). Generally, the thickness of the glass substrate 102 should be sufficient to support the semiconductor layer 104 throughout the bonding process and during subsequent processing of the SiOG structure 100. Although there is no theoretical upper limit on the thickness of the glass substrate 102, it is not advantageous to exceed the thickness required for the support function or the thickness required for the final SiOG structure 1 because the greater the thickness of the glass substrate 102, the more difficult it is to form the Si〇G structure. Complete at least some processing steps. The oxide glass or oxide glass ceramic 1〇2 may be mainly Shishishi. Thus, the Si 〇 2 molar percentage in the oxide glass or oxide glass ceramic can be greater than 30% molar ratio and can be greater than the weight molar ratio. In the case of glass ceramics, the crystalline phase can be mullite, cordierite, anorthite, spinel or other well-known glass-ceramic phases. Non- vermiculite-based glass or glassware can be used to practice one or more embodiments of the invention, but is generally less beneficial because of its higher price and/or poor performance characteristics. Similarly, for some applications, such as SOI structures using non-stone-based semiconductor materials, non-oxide based glass substrates such as non-oxide glass are required, but are generally not beneficial because of their higher price. As explained in more detail below, in one or more embodiments, the glass or glass ceramic substrate 1〇2 is designed to match the coefficient of thermal expansion of the layer 1〇4 of one or more semiconductor materials (eg, Si, Ge, etc.), the layer Bonded directly or indirectly to the substrate. Thermal expansion Page 15 200818321 The expansion coefficient is matched to ensure the mechanical properties required during the deposition process heating cycle. For specific applications, such as display applications or solar cell applications, glass or glass ceramics are transparent in the visible, near-ultraviolet, and/or infrared wavelength range, such as glass or glass ceramics 1兖2 at 35〇nm Transparent to the 2 micron wavelength range. Although the glass filament 1G2 may be composed of a single-layer or glass layer, a laminated structure may be used if necessary. When a laminated structure is used, the laminate closest to the semiconductor layer 1G4 has the characteristics of a glass substrate 丨〇2 composed of a single glass or a glass ceramic. The layer away from the semiconductor layer 1〇4 also has these characteristics, but may have a more moderate property because it is not directly grounded with the semiconductor layer 1G4. In the latter case, when the glass application 1 2 no longer satisfies the specific characteristics of the glass substrate 102, the glass substrate 1〇2 is considered to be unusable. Refer to Figure 2-6. Figure 2 illustrates the processing steps to fabricate the SiOG structure of Figure i (and/or other embodiments disclosed herein) while the Figure 3-6 process can be formed. In Figure 3, the arrow shows no ion current (e.g., hydrogen ions) and the general direction when implanted. In FIG. 2, reference numerals have the following meanings: 202: processing the surface of the donor semiconductor wafer; 204) applying the bulk semiconductor wafer to the ion implantation process; 206 · applying the donor semiconductor wafer to moderate oxidation; 208: forming an anode bonded between the epitaxial layer and the glass; 210: separating the glass layer/epitaxial layer from the donor semiconductor wafer; and page 16 200818321 2i2: subjecting the donor semiconductor wafer or epitaxial layer to a laser annealing treatment. Referring first to Figures 2 and 3, in the step, the implanted wafer φ 121 of the donor semiconductor wafer 12 is processed by polishing, cleaning, etc. to produce and uniformly implant the surface 121 suitable for bonding to glass or glass ceramics. board. The implant _® 121 will form the bottom side of the semiconductor layer 1〇4. For purposes of illustration, the semiconductor wafer 120 can be a single crystal wafer, although any suitable semiconductor material as described above can be used. In step 204, the outer rider 122 produces a weakened region under the donor semiconductor wafer 120 level entry surface 121 by applying one or more ion implantation processes to the implant surface 121. Although the embodiment of the present invention is not subject to ^ == — 122 - the method of seeding, the slab 120 is read into the surface 121 and subjected to a hydrogen ion implantation process to at least initiate the formation of the outer The semiconductor wafer 12 is applied. The implant energy is adjusted using conventional techniques to achieve an appropriate thickness of the outer layer 122. For example, hydrogen ion implantation may be employed, although other ions = species ions such as trembling + hydrogen, or other epitaxial readings may be employed. Any other known or developed in this development is suitable for the formation of the external _122 2 technology can be used without departing from the present invention and the second example of the ί Z beam away from the Γ implant, plasma impregnation ion implantation (ριπ ) and use a single-ion species or multiple ion species from the cold '匕3. In the explanation of the underlying example data section, the epitaxial layer 122 is singularly measured, but since the laser annealing is different from the removal, the redistribution mass is again 1 = can be formed as needed and/or can be implemented as Thin. In addition, the semiconductor layer of the fake sweat 1 D SOI requires laser annealing (eg, thicker than necessary), and before the laser annealing of the surface is modified on page 17, 200818321, the ions can be removed using known methods such as CMP or polishing. The thickness of the layer. However, the use of quality removal steps will increase the time and expense of the overall manufacturing process. In step 206, the donor semiconductor wafer 120 can be processed to reduce the concentration of hydrogen ions on the implanted surface 121i. For example, the donor semiconductor wafer can be washed and cleaned, and the ion implantation surface 121 of the epitaxial layer 122 is moderately oxidized. The moderate oxidation treatment may be carried out in an oxygen plasma treatment, an ozone treatment, using argon peroxide, ruthenium peroxide and ammonia, chlorine peroxide and acid treatment or a combination of these treatments. It is expected that during these treatments, the terminal hydrogen surface group is oxidized to a hydroxyl group, which in turn also renders the surface of the stone wafer hydrophilic. The oxygen plasma can be treated at room temperature and the ammonia or acid treatment can be carried out at a temperature of 25-150 〇C. Referring to Figures 2 and 4, the glass substrate 1〇2 can be bonded to the epitaxial layer 122 in step 208. A suitable bonding process is described in U.S. Patent No. 2/22,944, the disclosure of which is incorporated herein by reference. Some of this process is known as anodic bonding, which will be explained. During the anodic bonding process, the appropriate surface cleaning of the glass substrate 102 (and the epitaxial layer 122, if not completed) can be performed. Thus the intermediate structure may promote direct or indirect contact to achieve an arrangement as schematically illustrated in Figure 4. Before or after the contact, the epitaxial layer 122' 102 is heated by the donor semiconductor wafer 12'''''''''''''''''' The glass core 102 can be heated to a higher temperature than the donor semiconductor wafer 12A and the outer rider 122. For example, the glass germane 102 and the donor semiconductor wafer 120 (and the epitaxial layer 122) (five) 福度纽至1°C, the difference can be as high as page 200818321 up to 10 (TC to 150 ° C. Temperature difference for thermal expansion coefficient A glass that matches the donor semiconductor wafer 120 (matching the thermal expansion coefficient) is desirable because it will facilitate subsequent separation of the subsequent extended layer 122 from the semiconductor wafer 120, which is caused by thermal stress. The glass substrate 102 And the temperature of the donor semiconductor wafer 120 can be within 150 ° C of the glass & 1 〇 2 strain point. Once the temperature difference between the glass substrate 102 and the donor semiconductor wafer 120 is stable, mechanical stress is applied to the intermediate component. The pressure is in the range of 1 to 5 psi. Applying a higher pressure, for example, a pressure higher than 10 psi, causes the glass substrate 102 to rupture. Second, the voltage application port is applied to both ends of the intermediate member, for example, the donor semiconductor wafer 120 is a positive electrode and a glass. The substrate 1〇2 is a negative electrode. The application of a voltage causes the metal or alkaline earth metal ions in the glass substrate 102 to move away from the semiconductor/glass interface and further into the glass substrate 102. This accomplishes two functions: (1) producing an interface of alkali-free metal or alkaline earth metal ions; and (iii) the glass substrate 101 becomes very reactive and strongly adheres to the extension layer 122 of the donor semiconductor wafer 12〇. Referring to FIG. 2 and in step 21〇 After the intermediate component is maintained under the above conditions for a period of time (for example, about 1 hour or less), the voltage is removed and the intermediate component is cooled to room temperature. Then, the donor semiconductor wafer 12 and the glass substrate 102 are separated, if not yet. It becomes completely self-contained, which may include some peeling to obtain a relatively thin epitaxial layer 22 of glass substrate 102, which is adhered thereto by (10) a conductor material base. The impurities may be shouted by the splitting of the thermal m force 122. The mechanical stress can be changed or additionally used, for example, the impurity or the chemical side makes the separation easy. Page 19 200818321 ^ Figure 5 shows that the structure formed after separation contains the glass Weitre and the adhesion to the semiconductor material above. Epitaxial layer 122. After epitaxy, the surface 123 of the knives 4 exhibits excessive surface build-up (shown in Figure 5) 'excessive ruthenium thickness, and implant damage 122A of the ruthenium layer (eg The hydrogen ions cause and form an amorphous layer. However, as confirmed in the figure, when laser annealing is used, the delamination layer 122 can be manufactured to be very thin at the beginning, because the damage is not extinguished. For the purpose of illustration, it is assumed that the final thickness of the semiconductor layer 1〇4 should be less than 1 mil (ie, 100om), for example, less than 2 〇〇, such as qing or smaller. The epitaxial layer 122 having a suitably thin thickness is required. In the past, the thickness of the amorphous germanium layer was about 5 (H5Gnm, and the energy of the artificial fiber and the implantation time, and the thickness of the epitaxial layer 122 was about 300-500 nm. However, with laser annealing, a thinner epitaxial layer 122 can be produced which must have a relatively thin amorphous layer. Thus, referring to Fig. 2, step 212 and Fig. 6, the splitting surface 123 is subjected to a subsequent processing which involves subjecting the splitting surface 123 to a laser annealing treatment. The large-scale Shi Xi test has shown that the laser annealing treatment can heat the surface of Shishi over its melting temperature (1685K) for several tens of nanoseconds. In the case of SiOG, if the peak temperature exceeds 1685K, and if unmelted seed crystals are present in the film, the film will crystallize due to cooling and is expected to be a near perfect crystal. After irradiation, the previously damaged surface exhibits very few defects and is less than defects in the large stone wafer. Additional laser annealing also smoothes the polycrystalline film and the large stone surface. Referring to Figure 6, the laser annealing process can be performed using an excimer laser 150, which is irradiated with radiation 155 to illuminate the split surface 123. As shown in Figure 6, a number of large irregularities 122B are visible on the split surface 123. Laser annealing (and thus material 124 redistribution and surface roughness becomes smooth) is controlled by one or more laser components, laser wavelength, radiant power, illumination time, and number of illumination pulses. After the required amount of material 124 is redistributed, an annealing surface 123A is created to terminate the laser annealing process. A few, relatively few irregularities 122C can be on the annealed surface as compared to Figure 6 without detail 122B; see [23A, which is shown in Figure 7. Although the description refers to the radiation source being a laser, as it is a preferred embodiment, the radiation source does not need to be a laser. A light source with a similar laser effect will suffice. As a current test, the radiating wire has a similar laser effect to some extent, which meets three specifications: 1) 彳 as it has the appropriate (high) moon ,, 2) if it can control the penetration of radiation into the semiconductor material Depth; and 3) it is capable of controlling the illumination period (for example by using a pulsed light source). In particular, in contrast to the laser, the radiation source does not need to be homogenous. Depending on the design and material parameters, the thief, such as the 丨 micro, emits a microwave light shot. Any laser or general radiation source can be used in the present invention, and a certain degree of radiation source can be configured to anneal the semiconductor layer 1-4, which is primarily determined by SOI structure 100 parameters such as material, thickness, and the like. In this respect, not only the light source is used, but also there are many variations on the selection of the Na method, such as pulse transmission and continuous wave (CW) transmission, and sweeping and full irradiation. Generally speaking, laser refers to the amplification of light that is stimulated by radiation. The laser also does not pass through the Weifa Newborn silk. Lei, riding often contains three 200818321 in Xu, the type of laser. _ is often expressed by the types of lean media known as mines and factories. The gain medium can be a gas, a vapor, a liquid solid or a semiconductor. The gas of argon and helium-tellurium is the most important of the Wei main radiation. Another example is the melon laser, which emits infrared energy and is used as a hard material for cutting. The vapor laser is a vaporized metal as a gain medium. Excitation is usually via an electronic charge such as _Saki Miyuki. At He-Cd, He-
Se，及He-Hg情況中，汽化金屬可混合其域料例如氣氣作 為緩衝劑。 、，液體雷射包含染料雷射，其中增益介質為複合有機染 料，例如為羅丹紅(Rh〇damine) 6G，在液體溶液或懸浮液中 。藉由變化染料溶液及/或其特性，染料雷射可在寬廣波長 範圍内加以調整。 固fe增盈介質雷射亦稱為固態雷射以及具有雷射材料 分佈於固態基質内。範例包含紅寶石或Nd—YAG雷射，其發 射出1064nm紅外線。 半導體雷射使用二極體作為增益介質，其有時稱為二 極體雷射。半導體雷射通常使用低功率以及可為非常小， 其容易使用於各種電子產物例如雷射列印機以及③播放器 中。 化學雷射使用化學反應作用以達到連續性操作之高功 200818321 率激發。兩種範例包含氳氟雷射，其發射27〇〇〜29〇〇咖光線 ，以及氖氟雷射發射3800nm光線，其分別地使用氫或氛氣體 與三氟化氮中乙烯燃燒產物反應作用。 )八 次種類之氣體雷射，準分子雷射使用反應性氣體當受 到電子受激啦生擬好稱騎激二雜，亦已知為準P 子。準分子受激時將產生紫外線之光線。在化學中，二聚 物係指由兩個相似次單元或單體連接在一起所構成之分子 。確實準分子為由受激狀態相同的分子形成之二聚體，因 而激生分子(exciplex)為由受激狀態不同分子形成二聚體 之分子。激生分子通常被誤稱為準分子，在本發明中所謂 準分子包含激生分子。能夠使用氣體例如為氯及氟，當單 獨使用時形鮮分子，或當與惰性氣體例如氬，氪或氙混合 時形成激生分子。 在本發明不同的實施例中我們已使用之雷射輻射範例 包含XeCl雷射(308nm);KeF雷射(248nm);以及連續波氬氣In the case of Se, and He-Hg, the vaporized metal may be mixed with a domain material such as gas as a buffer. The liquid laser comprises a dye laser, wherein the gain medium is a composite organic dye, such as Rhoddamine 6G, in a liquid solution or suspension. Dye lasers can be adjusted over a wide range of wavelengths by varying the dye solution and/or its properties. The solid-increasing medium laser is also known as solid-state laser and has a laser material distributed in a solid matrix. Examples include ruby or Nd-YAG lasers that emit 1064 nm infrared. Semiconductor lasers use a diode as the gain medium, which is sometimes referred to as a diode laser. Semiconductor lasers typically use low power and can be very small, making them easy to use in a variety of electronic products such as laser printers and 3 players. Chemical lasers use chemical reactions to achieve high performance in continuous operation. Two examples include a krypton-fluoride laser that emits 27 〇〇 to 29 〇〇 of ray light, and a krypton-fluoride laser that emits 3800 nm of light, which respectively reacts with ethylene combustion products in nitrogen trifluoride using hydrogen or an atmosphere. Eight kinds of gas lasers, excimer lasers use reactive gases. When they are excited by electrons, they are also called quasi-P. When the excimer is excited, it will produce ultraviolet light. In chemistry, a dimer refers to a molecule composed of two similar subunits or monomers joined together. It is true that an excimer is a dimer formed by a molecule having the same excited state, and thus an exciplex is a molecule which forms a dimer from a molecule having a different excited state. The excimer is often mistakenly referred to as an excimer, and in the present invention, the excimer contains an excimer. Gases such as chlorine and fluorine can be used, which form a fresh molecule when used alone, or form an excited molecule when mixed with an inert gas such as argon, helium or neon. Examples of laser radiation that we have used in various embodiments of the invention include XeCl laser (308 nm); KeF laser (248 nm); and continuous wave argon
體雷射。雷射照射系統說明於例如於扎j. Kahlert，KBody laser. The laser irradiation system is described, for example, in J. Kahlert, K.
Simon,及 Β· Burghardt，Mat. Res· Sodymp· Ρπ^· ν〇1· 685E，paperD6.2 (2001)，其相關部份在此加入作 為參考之用。基於目前應用内容，該雷射系統能夠使用於 本發明中。 使用低及局頻率微波能夠達成微波照射。高頻率照射 (例如n〇GHz磁旋管光源)優先地能夠對矽薄膜作良好的電 磁輕合，但疋對玻璃為不良耦合。因而能夠達成超過l〇〇°C /秒加熱速率並最小地將熱量轉移至基板。操作中，磁旋管 第23 頁 200818321 光源發出能量經由波導耦合至特別設計之真空試樣槽。槽 具有至少一個不同的尺寸以調整微波共振模式。薄膜溫^ 由模圖案支配，因而相對於共振模圖案(例如磁旋管)移動 而更均勻加熱試樣將為需要的。 能夠使用不_綠術雷射絲峰露綠面。採 用雷射絲騎作為範例，考慮T列非限制性方式： -使用單一雷射光束照射要被處理之表面； -同時地連續性地或其他方式使用多個雷射以照射要被 處理之表面； -使用大面積光束藉由例如泛光暴露以照射表面； 一般光微影之逐步及重複處理過程可使用於照射中，· 月b夠使用線性狹窄光束以掃猫被處理之表面； -能夠使用小面積光束以掃瞄表面例如為向量掃瞄，循序 掃猫等； -使用脈衝雷射光束以及照射數量藉由控制脈衝總數量 加以控制; -使用連續性雷射光束以及控制照射時間以控制總照射 能量；以及 -藉由控制雷射光束相對於被照射表面之速度例如控制 放置基板之載台平移速度以控制照射時間。 與照射方式及雷射光源無關，在本發明一項或多項實 施例中，處理表面施以均勻的照射能量，使得表面退火至相 同的溫度。達到該方面，需要均勻的雷射光束。 使用光學系統以在半導體層表面上產生均勻的光束。 第24 頁 200818321 光學系統可包含均勻器。產生均勻雷射光束之光學系統可 由市場上取得。雷射光束之均勻性規格由處理窗支配，其 因而決定於半導體層厚度以及決定於受損層之厚度。 本發明其他實施例將針對先前所提及Si〇Q處理過程加 以說明以及更進一步詳細說明。例如，由施體半導體晶片 120分離外延層122結果將產生施體半導體晶片12〇之第一 分裂表面以及外延層122之第二分裂表面123。如先前所說 明，雷射退火處理過程可施加於外延層122之第二分裂表面 123。額外地或加以變化地，雷射退火處理可施加於施體半 導體晶片120之第一分裂表面(使用上述所說明之一種或多 種技術）。 在本發明另一實施例中，施體半導體晶片可為部份施 體結構，其包含單晶施體半導體晶片12〇，以及外延半導體 層位於施體半導體晶片上。在中外延成長半導體層之 詳細說明可參考本公司2〇〇5年6月23日申請之美國第n/i5 9889號專利，该專利之說明在此力0入作為參考。因而，外延 層122可由外延半導體層形成(以及亦可包含部份來自於晶 片120之單晶矽施體半導體材料）。因而先前所提及雷射退 火處理可適用於外延層之分裂表面，其由外延半導體材料 及/或外延半導體材料與單晶石夕半導體材料組合开^成。 在形成半導體在絕緣體上結構励系統中雷射退火處 理可自動化。圖8顯示出範例性形成步驟8〇2-8〇8。在該圖 中，參考數字具有下列意義： 802:調理非退火之半導體在絕緣體上結構； 第25 頁 200818321 804:運送及定位so!結構至雷射退火組件中; 806:進行雷射退火;以及 808:由雷射退火組件運送。 系統包含半導體在絕緣體上結顯作組件，其操作結 構100以進行處理，以及雷射退火組件。雷射退火組件包人 雷射以照射半導體在絕緣體上結構職其藉由半導體 緣體上操作組件進行操作。假如需要情況下，操作組件可 在照射之前清理結構以去除表面污染及/或 原始氧化層。雷概烟村在真封较蝴 作以控制污染。 呆 例如，在SOI結構1〇〇部份地調理(步驟8〇2)後，在 雷射退火例如分裂表面123以及雷射退纽件中，處理操^ 組件能夠運送及定位(步驟未修整表面沏結構⑽。 不但外延形成之分裂表面123受益於雷射退火同時由則 任何數目步驟之形成處理過程所形成之半導顯表面(复 晶體結構受損，不想要離子雜質，及/或表面祕度)特徵 未修整表面632需要雷射退火。 ’ 雷射退火组件將進行雷射退火(步驟806)，以及操物 件能夠由雷射駄組件運送(步驟_)具有雷射退火表面 例如為退火表面123A之SOI結構〗〇〇作更進一步操作 退火組件能夠程式化以調整以調整雷射退火處理過程之密田 度及脈衝數目而改變半導體層材料，厚度，製造經歷等。 、在依據本發_射退火處理過針，至少部份施以退 火之結晶層域絲ι 第26 頁 200818321 =irt Γ奸雜秋歧触，此將導致 較短的”、、从處理。如我們發現本發明輪Simon, and Β· Burghardt, Mat. Res. Sodymp· Ρπ^· ν〇1· 685E, paper D6.2 (2001), the relevant portions of which are hereby incorporated by reference. The laser system can be used in the present invention based on current application content. Microwave illumination can be achieved using low and local frequency microwaves. High frequency illumination (e.g., a n GHz magnetron source) preferentially provides good electromagnetic coupling to the tantalum film, but is poorly coupled to the glass. It is thus possible to achieve a heating rate in excess of 10 ° C / sec and to minimize heat transfer to the substrate. In operation, the magnetic coil Page 23 200818321 The source emits energy via a waveguide coupled to a specially designed vacuum sample cell. The slots have at least one different size to adjust the microwave resonant mode. The film temperature is governed by the pattern and thus it will be desirable to heat the sample more uniformly with respect to the movement of the resonant mode pattern (e.g., the magnetic coil). The green surface can be used without the _ green technique. Using a laser ride as an example, consider the T-column non-limiting way: - use a single laser beam to illuminate the surface to be treated; - simultaneously or continuously use multiple lasers to illuminate the surface to be treated - use a large area of light to expose the surface by, for example, floodlight exposure; general gradual and repeated processing of light lithography can be used for illumination, · month b enough to use a linear narrow beam to sweep the surface of the cat to be treated; Use a small area beam to scan the surface such as vector scan, sweep the cat, etc.; - use the pulsed laser beam and the amount of illumination is controlled by the total number of control pulses; - use continuous laser beam and control the illumination time to control Total illumination energy; and - controlling the illumination time by controlling the speed of the laser beam relative to the illuminated surface, for example, controlling the stage translation speed of the substrate. Regardless of the mode of illumination and the laser source, in one or more embodiments of the invention, the treated surface is subjected to uniform illumination energy such that the surface is annealed to the same temperature. To achieve this, a uniform laser beam is required. An optical system is used to create a uniform beam of light over the surface of the semiconductor layer. Page 24 200818321 The optical system can include a homogenizer. An optical system that produces a uniform laser beam is commercially available. The uniformity specification of the laser beam is governed by the processing window, which is thus determined by the thickness of the semiconductor layer and by the thickness of the damaged layer. Other embodiments of the invention will be described with respect to the previously mentioned Si〇Q process and described in further detail. For example, separating the epitaxial layer 122 from the donor semiconductor wafer 120 will result in a first split surface of the donor semiconductor wafer 12 and a second split surface 123 of the epitaxial layer 122. As previously stated, a laser annealing process can be applied to the second splitting surface 123 of the epitaxial layer 122. Additionally or alternatively, a laser annealing process can be applied to the first split surface of the donor semiconductor wafer 120 (using one or more of the techniques described above). In another embodiment of the invention, the donor semiconductor wafer can be a partial donor structure comprising a single crystal donor semiconductor wafer 12A and an epitaxial semiconductor layer on the donor semiconductor wafer. For a detailed description of the epitaxial growth of the semiconductor layer, reference is made to the U.S. Patent No. 5/9,9,889, filed on Jun. 23, 2005, the disclosure of which is hereby incorporated by reference. Thus, the epitaxial layer 122 can be formed of an epitaxial semiconductor layer (and can also include a portion of the single crystal germanium donor semiconductor material from the wafer 120). Thus, the previously mentioned laser annealing treatment can be applied to the splitting surface of the epitaxial layer, which is formed by combining an epitaxial semiconductor material and/or an epitaxial semiconductor material with a single crystal semiconductor material. The laser annealing process can be automated in forming a semiconductor-on-insulator structure. Figure 8 shows an exemplary formation step 8〇2-8〇8. In the figure, the reference numerals have the following meanings: 802: conditioning the non-annealed semiconductor on the insulator structure; page 25 200818321 804: transporting and positioning the so! structure into the laser annealing assembly; 806: performing laser annealing; 808: Transported by a laser annealing assembly. The system includes a semiconductor-on-insulator junction as an assembly that operates the structure 100 for processing, as well as a laser annealing assembly. The laser annealing assembly encloses a laser to illuminate the semiconductor on the insulator structure and operates on the semiconductor body operating component. If desired, the operating assembly can clean the structure to remove surface contamination and/or the original oxide layer prior to illumination. Lei Yanyan Village is in the real seal to control pollution. For example, after the SOI structure is partially conditioned (step 8〇2), in the laser annealing such as the split surface 123 and the laser blank, the processing component can be transported and positioned (step untrimmed surface) Brewing structure (10). Not only the epitaxially formed splitting surface 123 benefits from laser annealing while being formed by any number of steps forming the semiconducting surface (the complex crystal structure is damaged, unwanted ionic impurities, and/or surface secrets) The feature unfinished surface 632 requires laser annealing. The laser annealing assembly will perform laser annealing (step 806), and the workpiece can be transported by the laser beam assembly (step _) with a laser annealed surface such as an annealed surface The SOI structure of 123A is further manipulated. The annealing component can be programmed to adjust the semiconductor layer material, thickness, manufacturing experience, etc. according to the tightness and the number of pulses in the laser annealing process. The shot is annealed and the needle is at least partially applied to the annealed crystal layer. Page 18 200818321 =irt Γ 杂 秋 歧 歧 , , , , , , , , , , , , , , , , , , , , , , , , They found that the invention wheel
對回復表面缺陷十分有效，在該步驟整體過程中;;H 全部被捕獲離子植入種類釋出氣體。在這些實施例中在 輻射退火後需錢_卜.熱耿轉，射被捕赫 子植入種類會相當程度轉出氣體。甚至於在這些實施例 中，由於在輻射退火步驟過程中，與CMP表面提昇處理過程 作比較，整體退火所需要的時間將減少。 我們更進-步考慮在本發明輻射退火處理過程之前， 以及在照概火處獅針，獻雷射駄之結晶半導體 層加熱至高溫。在特定實施例中，該溫度範圍在100它至 Tsp-loo c之間，其中假如使用玻璃基板，Tsp為玻璃基板之 應變點，加熱綠使用晶質材料，Tsp為晶質級之溶點。 此通常將必需加熱整個SOI結構，或其大部份至該溫度範圍 。該晶質層預先加熱具有下列優點:⑴其在輻射退火步驟 過程中較小晶質轉體射存在溫度梯度，翻:減少破裂 可能;（i i)其在輻射退火步驟過程中能夠使更多離子植入 種類釋出氣體;（iii)假如需要情況下，其減少進行後續加 熱退火之時間；以及(iv)有可能同時地進行輕射退火及力口 熱退火。 本發明更進一步藉由下列非限制性範例加以說明。 範例： 進行一系列試驗，其顯示出施加先前所提及雷射退火 處理於SiOG結構上。具有5〇〇簡厚度矽外延層122之SiOG結 第27 頁 200818321 f露於.1250mJ/平方公分準分子雷射150輻射155歷 時1至100脈衝。所使用準分子雷射150為Lajnsik Physik出 產XeC1準分子雷射，其操作於高達100Hz具有28奈秒脈衝之 308nm光線。308nm波長紫外線㈣進入石夕深度為數奈米， 假如在碎絲上錄絲德餘_當地，其導致 石夕層之頂舰:融。使用於具有均自器光學系統之雷射產生 均勻的5mmx0· 8mm光束。在本發明範例中所使用逐步及重 複照射將照射大於光束尺寸之照射面積。類似的雷射能量 足以將非晶f轉聽晶，其導致乡驗。不過在目前情 況中，外延層122為只具有植入損壞122A之單晶薄膜，能夠 使單晶薄膜作為晶種晶體。在目前試驗中，高於8〇〇mJ/平 方公分低限之能量促使表面粗糙度得到改善。 底下表1說明不同密度及脈衝數目對表面粗糙度(臥以 nm表示)之改善。量測初始表面粗糙度為6.6nm臥(9.4fflm 廳)，同時在一個1250mJ/平方公分雷射脈衝後雷射退火表 面123A之粗糙度量測為低於1· 〇nm。同樣地，十個1麵mj/ 平方公分雷射脈衝後，雷射退火表面123A之粗糙度亦減小 為低於1· Onm。 表1 1250mJ/cm2 1000mJ/cm2 800m J/cm2 0脈衝 6.61 6.61 6.61 1脈衝 0.99 1.42 — 2脈衝 0.98 1.16 1.45 10脈衝 0.63 0. 74 1.29 第28 頁 200818321 同樣地，圖9,10及11顯示出改善情況以及表面粗链度 顯著地減小。圖9為使用先前所提及製造處理過程實施例 形成SiOG結構1GG之初始分裂表® 123的原子力顯微(細 影像。圖10為圖9中相同SiOG結構1〇〇經過十個1250mj/平 方公分雷射脈衝後之原子力顯微影像。將圖g影像與圖1〇 影像比較，其清楚地顯示出退火處理過程去除表面不細卜 利用相當高脈衝能量密度(1250mJ/平方公分)達成較 佳表面粗糙度之減小。不過，在這些高能量密度下，局部缺 陷例如裂縫會經由退火處理過程形成於石夕薄膜中，其由於 氫向外擴散所致。在一些情況下，在退火處理過程中持續 性地使用不_統聽續高能量密度絲有益的、。 如圖11A，11B，12A，及12B中更詳細顯示出，退火處理產 生相當光滑復原植入損壞122A之退火表面123A於&⑴結構 1〇〇之半導體層104上。圖11A及11B分別為退火之前及退火 之後所形成半紐;| 104之透射電預微鏡(TEM)的斷面影 像在圖11B情況中，退火處理過程包含功率為1〇個⑹此】/ 平方公分之脈衝。圖12A及12B分別顯示出退火之前及退火 之後所形成半導體層刚之掃瞒電子顯微鏡(簡)之平面影 像。在該範例中，退火進行為施加15個8〇〇mJ/cm2之脈衝接 著10個之1200mJ/平方公分脈衝。在圖11A及12A中，初始分 裂表面123之表面損壞122A為明顯的，其中退火表面12弘遠 比圖11B及12B中乾淨，以及顯示出較高品質之結晶。 在相同情況中，圖13顯示出由SiOG結構100之光學反射 數據，兩者為所形成之分裂表面，以及在1〇個1000mJ/平方 第29頁 200818321 公分之脈衝後退火表面123A。對於照射及無照射薄膜，在 右邊之干涉條紋160幾乎相等，其表示薄膜厚度並不受到雷 射照射而改變，該發現經由表面分佈量測加以確認。不過 對於波長小於400nm之退火表面123A絕對反射為超過分裂 表面123之情況。此增加反射為表面粗糙度減小之特性，如 同由AFM數據得到之結論，以及在薄膜表面處晶體缺陷將減 小。除此，照射試樣之數據與並未繪出純的單晶矽表面相 關數據一致。 亦對試樣進行電子量測以確認退火表面123A為接近單 晶結晶。這些量測更進一步顯示出在薄膜中不想要導電活 性氫原子數目減少。因而，雷射退火處理實質上藉由釋出 被捕獲之氫離子以及藉由回復半導體層1〇4至接近單晶狀 態而去除植入損壞，以及使其表面U3A光滑。 總之，本發明相信首先應用雷射退火於氫離子植入形 成之SOI基板。其提供獨特地解決同時地改善表面粗糙度 及矽之結晶。 雖然本發明已對特定實施例加以說明，人們了解這些 實施例只作為說明本發明之原理及應用。人們了解這些列 舉實施例能夠作許多變化及設計出其他排列而並不會脫離 下列申請專利範圍界定出之本發明之精神及範圍。 【圖式簡單說明】 為了列舉本發明各項，其中相同的數字代表相同的元 件，附圖顯示出優先簡化之形式，人們了解本發明並不會受 限於所顯示之精確排歹!〗及組合，而本發明只受限於戶斤提出 第30 頁 200818321 之申請專利範圍。 施例其顯示出依據本發明-項或多項實 採牛圖為流程圖，其顯示出進行製造第一圖則詰構處 理步驟之流程圖。 娜』處理 =七圖為核組圖，其顯示出在雷射退火後SOI結構。 八81H輒翻示it}轉體麵緣體上結構之 處理步驟。 第九圖為在雷射退火之前未修整範例性半導體層之原 子力顯微^影像。 第十圖為在雷射退火之後第九圖相同的半導體層之原 子力顯微影像。 …第十-圖A及第十-圖B為分別地顯示出退火之前及之 後範例性半導體層透射電子顯微(TEM)斷面影像。 苐十一圖A及第十一圖B為分別地顯示出退火之前及之 後範例性半導體層掃目苗電子顯微(SEM)平面影像。 第十三圖依據本發明預先雷射退火試樣之光學反射數 據與後級雷射退火試樣之光學反射數據的曲線圖。 附圖元件數字符號說明： 半導體在絕緣體上(SOI)結構100;玻璃基板102;半 &體層104;施體半導體晶片120;植入表面121;外延片 122;受損材料122A;不規則部份122B，123C;分裂表面 第31 頁 200818321 123;退火表面123A;材料124;雷射150;輻射155;處理 施體半導體晶片之表面202;將施體半導體晶片施以離子 植入處理204;將施體半導體晶片施以中度氧化2〇6;形成 陽極黏接於外延層與玻璃之間208;由施體半導體晶片分 離玻璃層/外延層210;將施體半導體晶片或外延層施以雷 射退火處理212;調理非退火之半導體在絕緣體上結構 802;運送及定位SOI結構至雷射退火組件中8〇4;進行雷射 退火806;由雷射退火組件運送SOI結構808。 第32 頁It is very effective for recovering surface defects. During the whole process of this step; H is completely released by the trapped ion implantation species. In these embodiments, after the radiation annealing, it is necessary to convert the heat to the gas, and the type of the implanted trap will transfer the gas to a considerable extent. Even in these embodiments, the time required for bulk annealing will be reduced as compared to the CMP surface lift process during the radiation annealing step. We further consider the heating of the crystalline semiconductor layer of the laser to the high temperature before the radiation annealing process of the present invention and the lion's needle in the fire. In a particular embodiment, the temperature range is between 100 and Tsp-loo c, wherein if a glass substrate is used, Tsp is the strain point of the glass substrate, heating green uses the crystalline material, and Tsp is the crystalline grade melting point. This will usually necessitate heating the entire SOI structure, or most of it to this temperature range. The pre-heating of the crystalline layer has the following advantages: (1) it has a temperature gradient in the smaller crystalline body during the radiation annealing step, and reduces the possibility of cracking; (ii) it can make more ions during the radiation annealing step. Implanting the species to release the gas; (iii) reducing the time for subsequent thermal annealing if necessary; and (iv) possibly performing both light-exposure annealing and forced-mouth thermal annealing. The invention is further illustrated by the following non-limiting examples. Example: A series of tests were performed which showed the application of the previously mentioned laser annealing treatment to the SiOG structure. SiOG junction with 5 〇〇 thickness 矽 epitaxial layer 122 Page 18 200818321 f Exposure to .1250 mJ/cm ^ 2 excimer laser 150 radiation 155 for 1 to 100 pulses. The excimer laser 150 used produced a XeC1 excimer laser for Lajnsik Physik, which operates at 308 nm with a 28 nanosecond pulse up to 100 Hz. 308nm wavelength ultraviolet (four) into the Shi Xi depth is a few nanometers, if the silk is recorded on the broken silk _ local, which leads to the top of the Shi Xi layer: melt. It is used in a laser with a homogenous optical system to produce a uniform 5mm x 0. 8mm beam. The stepwise and repeated illumination used in the examples of the present invention will illuminate an illuminated area greater than the beam size. A similar laser energy is sufficient to turn the amorphous f into a crystal, which leads to a home test. However, in the present case, the epitaxial layer 122 is a single crystal film having only implant damage 122A, and the single crystal film can be used as a seed crystal. In the current test, energy above the lower limit of 8 〇〇 mJ/square centimeter resulted in improved surface roughness. The bottom table 1 below illustrates the improvement in surface roughness (in nm) for different densities and pulse numbers. The initial surface roughness was measured to be 6.6 nm (9.4fflm chamber), and the roughness of the laser annealed surface 123A after a 1250 mJ/cm 2 laser pulse was measured to be less than 1·〇nm. Similarly, after ten one-sided mj/cm 2 laser pulses, the roughness of the laser annealed surface 123A is also reduced to less than 1·Onm. Table 1 1250mJ/cm2 1000mJ/cm2 800m J/cm2 0 pulse 6.61 6.61 6.61 1 pulse 0.99 1.42 — 2 pulse 0.98 1.16 1.45 10 pulse 0.63 0. 74 1.29 Page 28 200818321 Similarly, Figures 9, 10 and 11 show improvement The situation and the surface roughness are significantly reduced. Figure 9 is an atomic force microscopy (fine image of the initial split table ® 123 of the SiOG structure 1GG formed using the previously described manufacturing process example. Figure 10 shows the same SiO structure in Figure 9 after ten passes of 1250 mj/cm 2 Atomic force microscopy image after laser pulse. Comparing the image of Figure g with the image of Figure 1, it clearly shows that the annealing process removes the surface and uses a relatively high pulse energy density (1250 mJ/cm 2 ) to achieve a better surface. The reduction in roughness. However, at these high energy densities, local defects such as cracks are formed in the film by the annealing process, which is caused by the outward diffusion of hydrogen. In some cases, during the annealing process. It is beneficial to use continuous high energy density filaments continuously. As shown in more detail in Figures 11A, 11B, 12A, and 12B, the annealing process produces a relatively smooth restored implant surface 123A of the damaged surface 122A. (1) Structure 1 on the semiconductor layer 104. Figures 11A and 11B are half-new layers formed before annealing and after annealing, respectively; | 104 Transmissive pre-micromirror (TEM) cross-sectional image in Figure 11B The annealing process includes a pulse of 1 ( (6) Å / 平方 cm. Figures 12A and 12B show the planar image of the buckling electron microscope (simplified) of the semiconductor layer formed before and after annealing, respectively. In this example, annealing is performed by applying 15 pulses of 8 〇〇mJ/cm 2 followed by 10 1200 mJ/cm 2 pulses. In FIGS. 11A and 12A, the surface damage 122A of the initial split surface 123 is significant, wherein the annealed surface 12 Hongyuan is cleaner than shown in Figures 11B and 12B, and exhibits higher quality crystals. In the same case, Figure 13 shows optical reflection data from SiOG structure 100, both of which are formed by the split surface, and at 1 1000 1000mJ/square page 29, 200818321 cm pulsed annealed surface 123A. For irradiated and unirradiated films, the interference fringes 160 on the right are almost equal, indicating that the film thickness is not changed by laser illumination, the discovery is via the surface The distribution measurement is confirmed, but for the case where the annealed surface 123A having a wavelength of less than 400 nm is absolutely reflected as exceeding the split surface 123. This increased reflection is a surface roughness. The reduced characteristics, like the conclusions obtained from the AFM data, and the crystal defects at the surface of the film will be reduced. In addition, the data of the irradiated sample is consistent with the data on the surface of the single crystal germanium which is not drawn. An electronic measurement was performed to confirm that the annealed surface 123A was close to the single crystal. These measurements further showed that the number of conductive active hydrogen atoms was not reduced in the film. Thus, the laser annealing treatment was substantially captured by the release. The hydrogen ions and the implant damage are removed by returning the semiconductor layer 1〇4 to near the single crystal state, and the surface U3A is smoothed. In summary, the present invention contemplates the first application of a laser annealing to an SOI substrate formed by hydrogen ion implantation. It provides a unique solution to simultaneously improve surface roughness and crystallization of flaws. While the invention has been described with respect to the specific embodiments thereof It is to be understood that the various embodiments of the present invention are susceptible to various modifications and alternatives. BRIEF DESCRIPTION OF THE DRAWINGS In order to illustrate the various features of the invention, wherein like reference numerals refer to the In combination, the present invention is limited only by the scope of the patent application filed on page 30, 200818321. The embodiment shows a flow chart in accordance with the present invention or a plurality of actual plots, which shows a flow chart for performing the processing steps of the first plan. Na" Processing = Seven graphs are nuclear maps showing the SOI structure after laser annealing. Eight 81H辄 辄 it it} The process of processing the structure on the body surface. The ninth picture shows the atomic force microscopy image of the exemplary semiconductor layer that was not trimmed prior to laser annealing. The tenth photo shows the atomic force microscopic image of the same semiconductor layer in the ninth figure after laser annealing. Tenth-A and Ten-B are respectively showing transmission electron microscopic (TEM) cross-sectional images of exemplary semiconductor layers before and after annealing. Figure 11 and Figure 11B show electron microscopy (SEM) planar images of the exemplary semiconductor layers before and after annealing, respectively. Fig. 13 is a graph showing optical reflection data of a pre-laser annealed sample and optical reflection data of a post-stage laser annealed sample according to the present invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 10 is a schematic representation of a semiconductor on insulator (SOI) structure 100; a glass substrate 102; a semi- & body layer 104; a donor semiconductor wafer 120; an implant surface 121; an epitaxial wafer 122; a damaged material 122A; Portion 122B, 123C; split surface page 31 200818321 123; annealed surface 123A; material 124; laser 150; radiation 155; treatment of the surface 202 of the donor semiconductor wafer; application of the donor semiconductor wafer to the ion implantation process 204; The donor semiconductor wafer is subjected to moderate oxidation of 2〇6; the anode is bonded between the epitaxial layer and the glass 208; the glass layer/epitaxial layer 210 is separated by the donor semiconductor wafer; and the donor semiconductor wafer or epitaxial layer is applied with a thunder An annealing treatment 212; conditioning the non-annealed semiconductor on insulator structure 802; transporting and positioning the SOI structure to the laser annealing assembly 8〇4; performing a laser annealing 806; transporting the SOI structure 808 by the laser annealing assembly. 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