TWI470682B - Substrate provided with semiconductor films and manufacturing method thereof - Google Patents

Description

Substrate provided with semiconductor film and method of manufacturing the same

The present invention relates to a substrate provided with a semiconductor film and a method of manufacturing the same. The substrate provided with the semiconductor film is a semiconductor substrate having a structure on insulator (SOI).

In recent years, VLSI technology has been rapidly developed, and attention has been paid by SOI technology that achieves speed increase and power consumption reduction. This technique is generally a technique in which an active region (channel formation region) of a field effect transistor (FET) made of a bulk single crystal germanium substrate is composed of a single crystal germanium film. It is well known that when a MOS field effect transistor is fabricated using an SOI structure instead of a conventional bulk single crystal germanium substrate, parasitic capacitance can be reduced, and such a MOS field effect transistor is advantageous in speeding up.

As the SOI substrate, SIMOX substrates and bonding substrates are known. For example, a SIMOX substrate having an SOI structure is fabricated in such a manner that oxygen ions are implanted into a bulk single crystal substrate and heat-treated at 1300 ° C or higher to form a buried oxide (BOX) layer; therefore, a single crystal germanium film is Formed on the surface of the BOX layer. In the manufacture of the SIMOX substrate, although the depth of the single crystal film can be precisely controlled so that the single crystal film can have a uniform thickness because the implantation of oxygen ions can be precisely controlled, the implantation of oxygen ions takes a long time. Time, so there is a problem with the operation time and cost. In addition, another problem is that the single crystal ruthenium film is easily destroyed by oxygen ion implantation.

A bonding substrate having an SOI structure is manufactured in such a manner that two single crystal germanium substrates (a bottom substrate and a bonding substrate) are bonded together with an oxide film interposed therebetween; and one of the single crystal germanium substrates (bonding substrate) is from the rear surface The (unjoined surface) is thinned to form a single crystal germanium film. As a method of thinning a substrate, it is difficult to form a thin and uniform single crystal germanium film by grinding and polishing, and thus a technique called "Smart Cut" (Smart Cutting) has been proposed using hydrogen ion implantation. (See Patent Document 1: Japanese Laid-Open Patent Application No. H5-211128).

However, the size of a conventional SOI substrate depends on the size of a single crystal germanium wafer, and it is difficult to achieve an increase in size for a conventional SOI substrate. Accordingly, it is an object of the present invention to provide a substrate provided with a semiconductor film which is larger than a single crystal germanium substrate and which is bonded to a plurality of single crystal germanium semiconductor layers. Another object is to provide a method of fabricating a substrate provided with a semiconductor film by which a plurality of single crystal germanium semiconductor layers can be efficiently bonded to a large-area substrate.

One aspect of the substrate provided with the semiconductor film of the present invention includes a bottom substrate, a plurality of insulating layers in close contact with the upper surface of the bottom substrate, and a single crystal germanium semiconductor layer in close contact with the upper surface of each of the insulating layers . As the base substrate, it is preferred to use a substrate having a side of 300 mm or longer.

An aspect of a method of fabricating a substrate provided with a semiconductor film according to the present invention includes the steps of: preparing a bottom substrate and a plurality of single crystal semiconductor substrates formed on an upper surface of the single crystal semiconductor substrates and at each single crystal A damaged region in the semiconductor substrate is formed at a desired depth; a plurality of single crystal semiconductor substrates are disposed on the disk; and the plurality of single crystal semiconductor substrates placed on the disk are in close contact with the bottom substrate with a bonding layer interposed therebetween for bonding One surface of the layer and one surface of the bottom substrate such that the bottom substrate and the plurality of single crystal semiconductor substrates are bonded to each other; and cracks are generated in the damaged region by heating a plurality of single crystal semiconductor substrates placed on the disk, Thereby, a bottom substrate in which a plurality of first single crystal semiconductor layers separated from the single crystal semiconductor substrate are in close contact is formed.

An aspect of a method of fabricating a substrate provided with a semiconductor film according to the present invention includes the steps of: preparing a bottom substrate and a plurality of single crystal semiconductor substrates formed on an upper surface of the single crystal semiconductor substrates and at each single crystal A damaged region in the semiconductor substrate is formed at a desired depth; a plurality of single crystal semiconductor substrates are disposed on the first disk; and the plurality of single crystal semiconductor substrates placed on the first disk are in close contact with the bottom substrate with a bonding layer interposed therebetween To bond one surface of the bonding layer and one surface of the bottom substrate such that the bottom substrate and the plurality of single crystal semiconductor substrates are bonded to each other; and by heating a plurality of single crystal semiconductor substrates placed on the first disk A crack is formed in the damaged region, thereby forming a bottom substrate in which the plurality of first single crystal semiconductor layers separated from the single crystal semiconductor substrate are in close contact.

In the forming step of the insulating layer, the plurality of single crystal substrates placed on the second tray may be placed in a reaction chamber containing a fluoride gas or a fluorine gas, and the processing gas may be introduced into the reaction chamber, and the processing gas may be excited To generate a plasma, a chemical reaction of the active species included in the plasma can be performed to form an insulating film having a single layer or two or more layers. The same disc or a different disc can be used as the first disc and the second disc.

Fluoride gas or fluorine gas may be contained in the reaction chamber in such a manner that the fluoride gas or fluorine gas is left in the reaction chamber by plasma gas etching or fluorine gas cleaning by plasma gas etching. Alternatively, a fluoride gas or a fluorine gas may be contained in the reaction chamber by supplying a fluoride gas or a fluorine gas into the reaction chamber.

In the above invention, a substrate having a side of 300 mm or longer is preferably used as the base substrate. Further, the bonding layer is preferably formed on the insulating layer which is formed in contact with the single crystal semiconductor substrate.

The substrate provided with the semiconductor film of the present invention is a substrate having an SOI structure having a larger area than a bulk single crystal semiconductor substrate such as a germanium wafer. Therefore, by using the substrate provided with the semiconductor film of the present invention, the productivity of a semiconductor device such as a semiconductor integrated circuit can be improved. Note that in the present specification, a semiconductor device generally refers to a device that can function by utilizing semiconductor characteristics.

According to the manufacturing method of the present invention, a substrate provided with a semiconductor film having an SOI structure having a larger area than a bulk single crystal semiconductor substrate such as a germanium wafer can be manufactured.

Hereinafter, the present invention will be described. It will be readily apparent to those skilled in the art that the present invention may be practiced in many different ways and the various embodiments and details disclosed herein may be modified in various ways without departing from the spirit and scope of the invention. Therefore, the invention should not be construed as being limited to the description of the embodiments. Note that elements denoted by the same reference numerals in the different drawings are the same elements; therefore, repeated description of materials, shapes, manufacturing methods, and the like are omitted.

Embodiment 1

In Embodiment 1, a substrate provided with a semiconductor film having an SOI structure, which is a substrate provided with a plurality of single crystal semiconductor layers, and a method of manufacturing the same are described.

FIG. 1 is a perspective view showing a structural example of a substrate 100 provided with a semiconductor film. As the substrate 100 provided with the semiconductor film, a plurality of single crystal semiconductor layers 116 are bonded to the base substrate 101. Each of the single crystal semiconductor layers 116 is disposed on the base substrate 101 with the insulating layer 102 interposed therebetween, and the substrate 100 provided with the semiconductor film is a so-called semiconductor substrate having an SOI structure. Therefore, the substrate 100 provided with the semiconductor film will hereinafter be referred to as "semiconductor substrate 100".

The insulating layer 102 may have a single layer structure or a stacked structure. In the present embodiment, the insulating layer 102 has a three-layer structure. Above the bottom substrate 101, the bonding layer 114, the insulating film 112b, and the insulating film 112a are stacked in this order.

Each of the single crystal semiconductor layers 116 is a layer formed by thinning a single crystal semiconductor substrate. A commercially available semiconductor substrate can be used as the single crystal semiconductor substrate. For example, a single crystal semiconductor substrate made of a Group 4 element such as a single crystal germanium substrate, a single crystal germanium substrate, or a single crystal germanium-germanium substrate can be used. Alternatively, a compound semiconductor substrate including gallium arsenide, indium phosphide, or the like can be used.

As the base substrate 101, a substrate having an insulating surface is used. Specifically, various glass substrates used in the electronics industry, such as a substrate using an aluminosilicate glass, an aluminoborosilicate glass, or a bismuth borate glass, may also be mentioned, as well as a quartz substrate, a ceramic substrate, and Sapphire base. Preferably, a glass substrate is used as the bottom substrate 101. As the glass substrate, a coefficient of thermal expansion higher than or equal to 25 × 10 ^-7 / ° C and lower than or equal to 50 × 10 ^-7 / ° C (preferably higher than or equal to 30 × 10 ^-7 / ° C and lower or A glass substrate equal to 40 x 10 ^-7 / ° C) and having a distortion point higher than or equal to 580 ° C and lower than or equal to 680 ° C (preferably higher than or equal to 600 ° C and lower than or equal to 680 ° C). Further, in order to suppress contamination of the semiconductor device, the glass substrate is preferably an alkali-free glass. As a material of the alkali-free glass substrate, a glass material such as aluminosilicate glass, aluminoborosilicate glass, or bismuth borate glass can be cited. Further, as the base substrate 101, an insulating substrate made of an insulator such as a ceramic substrate, a quartz substrate, and a sapphire substrate; a conductive substrate made of a conductor such as metal or stainless steel; or a material such as germanium or gallium arsenide may be used. A semiconductor substrate made of a semiconductor or the like instead of a glass substrate.

As the base substrate 101, it is preferred to use a substrate of 300 mm × 300 mm or more. For example, as such a large-area substrate, a mother glass substrate developed for manufacturing a liquid crystal panel is preferably used. Substrates of the following sizes are known as mother glass substrates, such as: third generation (550 mm x 650 mm), 3.5th generation (600 mm x 720 mm), fourth generation (680 mm x 880 mm or 730 mm x 920 mm), fifth generation (1100mm × 1300mm), sixth generation (1500mm × 1850mm), seventh generation (1870mm × 2200mm), eighth generation (2200mm × 2400mm) and so on. By fabricating an SOI substrate using a large-area mother glass substrate as the bottom substrate 101, an increase in the size of the SOI substrate can be achieved.

The size increase of the SOI substrate can be achieved by using a large-area substrate such as a mother glass substrate as the bottom substrate 101. When the size of the SOI substrate is increased, a large number of IC chips, LSI wafers, and the like can be fabricated from one SOI substrate. This can greatly increase productivity due to an increase in the number of wafers manufactured from one substrate.

Referring to FIGS. 2, 3, 4, 5A and 5B, FIGS. 6A and 6B, FIGS. 7A-7D, FIGS. 8A and 8B, FIG. 9, and FIGS. 10A and 10B, the semiconductor substrate 100 shown in FIG. 1 is described ( A method of manufacturing a substrate 100) provided with a semiconductor film.

First, a single crystal semiconductor substrate 111 is prepared. The single crystal semiconductor substrate 111 is processed to a desired size and shape. FIG. 2 is an external view showing one example of the structure of the single crystal semiconductor substrate 111. The shape of the single crystal semiconductor substrate 111 when considering the fact that the shape of the base substrate 101 to which the single crystal semiconductor substrate 111 is bonded is rectangular, and the exposure region of the exposure device such as a reduced-projection exposure device is rectangular It is preferably a rectangle, as shown in Figure 2. Note that squares can also be included as rectangles unless otherwise specified. For example, the length of the long side of the rectangular single crystal semiconductor substrate 111 is preferably processed to be n times the length of the side of one shot of the exposed area of one projection of the miniature projection exposure apparatus (n is any positive integer, and ).

The rectangular single crystal semiconductor substrate 111 can be formed by cutting a commercially available circular bulk single crystal semiconductor substrate. In order to cut the substrate, a cutting device such as a dicer or a wire saw, a cutting device such as a laser cutter, a plasma cutter or an electron beam cutter may be used. Alternatively, the crystal block for fabricating the semiconductor substrate may be processed into a rectangular body to have a rectangular cross section before being cut into a substrate, and the crystal block of the rectangular parallelepiped may be cut to manufacture a rectangular single crystal semiconductor substrate 111.

Note that in the case where a substrate made of a Group 4 element having a crystal structure of a diamond structure (such as a single crystal germanium substrate) is used as the single crystal semiconductor substrate 111, the plane orientation of the main surface thereof may be (100), ( 110) or (111). By using the single crystal semiconductor substrate 111 having the main surface (100), the interface state density between the single crystal semiconductor layer 116 and the insulating layer formed on the surface thereof can be made low, which is when manufacturing the field effect transistor advantageous.

By using the single crystal semiconductor substrate 111 having the main surface (110), a tight bond between an element included in the insulating film 112a and a Group 4 element (for example, a lanthanum element) included in the single crystal semiconductor layer 116 is A formation surface is formed between the insulating film 112a and the single crystal semiconductor layer 116. Therefore, the bonding force between the bonding layer 114 and the single crystal semiconductor layer 116 is improved.

By using the single crystal semiconductor substrate 111 having the main surface (110), the planarity of the single crystal semiconductor layer 116 is improved because atoms are densely arranged on the main surface as compared with other planarly oriented surfaces. Therefore, a transistor fabricated using the single crystal semiconductor layer 116 having the main surface (110) has excellent electrical characteristics such as a small S value and a high electron field effect mobility. Note that the single crystal semiconductor substrate having the main surface (110) has a Young's modulus higher than that of the single crystal semiconductor substrate having the main surface (100), and has an advantage that cracks are easily formed.

After the single crystal semiconductor substrate 111 is cleaned, a plurality of single crystal semiconductor substrates 111 are placed on the disk 10. FIG. 3 is an external view showing a structural example of the disk 10. The disk 10 is a plate-like member, and is provided with a plurality of recesses 11 for accommodating the single crystal semiconductor substrate 111. The disk shown in FIG. 3 is a disk for manufacturing the semiconductor substrate 100 of FIG. 1, in which the recesses 11 are formed in three rows and three columns. As shown in FIG. 4, a single crystal semiconductor substrate 111 is placed on the disk 10 to be loaded into the recess 11. FIG. 4 is an external view showing a state in which a plurality of single crystal semiconductor substrates 111 are placed on the disk 10.

The disk 10 is fabricated using a material that does not change its quality and shape by heat treatment during the manufacturing process of the semiconductor substrate 100. Specifically, it is preferable to select a material that does not expand much by heat treatment. For example, the disk 10 can be manufactured using quartz glass, stainless steel, alkali-free glass, or the like.

The thickness of the disk 10 may be equal to or greater than 1.1 mm and equal to or less than 2 mm. The depth of the recess 11 may be equal to or larger than 0.2 mm and equal to or smaller than 0.6 mm, and is preferably equal to or larger than 0.3 mm and equal to or smaller than 0.5 mm. The disk 10 preferably has the same dimensions as the bottom substrate 101. The recess 11 may have a size in which the single crystal semiconductor substrate 111 is fitted into the recess 11. As shown in FIG. 4, in the manufacturing method of the present embodiment, the size and array of the single crystal semiconductor layer 116 of the semiconductor substrate 100 are limited by the size and array of the recesses 11.

5A and 5B and Figs. 6A and 6B are plan views showing structural examples of the disk 10. 5A and 5B are plan views of the disk 10 in the case where a mother glass substrate having a size of 600 mm × 720 mm is used as the base substrate 101, wherein the disk 10 has a size of 600 mm × 720 mm. 6A and 6B are plan views of the disk 10 in the case where a fourth generation mother glass substrate having a size of 730 mm × 920 mm is used as the base substrate 101, wherein the disk 10 has a size of 730 mm × 920 mm.

Figure 5A is a plan view of disk 10 selected to conform to a miniature projection exposure apparatus having an exposed area of 4 inches on each side, taking into account the size and array of recesses 11. The disk 10 is divided into four blocks, and in each block, nine recesses 11 are formed in three rows and three columns. The recesses 11 each have a size of 102 mm x 82 mm to facilitate loading of the exposed area of one shot. In one block, the distance between adjacent recesses 11 of each row and column is 11 mm, and the distance from the sides of the disk 10 to the sides of the recess 11 closest to the sides of the disk 10 in the longitudinal and lateral directions is 16 mm.

Figure 5B is a plan view of the disc 10 selected to conform to the miniature projection exposure apparatus having an exposed area of 5 inches on each side, taking into account the size and array of recesses 11. The disk 10 is divided into four blocks, and in each block, six recesses 11 are formed in three rows and two columns. The recesses 11 each have a size of 102 mm x 130 mm to facilitate loading of the exposed area of one shot. In one block, the distance between adjacent recesses 11 in each column is 11 mm, and the distance between adjacent recesses 11 in each row is 10 mm. The distance from the sides of the disk 10 to the sides of the recess 11 closest to the sides of the disk 10 in the longitudinal and lateral directions is 16 mm.

Figure 6A is a plan view of disk 10 selected to conform to a miniature projection exposure apparatus having an exposure zone having a size of 4 inches on each side, taking into account the size and array of recesses 11. The disk 10 is divided into six blocks, and nine recesses 11 are formed in three rows and three columns in each block. The recesses 11 each have a size of 105 mm x 84 mm to facilitate loading of the exposed area of one shot. In one block, the distance between adjacent recesses 11 in each column is 10 mm, and the distance between adjacent recesses 11 in each row is 10 mm. The distance from each side of the disc 10 to the side of the recess 11 closest to each side of the disc 10 is 16 mm, and the distance from each side of the disc 10 to the side of the recess 11 closest to each side of the disc 10 is 15 mm.

Figure 6B is a plan view of the disc 10 selected to conform to the miniature projection exposure apparatus having an exposed area of 5 inches on each side, taking into account the size and array of recesses 11. The disk 10 is divided into six blocks, and six recesses 11 are formed in two rows and three columns in each block. The recesses 11 each have a size of 132 mm x 105 mm to facilitate loading of the exposed area of one shot. In one block, the distance between adjacent recesses 11 in each column is 13 mm, and the distance between adjacent recesses 11 in each row is 10 mm. The distance from the sides of the disk 10 to the sides of the recess 11 closest to the sides of the disk 10 in the longitudinal and lateral directions was 15 mm.

Hereinafter, a method of manufacturing the semiconductor substrate 100 after depositing the single crystal semiconductor substrate 111 on the disk 10 as shown in FIG. 3 will be described with reference to cross-sectional views of FIGS. 7A to 10B. First, as shown in FIG. 7A, an insulating layer 112 is formed on a single crystal semiconductor substrate 111. The insulating layer 112 may have a single layer structure or a multilayer structure of two or more layers. The thickness of the insulating layer 112 may be greater than or equal to 5 nm and less than or equal to 400 nm. As the insulating layer 112, an insulating film containing germanium or antimony in its composition, such as a hafnium oxide film, a tantalum nitride film, a hafnium oxynitride film, a hafnium oxynitride film, a hafnium oxide film, a tantalum nitride film, or an oxygen-nitrogen can be used. A ruthenium film or a ruthenium oxynitride film. Alternatively, an insulating film made of a metal oxide such as alumina, yttria, or lanthanum oxide; an insulating film made of a metal nitride such as aluminum nitride; a metal oxide such as an aluminum oxynitride film may be used. An insulating film made of nitride; or an insulating film made of metal oxynitride such as an aluminum oxynitride film.

Note that in the present specification, oxynitride refers to a substance in which the number of oxygen atoms is greater than the number of nitrogen atoms, and nitrogen oxide refers to a substance in which the number of nitrogen atoms is greater than the number of oxygen atoms. . For example, yttrium oxynitride has an oxygen content in the range of 55 atom% to 65 atom%, a nitrogen content in the range of 0.5 atom% to 20 atom%, and a Si content in the range of 25 atom% to 35 atom%, hydrogen. A substance having a content in the range of 0.1 atom% to 20 atom%. In addition, bismuth oxynitride has an oxygen content in the range of 5 atom% to 30 atom%, a nitrogen content in the range of 20 atom% to 55 atom%, a Si content in the range of 25 atom% to 35 atom%, and a hydrogen content. A substance in the range of 10 atom% to 30 atom%. Note that the composition of oxynitride and oxynitride can be measured using Rutherford backscatter spectroscopy (RBS) and hydrogen forward scatter (HFS). Note that the percentage of oxygen, nitrogen, hydrogen, and helium is a value when the total number of atoms contained in yttrium oxynitride or yttrium oxynitride is defined as 100 at.%.

The insulating film forming the insulating layer 112 can be formed by a CVD method, a sputtering method, a method of oxidizing or nitriding the single crystal semiconductor substrate 111, or the like.

In the case where a substrate containing an impurity such as an alkali metal or an alkaline earth metal which lowers the reliability of the semiconductor device is used as the underlying substrate 101, the insulating layer 112 is preferably provided with at least one layer which prevents such impurities from diffusing from the underlying substrate 101. a film to a semiconductor layer of an SOI substrate. Examples of such a film include a tantalum nitride film, a hafnium oxynitride film, an aluminum nitride film, and an aluminum nitride oxide film. By including such a film, the insulating layer 112 can function as a barrier layer.

For example, in the case where the insulating layer 112 is formed as a barrier layer having a single layer structure, a tantalum nitride film, a hafnium oxynitride film, an aluminum nitride film, or an aluminum nitride oxide film having a thickness of 5 nm to 200 nm can be formed.

In the case where the insulating layer 112 is formed as a barrier layer having a two-layer structure, the upper layer is composed of an insulating film having a high barrier function. As such an insulating film, a tantalum nitride film, a hafnium oxynitride film, an aluminum nitride film, or an aluminum nitride oxide film having a thickness of 5 nm to 200 nm can be formed. These films have a high barrier effect of preventing diffusion of impurities, but have high internal stress. Therefore, as the lower insulating film that is in contact with the single crystal semiconductor substrate 111, it is preferable to select a film having an effect of reducing the stress of the upper insulating film. Examples of such an insulating film include a hafnium oxide film, a tantalum nitride film, a thermal oxide film formed by thermally oxidizing the single crystal semiconductor substrate 111, and the like. The thickness of the underlying insulating film may be 5 nm to 300 nm.

In the present embodiment, the insulating layer 112 has a two-layer structure including an insulating film 112a and an insulating film 112b. As a combination of the insulating film 112a serving as a barrier film in the insulating layer 112 and the insulating film 112b, the following can be given as an example. A ruthenium oxide film and a tantalum nitride film, a bismuth oxynitride film and a tantalum nitride film, a ruthenium oxide film and a ruthenium oxynitride film, a bismuth oxynitride film, a ruthenium oxynitride film, and the like.

For example, the upper insulating film 112a may be composed of a yttrium oxynitride film formed by a plasma-excited CVD method (hereinafter referred to as "PECVD method") using SiH ₄ and N ₂ O as a processing gas. Alternatively, as the insulating film 112a, the yttrium oxide film can be formed by a PECVD method using organic decane and oxygen as a processing gas. Still alternatively, the insulating film 112a may be composed of an oxide film formed by oxidizing the single crystal semiconductor substrate 111.

The organic decane is a compound such as ethyl citrate (tetraethoxy decane, abbreviated as TEOS, chemical formula: Si(OC ₂ H ₅ ) ₄ ), tetramethyl decane (TMS, chemical formula: Si(CH ₃ ) ₄ ) Tetramethylcyclotetraoxane (TMCTS), octamethylcyclotetraoxane (OMCTS), hexamethyldioxane (HMDS), triethoxydecane (SiH(OC ₂ H ₅ ) ₃ ), tris(dimethylamino)decane (SiH(N(CH ₃ ) ₂ ) ₃ ), and the like.

The lower insulating film 112b may be a hafnium oxynitride film formed by a PECVD method using SiH ₄ , N ₂ O, NH _{3 ,} and H ₂ as a processing gas, or by using SiH ₄ , N ₂ , N _{3 ,} and H ₂ It is composed of a tantalum nitride film formed by a PECVD method as a processing gas.

For example, in the case where the insulating film 112a made of hafnium oxynitride and the insulating film 112b made of hafnium oxynitride are formed by a PECVD method, a plurality of single crystal semiconductor substrates 111 are loaded into a processing chamber of a PECVD apparatus. Then, SiH ₄ and N ₂ O are supplied to the processing chamber as a processing gas for forming the insulating film 112a, plasma of these processing gases is generated, and a hafnium oxynitride film is formed on the single crystal semiconductor substrate 111. Then, the gas introduced into the processing chamber is switched to the processed gas for forming the insulating film 112b. Here, SiH ₄ , NH ₃ , H ₂ and N ₂ O are used. A plasma of a mixed gas of these gases is generated, and a ruthenium oxynitride film is formed without interruption on the yttrium oxynitride film. Also, in the case of using a PECVD apparatus having a plurality of processing chambers, a hafnium oxynitride film and a hafnium oxynitride film can be formed in different processing chambers. Of course, by switching the gas introduced into the process chamber, the ruthenium oxide film can be formed as a lower layer, and the tantalum nitride film can be formed as an upper layer.

By forming the insulating film 112a and the insulating film 112b in the above manner, the insulating layer 112 can be formed on the plurality of single crystal semiconductor substrates 111 with an advantageous throughput. Further, since the insulating film 112a and the insulating film 112b can be formed without being exposed to the atmosphere, contamination of the interface between the insulating film 112a and the insulating film 112b by the atmosphere can be prevented.

Alternatively, an oxide film formed by oxidizing the single crystal semiconductor substrate 111 can be used as the insulating film 112a. The thermal oxidation treatment for forming the oxide film may be dry oxidation, but it is preferred to add a halogen-containing gas to an oxygen atmosphere. As the halogen-containing gas, one or more types of gases selected from the group consisting of HCl, HF, NF ₃ , HBr, Cl, ClF, BCl ₃ , F, Br ₂ and the like can be used.

For example, heat treatment is performed in an atmosphere of HCl having a volume ratio of 0.5% to 10% (preferably, a volume ratio of 3%) at 700 ° C or higher. Preferably, the thermal oxidation is carried out at a heating temperature of 950 ° C to 1100 ° C. The treatment time can be from 0.1 to 6 hours, preferably from 0.5 to 1 hour. The thickness of the oxide film formed can be made 10 nm to 1000 nm (preferably 50 nm to 200 nm), for example, 100 nm.

By performing the oxidation treatment in this temperature range, the gettering action of the halogen element can be obtained. As the gettering action, specifically, the effect of removing metal impurities is obtained. That is, impurities such as metals are converted into volatile chlorides by the action of chlorine, and then discharged in the vapor phase and removed from the single crystal semiconductor substrate 111. Further, by using a halogen element in the oxidation treatment, the dangling bonds on the surface of the single crystal semiconductor substrate 111 are terminated, and the local level density of the interface between the oxide film and the single crystal semiconductor substrate 111 can be lowered.

The oxide film may contain a halogen by performing the thermal oxidation treatment in a halogen-containing atmosphere. By the concentration of the halogen-containing element being 1 × 10 ¹⁷ atoms/cm ³ to 5 × 10 ²⁰ atoms/cm ³ , in the semiconductor substrate 100, the oxide film can exhibit a protective film function, that is, by capturing impurities such as metal to prevent The single crystal semiconductor layer 116 is contaminated.

As an example of a method for forming the lower insulating film 112a by thermal oxidation treatment and forming the upper insulating film 112b by a vapor deposition method such as PECVD, the following method can be used: the single crystal semiconductor substrate 111 is placed The insulating film 112a is formed by thermal oxidation treatment on the disk 10, and the single crystal semiconductor substrate 111 of the insulating film 112a on which the oxide film has been formed is placed on the disk 10, and then the insulating film 112b is formed.

In the present embodiment, at least one of the insulating films included in the insulating layer 112 having a single layer structure or a laminated structure is preferably a fluorine-containing insulating film. Specifically, an insulating layer 112 in contact with the single crystal semiconductor substrate 111 is preferably formed using a fluorine-containing insulating film. In the case of the present embodiment, fluorine can be contained in the insulating film 112a by forming the insulating film 112a in the reaction chamber of the fluorine-containing gas or fluorine gas PECVD apparatus. A process gas for forming the insulating film 112a is introduced into the reaction chamber, the process gas is excited to generate a plasma, and a chemical reaction of the active species included in the plasma is caused, so that the insulating film 112a is on the single crystal semiconductor substrate 111. Formed on.

The cleaning chamber is etched by plasma gas etching using a fluoride gas, and the fluorine compound gas may be contained in a reaction chamber of the PECVD apparatus. When the film is formed by a PECVD apparatus, the product produced by the reaction of the source material is deposited not only on the surface of the substrate but also on the inner wall of the reaction chamber, the electrode, the substrate holder, and the like. These deposited products are the cause of particles and dust. Therefore, the washing step of removing these deposited products is performed periodically. As a typical cleaning method of the reaction chamber, a method of etching using a plasma gas can be mentioned. This is a method in which a fluoride gas such as NF ₃ is introduced into the reaction chamber, the fluoride gas is excited to generate a plasma to generate a fluorine group, and the deposition product is etched for removal. Since the fluoride produced by the reaction with the fluorine group has a high vapor pressure, the fluoride is removed from the reaction chamber by the exhaust system.

When cleaning by plasma gas etching, the fluoride gas used as the cleaning gas is adsorbed on the inner wall of the reaction chamber and the electrodes and various tools disposed in the reaction chamber. That is, a fluoride gas can be contained in the reaction chamber. Note that as a method for causing a fluoride gas to be contained in the reaction chamber, a method in which a fluoride gas is introduced into the reaction chamber after the single crystal semiconductor substrate 111 placed on the disk 10 is disposed in the reaction chamber, and fluorine is used therein A method in which the chemical gas purges the reaction chamber and retains the fluoride gas in the reaction chamber.

For example, in the case where a hafnium oxynitride film is formed as the insulating film 112a by a PECVD method using SiH ₄ and N ₂ O, SiH ₄ and N ₂ O are supplied to the reaction chamber, and these gases are excited to generate a plasma, The fluoride gas remaining in the reaction chamber is also excited to form a fluorine group. Thus, the yttrium oxynitride film can be fluorine-containing. In addition, a small amount of fluoride remains in the reaction chamber, and the fluoride is not supplied during the formation of the yttrium oxynitride film. Therefore, fluorine is introduced in the early stage of forming a yttrium oxynitride film. In this manner, in the insulating film 112a, the concentration of fluorine can be increased on the interface between the single crystal semiconductor substrate 111 and the insulating film 112a (insulating layer 112) or in the vicinity of the interface. That is, in the insulating layer 112 of the semiconductor substrate 100 shown in FIG. 1, the concentration of fluorine may increase on the interface with the single crystal semiconductor layer 116 or in the vicinity of the interface.

The dangling bonds in the semiconductor at the interface with the single crystal semiconductor layer 116 can be terminated with fluorine by making the region fluorine-containing; accordingly, the interface state density between the single crystal semiconductor layer 116 and the insulating layer 112 can be lowered. Further, even in the case where a metal such as sodium diffuses from the base substrate 101 to the insulating layer 112, if fluorine exists, the metal can be trapped by the fluorine, thereby preventing the single crystal semiconductor layer 116 from being contaminated with metal.

Instead of the fluoride gas, the reaction chamber may also contain fluorine gas (F ₂ ). Fluoride is a compound containing fluorine (F) in its composition. As the fluoride gas, a gas selected from the group consisting of OF ₂ , ClF ₃ , NF ₃ , FNO, F ₃ NO, SF ₆ , SF ₅ NO, SOF ₂ or the like can be used. Alternatively, any of the following fluorine compound gases containing carbon in the composition may be used as the fluoride gas: perfluorocarbon (PFC), hydrofluorocarbon (HFC), hydrochlorofluorocarbon (HCFC), fluoroether, carbon Acyl fluoride and fluoroester.

As the perfluorocarbon, CF ₄ , C ₂ F ₆ , C ₃ F ₈ , C ₄ F ₁₀ , C ₃ F ₈ , C ₄ F ₆ , C ₄ F ₈ , C ₅ F ₈ or the like can be used. As the hydrofluorocarbon, CF ₃ CHF ₂ , CHF ₂ CHF ₂ , CF ₃ CHFCF ₃ , CF ₃ CF ₂ CHF ₂ , CHF ₂ CF ₂ CHF ₂ or the like can be used. As the fluoroether, hydrofluoroether (HFE) such as CHF ₂ OCHF ₂ , CF ₃ OCHFCF ₃ can be used; CF ₃ OCF=CF ₂ , C ₂ F ₅ OCF=CF ₂ , C ₃ F ₆ O, C ₃ F ₆ O ₂ , C ₄ F ₈ O, C ₄ F ₈ O ₂ and the like. As the carbonyl fluoride, CF ₃ COCF ₃ or the like can be used. As the fluoroalkyl ester, may be used _{CF 3 COOCHF 2, CF 3 COOC} 2 F 5 and the like.

As the fluorine-containing compound gas containing carbon in the composition, it is also possible to use a compound selected from the group consisting of COF ₂ , CF ₃ COF, CF ₂ (COF) ₂ , C ₃ F ₇ COFCF ₃ OF, CF ₃ I, CF ₃ OOCF ₃ , CF ₃ OOOCF. ₃ , CF ₃ CN, CF ₃ NO and other gases.

Next, a step of forming the damaged region 113 in each of the single crystal semiconductor substrates 111 will be described with reference to FIG. 7B. An ion beam 121 composed of ions accelerated by an electric field is emitted through the insulating layer 112 to the single crystal semiconductor substrate 111 to form a damaged region 113 in a region of a predetermined depth from the surface of the single crystal semiconductor substrate 111. The ion irradiation step is a step in which the single crystal semiconductor substrate 111 is irradiated with the ion beam 121 composed of the accelerated ion species, and an element included in the ion species is added to the single crystal semiconductor substrate 111. Therefore, when the ion beam 121 is emitted to the single crystal semiconductor substrate 111, an embrittlement layer in which the crystal structure is brittle is formed at a predetermined depth in each of the single crystal semiconductor substrates 111 by the impact of the accelerated ion species. This layer is the damaged area 113. The ion beam 121 is generated by exciting a source gas to generate a plasma of the source gas, and then extracting ions contained in the plasma by an action of an electric field.

The depth of the region where the damaged region 113 is formed can be adjusted by controlling the acceleration energy and the incident angle of the ion beam 121. The acceleration energy can be adjusted by controlling the acceleration voltage, the dose, and the like. The damaged area 113 is formed in a region at the same depth as the average depth of the ions. The thickness of the semiconductor layer separated from the single crystal semiconductor substrate 111 is set depending on the depth to which the ions are added. The depth of the damaged region 113 is formed in the range of 50 nm to 500 nm, preferably in the range of 50 nm to 200 nm.

When ions are added to the single crystal semiconductor substrate 111, it is preferable to use an ion doping method which does not involve mass separation, and an ion implantation method which involves mass separation. This is because the tact time for forming the damaged region 113 in the plurality of single crystal semiconductor substrates 111 placed on the disk 10 can be shortened.

The single crystal semiconductor substrate 111 housed in the disk 10 is loaded into an ion doping apparatus. Then, the source gas is excited to generate a plasma, and ion species are extracted from the plasma and accelerated to generate an ion beam 121. The ion beam 121 is emitted to the plurality of single crystal semiconductor substrates 111; therefore, ions are introduced into a region of a predetermined depth at a high concentration, and the damaged regions 113 are formed in the single crystal semiconductor substrate 111.

In the case where hydrogen (H ₂ ) is used as the source gas, hydrogen gas can be excited to generate a plasma containing H ⁺ , H ₂ ⁺ and H ₃ ⁺ . The ratio of the ion species generated from the source gas can be changed by adjusting the excitation method of the plasma, the pressure of the atmosphere in which the plasma is generated, the supply amount of the source gas, and the like. When the total amount of H ⁺ , H ₂ ⁺ and H ₃ ⁺ contained in the ion beam 121 is defined as 100%, it is preferable to include H ₃ ⁺ greater than or equal to 50%, more preferably 80% or more. H ₃ ⁺ .

Since H ₃ ⁺ has a larger number of hydrogen atoms than other hydrogen ion species (H ⁺ and H ₂ ⁺ ) and has a larger mass, in the case of acceleration with the same energy, with H ⁺ and H ₂ ⁺ The shallower region of the single crystal semiconductor substrate 111 is implanted than H ₃ ⁺ . Therefore, with respect to the high percentage of H ₃ ⁺ contained in the ion beam 121, the change in the average penetration depth of the hydrogen ions becomes small; therefore, the concentration distribution of hydrogen in the depth direction in the single crystal semiconductor substrate 111 becomes steep, and The peak position of this distribution is shallow. Therefore, it is preferred that when the total amount of H ⁺ , H ₂ ⁺ and H ₃ ⁺ contained in the ion beam 121 is defined as 100%, it is preferable to include H ₃ ⁺ greater than or equal to 50%, more preferably Greater than or equal to 80% H ₃ ⁺ .

In the case of ion addition by ion doping using hydrogen, the accelerating voltage may be 10 kV to 200 kV, and the dose may be 1 x 10 ¹⁶ ions/cm ² to 6 x 10 ¹⁶ ions/cm ² . By adding hydrogen ions under this condition, the damaged region 113 can be formed in a region of the single crystal semiconductor substrate 111 at a depth of 50 nm to 500 nm, although it depends on the kind of ions contained in the ion beam 121 and its percentage.

For example, in the case where the source gas is hydrogen, the accelerating voltage is 40 kV, and the dose is 2.2 × 10 ¹⁶ ions/cm ² , wherein the single crystal semiconductor substrate 111 is a single crystal germanium substrate, and the insulating film 112a is oxygen nitrogen having a thickness of 50 nm. In the case where the insulating film 112b is a hafnium oxynitride film having a thickness of 50 nm, a single crystal semiconductor layer having a thickness of about 120 nm can be peeled off from the single crystal semiconductor substrate 111. Alternatively, when hydrogen ions are added under the same conditions as above but the insulating film 112a is a yttrium oxynitride film having a thickness of 100 nm, a single crystal semiconductor layer having a thickness of about 70 nm can be peeled off from the single crystal semiconductor substrate 111.

Helium (He) can also be used as the source gas of the ion beam 121. Since the ion species generated by exciting the helium gas is almost entirely He ⁺ by the ion doping method which does not involve mass separation, He ⁺ can be added to the single crystal semiconductor substrate 111 as a main ion. Therefore, the micropores can be efficiently formed in the damaged region 113 by the ion doping method. In the case of ion addition by ion doping using ruthenium, the acceleration voltage may be 10 kV to 200 kV, and the dose may be 1 x 10 ¹⁶ ions/cm ² to 6 x 10 ¹⁶ ions/cm ² .

A halogen gas such as chlorine gas (Cl ₂ gas) or fluorine gas (F ₂ gas) can be used as the source gas.

After the damaged region 113 is formed, the bonding layer 114 is formed on the upper surface of the insulating layer 112 as shown in FIG. In the step of forming the bonding layer 114, the heating temperature of the single crystal semiconductor substrate 111 is a temperature at which elements or molecules added to the damaged region 113 are not precipitated, and the heating temperature is preferably 350 ° C or lower. In other words, the heating temperature is the temperature at which the gas is not released from the damaged area 113. Note that the bonding layer 114 may be formed before the damaged region 113 is formed. In this case, the processing temperature for forming the bonding layer 114 may be 350 ° C or higher.

The bonding layer 114 is a layer for forming a smooth and hydrophilic bonding surface on the surface of the single crystal semiconductor substrate 111. Therefore, the average surface roughness Ra of the bonding layer 114 is equal to or less than 0.7 nm, and more preferably equal to or less than 0.4 nm. The thickness of the bonding layer 114 may be equal to or greater than 10 nm and equal to or less than 200 nm. The thickness is preferably equal to or greater than 5 nm and equal to or less than 500 nm, and more preferably equal to or greater than 10 nm and greater than or less than 200 nm.

The bonding layer 114 is preferably an insulating film formed by a chemical vapor phase reaction. For example, a tantalum oxide film, a hafnium oxynitride film, a hafnium oxynitride film, a tantalum nitride film, or the like can be formed as the bonding layer 114. In the case where a ruthenium oxide film is formed as the bonding layer 114 by the PECVD method, an organic decane gas and oxygen (O ₂ ) are preferably used as the source gas. The use of organic decane as a source gas enables a cerium oxide film having a smooth surface to be formed at a processing temperature of 350 ° C or lower. Alternatively, the bonding layer 114 may be formed using a low temperature oxide (LTO) formed by a thermal CVD method at a heating temperature of 200 ° C or higher and 500 ° C or lower. In order to form LTO, methotane (SiH4), acetylene (Si ₂ H ₆ ), or the like can be used as the helium source gas, and nitrous oxide (N ₂ O) or the like can be used as the oxygen source gas.

For example, an example of a condition for forming the bonding layer 114 of the hafnium oxide film by using TEOS and O ₂ as a source gas is that TEOS is introduced into the processing chamber at a flow rate of 15 sccm and O _{2 is} introduced at a flow rate of 750 sccm. The film forming pressure may be 100 Pa, the film forming temperature may be 300 ° C, the high frequency power output may be 300 W, and the power frequency may be 13.56 MHz.

The order of the steps of Figure 7B and the steps of Figure 7C can be reversed. In other words, after the insulating layer 112 and the bonding layer 114 are formed on the plurality of single crystal semiconductor substrates 111 placed on the disk 10, the damaged region 113 can be formed. In this case, if the insulating layer 112 and the bonding layer 114 can be formed by the same film forming apparatus, it is preferable to form the insulating layer 112 and the bonding layer 114 in order.

Still alternatively, after the step of FIG. 7B, the steps of FIG. 7A and the steps of FIG. 7C may be performed. In other words, after the damaged region 113 is formed by ion doping a plurality of single crystal semiconductor substrates 111 placed on the disk 10, the insulating layer 112 and the bonding layer 114 may be formed. In this case, if the insulating layer 112 and the bonding layer 114 can be formed by the same film forming apparatus, it is preferable to form the insulating layer 112 and the bonding layer 114 in order. Alternatively, in order to protect the surface of the single crystal semiconductor substrate 111, the single crystal semiconductor substrate 111 may be subjected to an oxidation treatment to form an oxide film on each surface, and the single crystal semiconductor substrate 111 may utilize ions before forming the damaged region 113. The species is doped through an oxide film. The oxide film is removed after the damaged region 113 is formed. Alternatively, the insulating layer 112 may be formed while retaining the oxide film.

Since the single crystal semiconductor substrate 111 is doped with the ion species generated from the source gas by the ion doping method to form the damaged region 113, ion species other than the ion species of the source gas are included in the ion beam 121. These other ion species are, for example, metals or the like that partially form the tool or electrode of the processing chamber of the ion doping apparatus. Since other ion species have a mass larger than that of a source gas such as hydrogen or helium, other ion species are introduced into a film formed on the surface of the single crystal semiconductor substrate 111 by doping (insulating layer 112) The surface of the bonding layer 114 or the oxide film). In order to remove impurities such as metals, the surface of the film formed on the surface of the single crystal semiconductor substrate 111 may be removed by wet etching after the ion doping step.

Next, the single crystal semiconductor substrate 111, which is provided with the insulating layer 112, the damaged region 113, and the bonding layer 114, is separated from the disk 10, and the plurality of single crystal semiconductor substrates 111 are cleaned. This washing step can be carried out by ultrasonic cleaning using pure water. As ultrasonic cleaning, megahertz ultrasonic cleaning (megasonic cleaning) is the best. After the ultrasonic cleaning, the single crystal semiconductor substrate 111 may be washed with ozone water. By ozone water washing, organic substances can be removed, and surface initiation of hydrophilicity of the surface of the bonding layer 114 can be performed. After the cleaning step and the surface start-up process, the single crystal semiconductor substrate 111 is placed in the recess 11 of the disk 10 as shown in Fig. 7D.

As the activation treatment of the surface of the bonding layer 114, irradiation treatment with an atomic beam or an ion beam, plasma treatment, or base treatment, and cleaning with ozone water can be performed. When an atomic beam or an ion beam is used, an inert gas neutral atom beam or an inert gas ion beam of argon gas or the like can be used. These processes can also be performed with the single crystal semiconductor substrate 111 placed on the disk 10.

Next, the single crystal semiconductor substrate 111 and the bottom substrate 101 placed on the disk 10 are attached. The bottom substrate 101 is also cleaned prior to attachment. At this time, washing with hydrochloric acid, hydrogen peroxide solution, or megahertz ultrasonic cleaning may be used. Similar to the bonding layer 114, it is preferable to perform surface activation treatment on the surface which becomes the bonding surface of the base substrate 101.

Fig. 8A is a cross-sectional view showing a joining step. The base substrate 101 is placed over the disk 10 on which the plurality of single crystal semiconductor substrates 111 are placed, and the base substrate 101 and the plurality of single crystal semiconductor substrates 111 are brought into close contact with each other with the bonding layer 114 interposed therebetween. A pressure of about 300 N/cm ² to 15000 N/cm ² is applied to a portion of the edge of the bottom substrate 101. The pressure is preferably from 1000 N/cm ² to 5000 N/cm ² . Due to the pressing member, the bonding layer 114 and the bottom substrate 101 start to be bonded to each other. Then, all of the single crystal semiconductor substrates 111 on the disk 10 are bonded to one of the base substrates 101 so that the plurality of single crystal semiconductor substrates 111 can be in close contact with the base substrate 101. This bonding step can be performed at room temperature without heat treatment; therefore, a substrate such as a glass substrate having heat resistance as low as an allowable temperature limit of 700 ° C or lower can be used as the base substrate 101.

Since the plurality of single crystal semiconductor substrates 111 are placed on the disk 10, there is a surface of the bonding layer 114 in a single crystal semiconductor substrate 111 which is not in contact with the bottom substrate 101 due to the difference in thickness between the single crystal semiconductor substrates 111. The situation. Therefore, it is preferable to apply pressure to not only a part (a single crystal semiconductor substrate) but to each single crystal semiconductor substrate 111. Further, even in the case where the height of the surface of the bonding layer 114 is changed in a state where the single crystal semiconductor substrate 111 is placed on the disk 10, if a part of the bonding layer 114 is in close contact with it due to deformation of the bottom substrate 101 Then, the entire surface of the bonding layer 114 can also be bonded.

After the bottom substrate 101 is placed on the disk 10 as shown in FIG. 8A, the position of the bottom substrate 101 can be changed to the bottom as shown in FIG. By inverting the bottom substrate 101 and the disk 10 upside down, the difference in thickness between the single crystal semiconductor substrates 111 can be offset, so that the entire surface of the bonding layer 114 can be easily brought into contact with the surface of the bottom substrate 101.

After bonding the single crystal semiconductor substrate 111 to the base substrate 101, heat treatment is preferably performed to increase the bonding force at the bonding interface between the bottom substrate 101 and the bonding layer 114. The treatment temperature is set to a temperature that does not cause cracks in the damaged region 113, and may be in a temperature range from 200 °C to 450 °C. Further, when the single crystal semiconductor substrate 111 is bonded to the base substrate 101 while being heated at a temperature within the above range, the bonding force on the bonding interface between the bottom substrate 101 and the bonding layer 114 can be made strong.

After the bottom substrate 101 is placed on the single crystal semiconductor substrate 111 above the disk 10 as shown in FIG. 8A, if the joint surface is contaminated by dust or the like, the bonded portion is not joined. Therefore, in order to prevent contamination on the joint surface, it is preferable to place the bottom substrate 101 in the sealed processing chamber. Further, the processing chamber preferably has a reduced pressure of about 5.0 × 10 ^-3 Pa, and it is preferable to keep the atmosphere in the joining process clean.

Next, heat treatment is performed to cause separation at the damaged region 113, whereby the single crystal semiconductor layer 115 is separated from the single crystal semiconductor substrate 111. FIG. 8B shows a separation step of separating the single crystal semiconductor layer 115 from the single crystal semiconductor substrate 111. The element indicated by reference numeral 117 is a single crystal semiconductor substrate 111 from which the single crystal semiconductor layer 115 is separated.

As shown in FIG. 8B, the peripheral portion of the single crystal semiconductor substrate 111 is not bonded to the base substrate 101 in many cases. This is because the peripheral portion of the single crystal semiconductor substrate 111 is chamfered when the single crystal semiconductor substrate 111 is transported, or the peripheral portion of the bonding layer 114 is damaged or soiled; therefore, the bottom substrate 101 and the bonding layer are not allowed in the peripheral portion. 114 are in close contact with each other. Another possible reason is that the separation of the damaged region 113 is not easily performed at the peripheral portion of the single crystal semiconductor substrate 111. Therefore, the single crystal semiconductor layer 115 having a smaller size than the single crystal semiconductor substrate 111 is bonded to the base substrate 101. Further, a convex portion is formed on the periphery of the single crystal semiconductor substrate 117, and a portion of the insulating film 112b, the insulating film 112b, and the bonding layer 114 that is not bonded to the base substrate 101 is left in the convex portion.

When heat treatment is performed, elements added by ion doping are precipitated into the micropores which are formed in the damaged region 113 as the temperature increases, and the pressure in the micropores increases. As the pressure increases, the volume of the micropores in the damaged region 113 changes, and cracks are generated in the damaged region 113; therefore, the single crystal semiconductor substrate 111 is separated along the damaged region 113. Since the bonding layer 114 is bonded to the base substrate 101, the single crystal semiconductor layer 115 separated from the single crystal semiconductor substrate 111 is fixed over the base substrate 101. The temperature of the heat treatment for separating the single crystal semiconductor layer 115 from the single crystal semiconductor substrate 111 is set at a temperature not exceeding the strain point of the bottom substrate 101.

The heat treatment can be performed using a rapid thermal annealing (RTA) device, a resistance heating furnace, or a microwave heating device. As the RTA device, a gas rapid thermal annealing (GRTA) device or a lamp rapid thermal annealing (LRTA) device can be used. Most preferably, the temperature of the underlying substrate 101 bonded to the single crystal semiconductor layer 115 is increased to a temperature ranging from 550 ° C to 650 ° C by the heat treatment.

In the case of using a GRTA device, the heating temperature may be in the range of 550 ° C to 650 ° C, and the treatment time may be in the range of 0.5 minute to 60 minutes. In the case of using a resistance heating furnace, the heating temperature may be in the range of 200 ° C to 650 ° C, and the treatment time may be in the range of 2 hours to 4 hours. In the case of using a microwave heating device, for example, the processing time may be in the range of 10 minutes to 20 minutes, and the frequency of the microwave is 2.45 GHz.

A specific treatment method using heat treatment of a shaft furnace heated by electric resistance will be described. The bottom substrate 101 (see Fig. 8A) joined to the single crystal semiconductor substrate 111 placed on the disk 10 is placed in a boat of a shaft furnace. The boat was loaded into the chamber of the shaft furnace. First, the chamber is evacuated to have a vacuum state in order to suppress oxidation of the single crystal semiconductor substrate 111. The degree of vacuum is about 5 x 10 ^-3 P _a . After the vacuum state was formed, nitrogen gas was supplied to the chamber to give the chamber a nitrogen atmosphere at atmospheric pressure. During this time, the temperature was increased to 200 °C.

After the chamber was allowed to have a nitrogen atmosphere at atmospheric pressure, it was heated at 200 ° C for 2 hours. Then, the temperature was increased to 400 ° C in 1 hour. After the state of the heating temperature of 400 ° C was stabilized, the temperature was increased to 600 ° C in one hour. After the state of the heating temperature of 600 ° C was stabilized, heat treatment was performed at 600 ° C for 2 hours. Then, the temperature was lowered to 400 ° C in one hour, and after 10 minutes to 30 minutes, the boat was taken out from the chamber. The single crystal semiconductor substrate 117 placed on the disk 10 in the boat and the bottom substrate 101 bonded to the single crystal semiconductor layer 115 are cooled in the atmosphere.

As the heat treatment using the above resistance heating furnace, heat treatment for increasing the bonding force between the bonding layer 114 and the bottom substrate 101 and heat treatment for causing separation on the damaged region 113 may be sequentially performed. In the case where the two heat treatments are performed by different means, for example, a heat treatment at a treatment temperature of 200 ° C for 2 hours in a resistance heating furnace is performed, and then the bottom substrate 101 and the single crystal semiconductor substrate bonded to each other are taken out from the furnace. 111. Then, a heat treatment at a treatment temperature of 600 ° C to 700 ° C and a treatment time of 1 minute to 30 minutes is performed with an RTA apparatus to separate the single crystal semiconductor substrate 111 from the damaged region 113.

In order to firmly bond the bonding layer 114 and the underlying substrate 101 to each other by a treatment at 700 ° C or lower, it is preferable that OH groups or water molecules are present on the surface of the bonding layer 114 or the surface of the bottom substrate (H). ₂ O). This is because the bonding layer 114 and the bottom substrate 101 start to bond to each other by forming a covalent bond (a covalent bond between the oxygen molecule and the hydrogen molecule) or a hydrogen bond by an OH group or a water molecule.

Therefore, the surfaces of the bonding layer 114 and the bottom substrate 101 are preferably activated to be hydrophilic. Further, the bonding layer 114 is preferably formed by such a method to contain oxygen or hydrogen. For example, when a hafnium oxide film, a hafnium oxynitride film, a hafnium oxynitride film, a tantalum nitride film, or the like is formed by a PECVD method at a treatment temperature of 400 ° C or lower, the film may contain hydrogen. In order to form a hafnium oxide film or a hafnium oxynitride film, for example, SiH ₄ and N ₂ O may be used as the processing gas. In order to form a hafnium oxynitride film, for example, SiH ₄ , NH ₃ and N ₂ O can be used. In order to form a tantalum nitride film, for example, SiH ₄ and NH ₃ may be used. Further, it is preferable to use a compound including an OH group such as TEOS (chemical formula: Si(OC ₂ H ₅ ) ₄ ) as a source material when formed by a PECVD method.

Here, the treatment at a heating temperature of 700 ° C or lower is referred to as low temperature treatment because the treatment is performed at a temperature equal to or lower than the allowable temperature limit of the glass substrate. Further, in contrast to the present embodiment, when the SOI substrate is formed by Smart Cut (registered trademark), heat treatment at 800 ° C or higher is performed in order to bond the single crystal germanium layer and the single crystal germanium wafer, and it is required to be on the glass substrate. Heat treatment at a temperature where the temperature limit is allowed to be high. Therefore, the treatment at a temperature of 700 ° C or lower is referred to as low temperature treatment.

When a substrate which is greatly shrunk with heating is used as the base substrate 101, heat shrinkage due to temperature rise is a problem in the manufacturing process of the semiconductor substrate 100 and the manufacturing process of the semiconductor device using the semiconductor substrate 100 in some cases. . In this case, the influence of the problem can be suppressed by heating the underlying substrate 101 before bonding the single crystal semiconductor substrate 111 to cause heat shrinkage in advance. This heat treatment can be carried out, for example, in such a manner that heating at 640 ° C is carried out in a resistance heating furnace for 4 hours, followed by cooling at a rate of 0.2 ° C / minute. Alternatively, the heat treatment can be carried out in this manner using a GRTA apparatus: heating at 650 ° C for 6 minutes is repeated 3-5 times. Note that if the bottom substrate 101 can be thermally contracted by the heat treatment of FIG. 8B to separate the single crystal semiconductor substrate 111, it is not necessary to perform heat treatment before bonding.

Here, due to the separation at the damaged region 113 and the formation of the damaged region 113, crystal defects are formed in the single crystal semiconductor layer 115 in close contact with the base substrate 101. Further, the planarity of the surface of the single crystal semiconductor layer 115 is deteriorated. In order to reduce crystal defects and improve the planarity of the surface, the single crystal semiconductor layer 115 is irradiated with the laser beam 122 as shown in Fig. 10A.

The single crystal semiconductor layer 115 is melted from the upper surface thereof by irradiation with the laser beam 122 from the side of the single crystal semiconductor layer 115. After the melting, the single crystal semiconductor layer 115 is cooled and solidified; therefore, the single crystal semiconductor layer 116 whose upper surface planarity is improved is formed as shown in Fig. 10B. The external view of Fig. 10B is Fig. 1.

In the laser beam irradiation step, since the temperature rise of the bottom substrate 101 is suppressed by using the laser beam 122, a substrate having a low heat resistance like a glass substrate can be used as the base substrate 101. Most preferably, the single crystal semiconductor layer 115 is partially melted by the irradiation of the laser beam 122. If the single crystal semiconductor layer 115 is completely melted, the recrystallization of the single crystal semiconductor layer 115 is accompanied by a disordered nucleation process of the single crystal semiconductor layer 115 in the liquid phase, and the crystallinity of the single crystal semiconductor layer 115 is lowered. The so-called longitudinal growth in which crystal growth is performed from the unmelted solid portion by partial melting is performed in the single crystal semiconductor layer 115. Due to the recrystallization of the longitudinal growth, the crystal defects of the single crystal semiconductor layer 115 are reduced, and the crystallinity thereof is recovered. Note that in the case of the laminated structure of FIG. 10A, the state in which the single crystal semiconductor layer 115 is completely melted indicates that a portion from the upper surface of the single crystal semiconductor layer 115 to the interface with the bonding layer 114 is melted and is in a liquid phase. On the other hand, the state in which the single crystal semiconductor layer 115 is partially melted indicates that the upper layer is melted and is in the liquid phase, and the lower layer is in the solid phase.

As the laser device of the laser beam 122, a laser device capable of oscillating a laser beam having an oscillation wavelength from the ultraviolet region to the visible region is selected. The laser beam 122 has a wavelength that is absorbed by the single crystal semiconductor layer 115. The wavelength can be determined by considering the skin depth of the laser beam or the like. For example, the wavelength can range from 250 nm to 700 nm. The laser device can be a continuous wave laser, a pseudo continuous wave laser, or a pulsed laser. Pulsed lasers are preferably used for partial melting. For example, in the case of a pulsed laser, the repetition rate is equal to or greater than 1 MHz, and the pulse width is equal to or greater than 10 nanoseconds and equal to or less than 500 nanoseconds. For example, a XeCl excimer laser having a repetition rate of 10 Hz to 300 Hz, a pulse width of 25 nm, and a wavelength of 308 nm can be used.

Further, the energy of the laser beam 122 can be determined in consideration of the wavelength of the laser beam 122, the skin depth of the laser beam 122, the thickness of the single crystal semiconductor substrate 111, and the like. The energy of the laser beam 122 can be, for example, in the range of 300 mJ/cm ² to 800 mJ/cm ² . For example, in the case where the thickness of the single crystal semiconductor layer 115 is about 120 nm, a pulse laser is used as the laser device, and the wavelength of the laser beam 122 is 308 nm, and the energy density of the laser beam 122 may be 600 mJ/cm. ² to 700 mJ/cm ² . Irradiation with the laser beam 122 is preferably carried out in an inert atmosphere such as a rare gas atmosphere or a nitrogen atmosphere or in a vacuum state. In order to illuminate with the laser beam 122 in an inert gas atmosphere, the laser beam 1422 can be illuminated within the sealed chamber while controlling the atmosphere within the chamber. In the case where the chamber is not used, irradiation of the laser beam 122 in an inert atmosphere can be achieved by blowing an inert gas such as nitrogen or a rare gas onto the surface irradiated with the laser beam 122.

An inert atmosphere such as nitrogen and a vacuum state have a higher effect of improving the planarity of the single crystal semiconductor layer 116 than the air atmosphere. Further, since the inert atmosphere and the vacuum state have a function of suppressing generation of cracks and wrinkles higher than the air atmosphere, the applicable energy range of the laser beam 122 is widened. With the optical system, the energy distribution of the laser beam 122 is preferably evenly distributed and the cross section of the laser beam 122 is preferably made linear. Thus, uniform illumination of the laser beam 122 can be performed with high throughput. When the beam length of the laser beam 122 is longer than one side of the base substrate 101, all of the single crystal semiconductor layer 115 bonded to the base substrate 101 can be irradiated with the laser beam 122 by scanning once. When the beam length of the laser beam 122 is shorter than one side of the base substrate 101, all of the single crystal semiconductor layer 115 bonded to the base substrate 101 can be irradiated with the laser beam 122 by scanning several times.

Note that before the single crystal semiconductor layer 115 is irradiated with the laser beam 122, a process of removing an oxide film such as a natural oxide film formed on the surface of the single crystal semiconductor layer 115 is performed. The oxide film is removed because the surface of the single crystal semiconductor layer 115 is not sufficiently planarized even if the irradiation of the laser beam 122 is performed while the oxide film remains on the surface of the single crystal semiconductor layer 115. The treatment for removing the oxide film can be performed by treating the single crystal semiconductor layer 115 with a hydrofluoric acid solution. The treatment with hydrofluoric acid is desirably performed until the surface of the single crystal semiconductor layer 115 exhibits hydrophilicity. It was confirmed by the hydrophilicity that the oxide film was removed from the single crystal semiconductor layer 115.

The step of irradiating with the laser beam 122 shown in Fig. 10A can be performed in the following manner. First, the single crystal semiconductor layer 115 was treated with a hydrofluoric acid solution diluted in a ratio of 1:100 (= hydrofluoric acid: water) for 110 seconds to remove the oxide film on the surface. As the laser device of the laser beam 122, a XeCl excimer laser (wavelength: 308 nm, pulse width: 25 nm second, repetition rate: 60 Hz) was used. With the optical system, the laser beam 122 is formed into a line shape having a cross section of 300 mm × 0.34 mm. The single crystal semiconductor layer 115 is irradiated with the laser beam 122 at a scanning speed of 2.0 mm/sec, a scanning pitch of 33 μm, and an emission number of about 10. Scanning with the laser beam 122 is performed while blowing nitrogen gas onto the illuminated surface. Since the beam length of the laser beam 122 is 300 mm, in the case where the size of the bottom substrate 101 is 730 mm × 920 mm, the irradiation area of the laser beam 122 is divided into three regions. In this way, all of the single crystal semiconductor layer 115 bonded to the base substrate 101 can be irradiated with the laser beam 122. The surface of the single crystal semiconductor layer 116 irradiated with the laser beam 122 is planarized, and the average surface roughness of the unevenness of the surface may be equal to or greater than 1 nm and equal to or less than 7 nm. Further, the root mean square roughness of the unevenness may be equal to or greater than 1 nm and equal to or less than 10 nm. Further, the maximum peak-to-valley height of the unevenness may be equal to or greater than 5 nm and equal to or less than 250 nm. That is, the irradiation treatment with the laser beam 122 can be regarded as a planarization process of the single crystal semiconductor layer 115. When the single crystal semiconductor layer 116 each having a flat surface is formed, the thickness of the gate insulating film formed on the single crystal semiconductor layer 116 can be as thin as about 5 nm to 50 nm. Therefore, a transistor having a high on-current while having a suppressed gate voltage can be formed.

Although chemical mechanical polishing (abbreviation CMP) is well known as a planarization process, in the case where a mother glass substrate is used as the base substrate 101, planarization processing on the single crystal semiconductor layer 115 by CMP is difficult. Because the mother glass substrate has a large area and distortion. Since the irradiation treatment with the laser beam 122 is performed as the planarization process in the present embodiment, the single crystal semiconductor layer 115 can be planarized without using a method of damaging the application force of the mother glass substrate, or exceeding A method of heating a mother glass substrate at a temperature that allows temperature limits. After being irradiated with the laser beam 122, the single crystal semiconductor layer 116 is preferably subjected to heat treatment at a temperature equal to or higher than 500 ° C and equal to or lower than 650 ° C. By this heat treatment, the defect in the single crystal semiconductor layer 116 that is not recovered by the irradiation of the laser beam 122 can be eliminated, and the distortion of the single crystal semiconductor layer 116 that is not recovered by the irradiation of the laser beam 122 can be alleviated. The heat treatment can be performed by a rapid thermal annealing (RTA) device, a resistance heating furnace, or a microwave heating device. As the RTA device, a gas rapid thermal annealing (GRTA) device or a lamp rapid thermal annealing (LRTA) device can be used. In the case of using a resistance heating furnace, heating at a temperature of 500 ° C can be carried out for 1 hour, and then heating at 550 ° C can be carried out for 4 hours.

By the above processing, the semiconductor substrate 100 shown in FIGS. 1 and 10B can be manufactured. In the present embodiment, in the case where a plurality of single crystal semiconductor substrates 111 are placed on the disk 10, the insulating layer 112, the damaged region 113, and the bonding layer 114 are formed. Therefore, the plurality of single crystal semiconductor substrates 111 can be collectively processed; therefore, the semiconductor substrate 100 can be formed with high yield. Note that the formation of the insulating layer 112, the damaged region 113, and the bonding layer 114 can also be performed without placing the single crystal semiconductor substrate 111 on the disk 10.

Since the bottom substrate 101 is bonded to the single crystal semiconductor substrate 111 in the case where the single crystal semiconductor substrate 111 is placed on the disk 10, the plurality of single crystal semiconductor substrates 111 can be easily bonded to the bottom substrate 101 with high throughput. Expected location.

Since the steps from FIG. 7A up to (and including) FIG. 10B can be performed at a temperature equal to or lower than 700 ° C, a glass substrate having an allowable temperature limit of 700 ° C or lower can be used as the base substrate 101. Since an inexpensive glass substrate can be used, the material cost of the semiconductor substrate 100 can be reduced. Further, since a large-sized substrate such as a mother glass substrate (500 mm × 500 mm or more, preferably 600 mm × 700 mm or more, more preferably 700 mm × 900 mm or more) can be used as the base substrate, it is available A large-sized substrate having a semiconductor film including a single crystal semiconductor layer.

The steps from FIG. 7A up to (and including) FIG. 7C are performed without moving the single crystal semiconductor substrate 111 to the other disk 10; however, in each step, the single crystal semiconductor substrate 111 can be placed in this step. In the dedicated disk 10 of the device used. For example, the disc 10 dedicated to the PECVD apparatus can be used in the forming step of the insulating layer 112, and the disc 10 dedicated to the doping apparatus can be used in the step of FIG. 7C.

Alternatively, after the forming step of the insulating layer 112 of FIG. 7A, the single crystal semiconductor substrate 111 on which the insulating layer 112 is formed may be separated from the disk 10, and the single crystal semiconductor substrate 111 may be subjected to a cleaning process such as ultrasonic cleaning. The single crystal semiconductor substrate 111 may also be placed on a different cleaning disk 10 after the cleaning process.

Still further, after the forming step of the damaged region 113 of FIG. 7B, the single crystal semiconductor substrate 111 on which the damaged region 113 is formed may be removed from the disk 10, and the single crystal semiconductor substrate 111 may be subjected to cleaning such as ultrasonic cleaning. deal with. The single crystal semiconductor substrate 111 may also be placed on a different cleaning disk 10 after the cleaning process.

Embodiment 2

In Embodiment 2, the reprocessing of the single crystal semiconductor substrate will be described. Here, a method of reprocessing the single crystal semiconductor substrate 117 shown in FIG. 8B in which the single crystal semiconductor substrate 115 is separated from the single crystal semiconductor substrate 117 will be described with reference to FIGS. 11A to 11D.

After the step of FIG. 8B, as shown in FIG. 11A, the convex portion 117a is formed at the periphery of the single crystal semiconductor substrate 117, and the portions of the insulating film 112b, the insulating film 112a, and the bonding layer 114 that are not bonded to the bottom substrate 101 are left. On the convex portion 117a.

First, an etching process for removing the insulating film 112b, the insulating film 112a, and the bonding layer 114 is performed. In the cleaning in which these films are formed using cerium oxide, cerium oxynitride or cerium oxynitride, a wet etching treatment using a hydrofluoric acid solution is performed. The single crystal semiconductor substrate 117 is obtained by this etching treatment as shown in Fig. 11B. Fig. 11C is a cross-sectional view taken along the chain line X-Y of Fig. 11B.

Next, the single crystal semiconductor substrate 117 shown in FIGS. 11B and 11C is subjected to an etching treatment to remove the convex portion 117a and the separation surface 117b which are separated from the single crystal semiconductor substrate 115. The portion surrounded by the dotted line in Fig. 11C indicates the area that should be removed by the etching process. By this etching, a region remaining on the single crystal semiconductor substrate 117 and containing excess hydrogen, such as the damaged region 113, is removed. As the etching treatment for the single crystal semiconductor substrate 117, a wet etching treatment is preferable, and as an etchant, a tetramethylammonium hydroxide (abbreviated TMAH) solution can be used.

After the convex portion 117a, the separation surface 117b, and the damaged region 113 shown in FIG. 11C are removed by etching the single crystal semiconductor substrate 117, the surface is polished; accordingly, a single crystal semiconductor having a flat surface as shown in FIG. 11D is formed. Substrate 118. This 118 can be used again as the single crystal semiconductor substrate 111 shown in FIG. 2.

As the polishing treatment, chemical mechanical polishing (abbreviation CMP) can be used. In order to make the single crystal semiconductor substrate 118 have a smooth surface, it is desirable to perform polishing of about 1 μm to 10 μm. After the polishing, since the polishing particles or the like remain on the surface of the single crystal semiconductor substrate 118, cleaning with hydrofluoric acid or RCA cleaning is performed.

By reusing the single crystal semiconductor substrate 118, the material cost of the semiconductor substrate 100 can be reduced.

Embodiment 3

As an example of a manufacturing method of a semiconductor device using the semiconductor substrate 100, a method of manufacturing a film transistor (TFT) will be described in Embodiment 3 with reference to FIGS. 12A to 12D, FIGS. 13A to 13C, and FIG. Various semiconductor devices are fabricated by combining a plurality of film transistors. In the present embodiment, the semiconductor substrate 100 manufactured by the manufacturing method of the first embodiment is used.

As shown in FIG. 12A, the single crystal semiconductor layer 116 on the base substrate 101 is subjected to an etching process (or patterning) to have a desired shape, thereby forming a semiconductor film 603 and a semiconductor film 604. The p-channel transistor is formed using the semiconductor film 603, and the n-channel transistor is formed using the semiconductor film 604.

In order to control the valve threshold voltage, a P-type impurity element such as boron, aluminum or gallium or an n-type impurity element such as phosphorus or arsenic may be added to the semiconductor film 603 and the semiconductor film 604. For example, in the case where boron is added as an impurity element imparting P-type conductivity, boron may be added at a concentration greater than or equal to 5 × 10 ¹⁶ cm ^-3 and less than or equal to 1 × 10 ¹⁷ cm ^-3 . The addition of the impurity element for controlling the valve threshold voltage can be performed on the single crystal semiconductor layer 116 or the semiconductor film 603 and the semiconductor film 604. Alternatively, the addition of an impurity element for controlling the threshold voltage may be performed on the single crystal semiconductor substrate 111. Still alternatively, the addition of the impurity element may be performed on the single crystal semiconductor substrate 111 to roughly adjust the threshold voltage, and then the addition of the impurity element may be further performed on the single crystal semiconductor layer 116 or the semiconductor film 603 and the semiconductor film 604 for the trim valve Value voltage.

As an example of a case where a weak p-type single crystal germanium substrate is used as the single crystal semiconductor substrate 111, an example of a method of adding such an impurity element will be described. First, boron is added to the entire single crystal semiconductor layer 116 before the single crystal semiconductor layer 116 is etched. The addition of this boron is aimed at adjusting the threshold voltage of the p-channel transistor. B ₂ H _{6 was} used as the doping gas, and boron was added at a concentration of 1 × 10 ¹⁶ /cm ³ to 1 × 10 ¹⁷ /cm ³ . The concentration of boron is determined in consideration of the startup rate and the like. For example, the concentration of boron may be 6 × 10 ¹⁶ /cm ³ . Next, the single crystal semiconductor layer 116 is etched to form a semiconductor film 603 and a semiconductor film 604. Then, boron is added only to the semiconductor film 604. The second addition of boron is aimed at adjusting the threshold voltage of the n-channel transistor. B ₂ H _{6 was} used as the doping gas, and boron was added at a concentration of 1 × 10 ¹⁶ /cm ³ to 1 × 10 ¹⁷ /cm ³ . For example, the concentration of boron may be 6 × 10 ¹⁶ /cm ³ .

Note that in the case where a substrate having a conductivity type or resistance suitable for a threshold voltage of a p-channel transistor or an n-channel transistor can be used as the single crystal semiconductor substrate 111, an impurity for adding a control threshold voltage is added The required number of steps of the element may be 1; at this time, an impurity element that controls the threshold voltage may be added to one of the semiconductor film 603 and the semiconductor film 604.

As shown in FIG. 12B, a gate insulating film 606 is formed to cover the semiconductor film 603 and the semiconductor film 604. The gate insulating film 606 can be formed by oxidizing or nitriding the surfaces of the semiconductor film 603 and the semiconductor film 604 with a high-density plasma. The high-density plasma treatment is carried out using, for example, a rare gas such as He, Ar, Kr or Xe and a mixed gas of oxygen, nitrogen oxide, ammonia gas, nitrogen gas, hydrogen gas or the like. In this case, when the excitation of the plasma is performed by introducing microwaves, a high-density plasma having a low electron temperature can be generated. The surface of the semiconductor film is oxidized or nitrided by an oxy group (which may include an OH group) or a nitrogen group (which may include an NH group) generated by such a high-density plasma, thereby forming an insulating film having a thickness of 1 nm to 20 nm. Preferably, the thickness is from 5 nm to 10 nm to facilitate contact with the semiconductor film. An insulating film having a thickness of 5 nm to 10 nm is used as the gate insulating film 606.

Since the oxidation or nitridation of the semiconductor film by the high-density plasma treatment is a solid phase reaction, the interface state density between the gate insulating film 606 and each of the semiconductor film 603 and the semiconductor film 604 can be greatly reduced. Further, the semiconductor film is directly oxidized or nitrided by high-density plasma treatment, so that variation in thickness of the insulating film to be formed can be suppressed. In the case where the semiconductor film has crystallinity, the surface of the semiconductor film is oxidized by a high-density plasma treatment under a solid phase reaction, and rapid oxidation only in the grain boundary can be prevented; thereby, good uniformity can be formed. And a gate insulating film with a low dielectric density. For these reasons, a part or all of the gate insulating film including the insulating film formed by the high-density plasma treatment can suppress variations in characteristics.

Alternatively, the gate insulating film 606 can be formed by thermally oxidizing the semiconductor film 603 and the semiconductor film 604. Further, the gate insulating film 606 may be formed as a single layer film or a plurality of layers including ruthenium oxide, ruthenium oxynitride, tantalum nitride, hafnium oxide, aluminum oxide, or hafnium oxide by a PECVD method, a sputtering method, or the like. A laminate of films.

After the hydrogen-containing gate insulating film 606 is formed, heat treatment may be performed at a temperature equal to or higher than 350 ° C and equal to or lower than 450 ° C, so that hydrogen contained in the gate insulating film 606 may be diffused to the semiconductor film 603 and a semiconductor film 604. In this case, the gate insulating film 606 can be formed by laminating tantalum nitride or hafnium oxynitride at a processing temperature equal to or lower than 350 ° C by a PECVD method. By supplying hydrogen to the semiconductor film 603 and the semiconductor film 604, defects in the semiconductor film 603 and the semiconductor film 604 or in the interface between the gate insulating film and the semiconductor film 603 and the semiconductor film 604 which can function as a trapping center can be effectively reduced.

Then, after a conductive film is formed on the gate insulating film 606 as shown in FIG. 12C, the conductive film is processed (patterned) into a predetermined shape, thereby forming an electrode 607 on each of the semiconductor film 603 and the semiconductor film 604. . The conductive film can be formed by a CVD method, a sputtering method, or the like. As the conductive film, tantalum (Ta), tungsten (w), titanium (Ti), molybdenum (Mo), aluminum (Al), copper (Cu), chromium (Cr), niobium (Nb), or the like can be used. Alternatively, an alloy of the above metal as its main component or a compound containing the above metal may also be used. Still alternatively, a conductive film can be formed by using a semiconductor such as polysilicon formed by adding an impurity element such as phosphorus imparting a conductivity type to a semiconductor film.

As a combination of two conductive films, tantalum nitride or tantalum (Ta) can be used as the first layer, and tungsten (W) can be used as the second layer. Further, the following combinations are exemplified: tungsten nitride and tungsten, molybdenum nitride and molybdenum, aluminum and tantalum, aluminum and titanium, and the like. Since tungsten and tantalum nitride have high heat resistance, heat treatment can be performed for heat initiation after forming two conductive films. Alternatively, as a combination of the two conductive films, for example, ruthenium and nickel telluride doped with an impurity imparting n-type conductivity, ruthenium and WSix doped with an impurity imparting n-type conductivity, or the like can be used.

Further, although each electrode 607 is composed of a single layer film in the present embodiment, the embodiment is not limited thereto. The electrode 607 can be formed by laminating a plurality of conductive films. In the case of laminating a three-layer structure of three or more conductive films, a laminated structure of a molybdenum film, an aluminum film, and a molybdenum film may be employed.

As a mask for forming the electrode 607, ruthenium oxide, ruthenium oxynitride or the like may be used instead of the resist. Although in this example, the steps of etching yttrium oxide, yttrium oxynitride, etc. are added, the film thickness and width of the mask at the time of etching are reduced less than in the case of using a resist mask; Electrode 607 of the desired width. Alternatively, the electrode 607 can be selectively formed by a droplet discharge method without using a mask.

Note that the droplet discharge method means that a droplet containing a predetermined component is ejected or ejected from a fine hole to form a predetermined pattern, and includes an inkjet method or the like.

After the conductive film is formed, the conductive film is etched by inductively coupled plasma (ICP) etching to form an electrode 607. The conductive film can be etched into a desired taper by appropriately controlling the etching conditions (for example, the amount of electric power applied to the coil electrode layer, the amount of electric power applied to the base side electrode layer, or the electrode temperature on the substrate side). . Further, the angle of the taper or the like can also be controlled by the shape of the mask. Note that as the etching gas, a chlorine-based gas such as chlorine gas, boron chloride, barium chloride or carbon tetrachloride; a fluorine-based gas such as carbon tetrafluoride, sulfur fluoride, or nitrogen fluoride; or oxygen may be used as needed; .

Next, as shown in FIG. 12D, in the case where the electrode 607 is used as a mask, an impurity element imparting one conductivity type is added to the semiconductor film 603 and the semiconductor film 604. In the present embodiment, an impurity element (for example, boron) imparting p-type conductivity is added to the semiconductor film 603, and an impurity element (for example, phosphorus or arsenic) imparting n-type conductivity is added to the semiconductor film 604. In this step, an impurity region to be a source region and a drain region is formed in the semiconductor film 603, and an impurity region serving as a high resistance region is formed in the semiconductor film 604.

Note that when an impurity element imparting p-type conductivity is added to the semiconductor film 603, the semiconductor film 604 is covered with a mask or the like so that an impurity element imparting p-type conductivity is not added to the semiconductor film 604. On the other hand, when an impurity element imparting n-type conductivity is added to the semiconductor film 604, the semiconductor film 603 is covered with a mask or the like so that an impurity element imparting n-type conductivity is not added to the semiconductor film 603. Alternatively, after an impurity element imparting one of p-type and n-type conductivity is added to the semiconductor film 603 and the semiconductor film 604, another conductivity is imparted selectively added at a higher concentration than the previously added impurity element. To one of the semiconductor film 603 and the semiconductor film 604. By the addition step of the impurity element, the p-type high concentration impurity region 608 is formed in the semiconductor film 603, and the n-type high concentration impurity region 609 is formed in the semiconductor film 604. A region of the semiconductor film 603 and the semiconductor film 604 that overlaps with the electrode 607 is a channel formation region 610 and a channel formation region 611.

Then, as shown in FIG. 13A, a side wall 612 is formed on the side of the electrode 607. For example, the sidewall 612 may be formed in such a manner that a new insulating film is formed to cover the gate insulating film 606 and the electrode 607, and the new formation is partially etched by anisotropic etching in which etching is performed mainly in the vertical direction. Insulating film. The newly formed insulating film is partially etched by the anisotropic etching described above, whereby the sidewall 612 is formed on the side surface of the electrode 607. Note that the gate insulating film 606 is also partially etched by this anisotropic etching. The insulating film for forming the sidewall 612 may be formed as a single layer or a two layer of a film including an organic material such as an organic resin or a film of ruthenium, iridium oxide, or ruthenium oxynitride by a PECVD method, a sputtering method, or the like. Or a stack of more layers. In the present embodiment, the insulating film is formed of a ruthenium oxide film having a thickness of 100 nm by a PECVD method. Further, as the etching gas of the ruthenium oxide film, a mixed gas of CHF ₃ and helium gas can be used. It is noted that the steps for forming sidewalls 612 are not limited to the steps presented herein.

As shown in FIG. 13B, an impurity element imparting n-type conductivity is added to the semiconductor film 604 by using the electrode 607 and the sidewall 612 as a mask. This step is a step for forming an impurity region serving as a source region and a drain region in the semiconductor film 604. In this step, an impurity element imparting n-type conductivity is added to the semiconductor film 604 while the semiconductor film 603 is covered with a mask or the like.

In the above addition of the impurity element, the electrode 607 and the sidewall 612 are used as a mask; therefore, a pair of n-type high-concentration impurity regions 614 are formed in the semiconductor film 604 in a self-aligned manner. Then, the mask covering the semiconductor film 603 is removed, and heat treatment is performed to activate the impurity element imparting p-type conductivity added to the semiconductor film 603 and the impurity element imparting n-type conductivity added to the semiconductor film 604. The p-channel transistor 617 and the n-channel transistor 618 are formed by the sequence of steps shown in FIGS. 12A to 13B.

In order to reduce the resistance of the source and the drain, the deuterated layer may be formed by decomposing the high-concentration impurity region 608 in the semiconductor film 603 and the high-concentration impurity region 614 in the semiconductor film 604. This deuteration is performed by placing a metal in contact with the semiconductor film 603 and the semiconductor film 604 and causing a reaction between the metal and the germanium in the semiconductor film by heat treatment; in this manner, a telluride compound is produced. As the metal, cobalt or nickel is the best, or the following may be used: titanium (Ti), tungsten (W), molybdenum (Mo), zirconium (Zr), hafnium (Hf), tantalum (Ta), vanadium (V) , niobium (Nd), chromium (Cr), platinum (Pt), palladium (Pd), and the like. In the case where the semiconductor film 603 and the semiconductor film 604 are thin, the deuteration reaction can proceed to the bottom of the semiconductor film 603 and the semiconductor film 604 in this region. As the heat treatment for forming the telluride, a resistance heating furnace, an RTA apparatus, a microwave heating apparatus, or a laser irradiation apparatus can be used.

Next, as shown in FIG. 13C, an insulating film 619 is formed to cover the transistor 617 and the transistor 618. As the insulating film 619, an insulating film containing hydrogen is formed. In this embodiment, a hafnium oxynitride film having a thickness of about 600 nm is formed by a PECVD method using methanthan, ammonia, and N ₂ O as a source gas. The insulating film 619 is made to contain hydrogen because hydrogen can be diffused from the insulating film 619 to terminate the dangling bonds in the semiconductor film 603 and the semiconductor film 604. The formation of the insulating film 619 prevents impurities such as alkali metals and alkaline earth metals from entering the transistor 617 and the transistor 618. Specifically, it is desirable to use tantalum nitride, hafnium oxynitride, aluminum nitride, aluminum oxide, cerium oxide or the like as the insulating film 619.

Next, an insulating film 620 is formed on the insulating film 619 to cover the transistor 617 and the transistor 618. An organic material having heat resistance such as polyimide, acrylic fiber, benzocyclobutene, polyamide or epoxy resin can be used as the insulating film 620. In addition to this organic material, it is also possible to use a low dielectric constant material (low-k material), a decane resin, cerium oxide, cerium nitride, cerium oxynitride, PSG (phosphorus silicate glass), BPSG (boric acid). Salt glass), alumina, etc. The decyloxyalkyl resin may include at least one of fluorine, an alkyl group, and an aryl group as a substituent and hydrogen. Alternatively, the insulating film 620 may be formed by laminating a plurality of insulating films formed of these materials. The insulating film 620 can be flattened by a CMP method or the like.

Note that the decyloxyalkyl resin corresponds to a resin including a Si-O-Si bond formed by using a fluorenylalkyl material as a raw material. The decyloxyalkyl resin may include at least one of fluorine, an alkyl group, and an aryl group as a substituent and hydrogen.

In order to form the insulating film 620, the following methods may be used depending on the material of the insulating film 620: CVD method, sputtering method, SOG method, spin coating method, dip coating method, spray coating method, droplet discharge method (for example, inkjet method, silk) Screen printing method, or offset printing method), doctor blade method, roll coating method, curtain coating method, blade coating method, and the like.

Next, heat treatment is performed for 1 hour under a nitrogen atmosphere at about 400 ° C to 450 ° C (for example, 410 ° C) to diffuse hydrogen from the insulating film 619, and the dangling bonds in the semiconductor film 603 and the semiconductor film 604 are terminated with hydrogen. Since the single crystal semiconductor layer 116 has a much lower defect density than the polycrystalline germanium film formed by the crystalline amorphous germanium film, this termination treatment with hydrogen can be performed in a short time.

Next, as shown in FIG. 14, contact holes are formed in the insulating film 619 and the insulating film 620 to partially expose the semiconductor film 603 and the semiconductor film 604. The formation of the contact holes can be performed by dry etching using a mixed gas of CHF ₃ and He; however, the present invention is not limited thereto. Then, the conductive film 621 and the conductive film 622 are formed to be in contact with the semiconductor film 603 and the semiconductor film 604 through the contact holes, respectively. The conductive film 621 is connected to the high concentration impurity region 608 of the p-channel transistor 617. The conductive film 622 is connected to the high concentration impurity region 614 of the p-channel transistor 618.

The conductive film 621 and the conductive film 622 can be formed by a CVD method, a sputtering method, or the like. Specifically, the following can be used as the conductive film 621 and the conductive film 622: aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), molybdenum (Mo), nickel (Ni), platinum (Pt) Copper (Cu), gold (Au), silver (Ag), manganese (Mn), niobium (Nd), carbon (C), antimony (Si), and the like. Alternatively, an alloy containing the above metal as its main component or a compound containing the above metal may also be used. The conductive film 621 and the conductive film 622 may be composed of a single layer or a plurality of layers of a film formed using the above metal.

As an example of an alloy containing aluminum as its main component, an alloy containing aluminum as its main component and also containing nickel is exemplified. Further, an alloy containing aluminum as its main component and containing nickel and one or both of carbon and niobium may also be mentioned. Since aluminum and aluminum bismuth alloys have low resistance values and are inexpensive, aluminum and aluminum bismuth alloys are suitable as materials for forming the conductive film 621 and the conductive film 622. In particular, when the shape of the aluminum-bismuth (Al-Si) film is treated by etching, hillocks can be prevented from being formed at the time of baking of the resist for forming an etching mask, compared to the case of using an aluminum film. Instead of bismuth (Si), Cu may be mixed into the aluminum film at about 0.5%.

For example, a laminate structure including a barrier film, an aluminum-iridium (Al-Si) film and a barrier film or a laminate structure including a barrier film, an aluminum-iridium (Al-si) film, a titanium nitride film, and a barrier film can be used as The conductive film 621 and the conductive film 622. Note that the barrier film refers to a film formed using titanium, titanium nitride, molybdenum, or molybdenum nitride. When the barrier layer is formed to sandwich the aluminum-bismuth (Al-Si) film, the formation of hillocks of aluminum or aluminum-bismuth alloy can be more effectively prevented. Further, when a barrier film is formed using titanium as a highly reducible element, even if a thin oxide film is formed on the semiconductor film 603 and the semiconductor film 604, the oxide film can be reduced by the titanium contained in the barrier film, thereby The best contact between the conductive films 621 and 622 and the semiconductor films 603 and 604 can be obtained. Further, it is also possible to laminate a plurality of barrier films. In this case, for example, a five-layer structure in which titanium, titanium nitride, aluminum-niobium alloy, titanium, and titanium nitride are laminated from the lowermost layer can be used as the conductive films 621 and 622.

For the conductive films 621 and 622, tungsten germanium formed by a chemical vapor deposition method using WF ₆ gas and SiH ₄ gas can be used. Alternatively, tungsten formed by hydrogen reduction of WF ₆ can be used as the conductive films 621 and 622.

In FIG. 14, a top view of the p-channel transistor 617 and the n-channel transistor 618 and a cross-sectional view taken along line A-B of the top view are shown. Note that the conductive film 621, the conductive film 622, the insulating film 619, and the insulating film 620 are omitted in the plan view of FIG.

Although the case where the n-channel transistor 617 and the p-channel transistor 618 each have one electrode 607 serving as a gate is described in the present embodiment, the present invention is not limited to this structure. The transistor fabricated in the present invention may have a multi-gate structure including a plurality of electrodes serving as gates and electrically connected to each other.

Further, the transistor included in the semiconductor device manufactured in the present invention may have a gate plane structure.

Note that since the semiconductor layer included in the substrate provided with the semiconductor film of the present invention is a dicing layer of the single crystal semiconductor substrate, the orientation does not change. Therefore, variations in electrical characteristics such as threshold voltage and mobility of a plurality of transistors fabricated using a semiconductor substrate can be made small. Further, since there is substantially no grain boundary, leakage current due to grain boundaries can be suppressed, and energy saving of the semiconductor device can be realized. Therefore, a highly reliable semiconductor device can be manufactured.

In the case of manufacturing a transistor made of a polycrystalline semiconductor film obtained by laser crystallization, it is necessary to consider the scanning direction of the laser to determine the layout of the semiconductor film of the transistor in order to obtain high mobility. However, there is no such need for the substrate provided with the semiconductor film of the present invention, and there is almost no limitation in designing the semiconductor device.

Embodiment 4

In Embodiment 3, a method of manufacturing a TFT is described as an example of a method of manufacturing a semiconductor device. A high added value semiconductor device can be manufactured by forming various semiconductor elements such as capacitors, resistors, and the like together with a TFT on a substrate provided with a semiconductor film. In the present embodiment, a specific amount of the semiconductor device is described with reference to the drawings.

First, as an example of a semiconductor device, a microprocessor will be described. FIG. 15 is a block diagram showing a structural example of the microprocessor 200.

The microprocessor 200 includes an arithmetic logic unit (ALU) 201, an ALU controller 202, an instruction decoder 203, an interrupt controller 204, a timing controller 205, a register 206, a register controller 207, and a bus interface ( Bus I/F) 208, read only memory (ROM) 209, and memory interface 210.

The instructions input to the microprocessor 200 via the bus interface 208 are input to the instruction decoder 203 and decoded, and then input to the ALU controller 202, the interrupt controller 204, the register controller 207, and the timing controller 205. The ALU controller 202, the interrupt controller 204, the scratchpad controller 207, and the timing controller 205 perform various controls based on the decoded instructions.

The ALU controller 202 generates signals for controlling the operation of the ALU 201. The interrupt controller 204 is a circuit that processes an interrupt request from an external input/output device or peripheral circuit during execution of the program of the microprocessor 200, and the interrupt controller 204 determines the priority order or mask state of the interrupt request, and processes the Interrupt the request. The scratchpad controller 207 generates the address of the scratchpad 206 and performs read and write to the scratchpad 206 depending on the state of the microprocessor 200. The timing controller 205 generates a signal that controls the timing of the operation of the ALU 201, the ALU controller 202, the instruction decoder 203, the interrupt controller 204, and the scratchpad controller 207. For example, the timing controller 205 is provided with an internal clock generator that generates an internal clock signal CLK2 based on the reference clock signal CLK1. As shown in FIG. 15, the internal clock signal CLK2 is input to another circuit.

Next, an example of a semiconductor device provided with a function of performing transceiving of data and an arithmetic function without contact may be described. Fig. 16 is a block diagram showing a structural example of such a semiconductor device. The semiconductor device 211 shown in Fig. 16 is used as an arithmetic processing unit which operates by transmitting and receiving signals with an external device by wireless communication.

As shown in FIG. 16, the semiconductor device 211 includes an analog circuit portion 212 and a digital circuit portion 213. The analog circuit portion 212 includes a resonance circuit 214 having a resonance capacitor, a rectifier circuit 215, a constant voltage circuit 216, a reset circuit 217, an oscillation circuit 218, a demodulation circuit 219, and a modulation circuit 220. In addition, the digital circuit portion 213 includes an RF interface 221, a control register 222, a clock controller 223, an interface 224, a central processing unit (CPU) 225, a random access memory (RAM) 226, and a read-only memory (ROM). 227.

The outline of the operation of the semiconductor device 211 is as follows. The induced electromotive force is generated in the resonant circuit 214 using the signal received by the antenna 228. The induced electromotive force is supplied to the capacitor 229 by the rectifying circuit 215. The capacitor 229 is preferably a capacitor such as a ceramic capacitor or a galvanic layer capacitor. The capacitor 229 does not necessarily need to be integrated with the substrate included in the semiconductor device 211, and it can be mounted to the semiconductor device 211 as a different component.

The reset circuit 217 generates a signal for resetting and initializing the digital circuit portion 213. For example, a signal that rises hysteresis after the power supply voltage rises is generated as a reset signal. The oscillation circuit 218 changes the frequency and duty ratio of the clock signal depending on the control signal generated in the constant voltage circuit 216. The demodulation circuit 219 is a circuit that demodulates the received signal, and the modulation circuit 220 is a circuit that modulates the data to be transmitted.

For example, the demodulation circuit 219 is formed using a low pass filter and binarizes the amplitude modulated (ASK) received signal based on the change in amplitude. Since the modulation circuit 220 changes the amplitude of the amplitude modulated (ASK) transmission signal and transmits the data, the modulation circuit 220 changes the amplitude of the communication signal by changing the resonance point of the resonance circuit 214.

Depending on the supply voltage or current consumption in the CPU 225, the clock controller 223 generates a control signal for varying the frequency and duty cycle of the clock signal. Monitoring of the power supply voltage is performed in the power management circuit 230.

The signal input from the antenna 228 to the semiconductor device 211 is demodulated in the demodulation circuit 219, and then divided into control commands, data, and the like in the RF interface 221. This control command is stored in control register 222. The control commands include instructions for reading data stored in the ROM 227, writing data to the RAM 226, performing arithmetic operations in the CPU 225, and the like.

The CPU 225 accesses the ROM 227, the RAM 226, and the control register 222 via the interface 224. The interface 224 has a function of generating an access signal corresponding to any one of the ROM 227, the RAM 226, and the control register 222 based on the address requested by the CPU 225.

As the arithmetic method of the CPU 225, a method in which the operating system (OS) is stored in the ROM 227 and the program is read and executed at the start of operation can be employed. Alternatively, a method may be employed in which a dedicated circuit is set as an arithmetic circuit and an arithmetic process is executed using hardware. In a method using both hardware and software, a part of the arithmetic process is executed in a dedicated arithmetic circuit, and then the rest of the arithmetic process is executed using a program in the CPU 225.

Next, a display device will be described as a structural example of a semiconductor device with reference to FIGS. 17, 18A and 18B, and FIGS. 19A and 19B.

17 is a diagram showing a main part of a semiconductor device 100 manufactured according to the manufacturing method in Embodiment 1. From a single semiconductor substrate 100, a plurality of display panels each included in a display device can be fabricated. In Fig. 17, an example of a circuit configuration for manufacturing a display device from one single crystal semiconductor layer 116 is shown. For each of the single crystal semiconductor layers 116, a display panel forming region 300 is formed. In the display device, a scan line driver circuit, a signal line driver circuit, and a pixel portion are included. Therefore, each of the display panel forming regions 300 has a plurality of regions (scanning line driver circuit forming region 301, signal line driver circuit forming region 302, and pixel forming region 303) in which they are formed.

18A and 18B are diagrams showing a structural example of a liquid crystal display device. 18A is a plan view of a pixel of the liquid crystal display device, and FIG. 18B is a cross-sectional view along the line JK of FIG. 18A; in FIG. 18A, the semiconductor layer 311 is a layer formed from the single crystal semiconductor layer 116, and is formed. Pixel's TFT 325. The pixel includes a semiconductor layer 311, a scanning line 322 crossing the semiconductor layer 311, a signal line 323 crossing the scanning line 322, a pixel electrode 324, and an electrode 328 electrically connected to the pixel electrode 324 and the semiconductor layer 311.

As shown in FIG. 18B, a bonding layer 114, an insulating layer 112 including an insulating film 112b and an insulating film 112a, and a semiconductor layer 311 are laminated on the substrate 310. The substrate 310 is a separated bottom substrate 101. The semiconductor layer 311 is a layer formed by separating the single crystal semiconductor layer 116 by an etching unit. In the semiconductor layer 311, a channel formation region 312 and an n-type impurity region 313 are formed. The gate electrode of the TFT 325 is included in the scan line 322, and one of the source electrode and the drain electrode is included in the signal line 323.

Above the interlayer insulating film 327, a signal line 323, a pixel electrode 324, and an electrode 328 are provided. A cylindrical spacer 329 is formed over the interlayer insulating film 327, and an alignment film 330 is formed to cover the signal line 323, the pixel electrode 324, the electrode 328, and the cylindrical spacer 329. On the opposite substrate 332, an opposite electrode 333 and an alignment film 330 covering the opposite electrode are formed. A cylindrical spacer 329 is formed to maintain a space between the substrate 310 and the opposite substrate 332. In the space formed by the cylindrical spacer 329, a liquid crystal layer 335 is formed. On the connection portion of the signal line 323 and the electrode 328 having the impurity region 313, since there are steps formed in the interlayer insulating film 327 due to the formation of the contact hole, the orientation of the liquid crystal of the liquid crystal layer 335 in these connection portions is liable to become unnecessary. sequence. Therefore, the cylindrical spacer 329 is formed at these step portions to prevent the orientation disorder of the liquid crystal.

Next, an electroluminescence display device (hereinafter referred to as "EL display device") will be described. 19A and 19B are diagrams for describing an EL display device manufactured according to the method of Embodiment 2. 19A is a plan view of a pixel of an EL display device, and FIG. 19B is a cross-sectional view of the pixel. As shown in FIG. 19A, the pixel includes a selection transistor 401 made of a TFT, a display control transistor 402, a scanning line 405, a signal line 406, a power supply line 407, and a pixel electrode 408. Each of the pixels is provided with a light-emitting element having a structure in which a layer (EL layer) containing an electroluminescent material formed is sandwiched between a pair of electrodes. One of the electrodes of the light-emitting element is a pixel electrode 408.

The selection transistor 401 is an n-channel TFT and includes a semiconductor layer 403 made of a single crystal semiconductor layer 116. In the selection transistor 401, a gate electrode is included in the scanning line 405, one of the source electrode and the germanium electrode is included in the signal line 406, and the other of the source electrode and the germanium electrode is formed as the electrode 411. In the display control transistor 402, the gate electrode 412 is electrically connected to the electrode 411, and one of the source electrode and the germanium electrode is formed to be electrically connected to the electrode 413 of the pixel electrode 408, and the other of the source electrode and the germanium electrode It is included in the power line 407.

The display transistor 402 is a p-channel TFT and includes a semiconductor layer 404 made of a single crystal semiconductor layer 116. As shown in FIG. 19B, in the semiconductor layer 404, a channel formation region 451 and a P-type impurity region 452 are formed. The interlayer insulating film 427 is formed to cover the gate electrode 412 of the display control transistor 402. On the interlayer insulating film 427, a signal line 406, a power source line 407, electrodes 411 and 413, and the like are formed. Further, over the interlayer insulating film 427, a pixel electrode 408 electrically connected to the electrode 413 is formed. The peripheral portion of the pixel electrode 408 is surrounded by an insulating spacer layer 428. The EL layer 429 is formed on the electrode 408, and the opposite electrode 430 is formed on the EL layer 429. The opposite substrate 431 is provided as a reinforcing plate, and is fixed to the substrate 400 with a resin layer 432 with respect to the substrate 431. The substrate 400 is a separated bottom substrate 101.

Note that in the semiconductor substrate 100 of FIG. 17, the semiconductor device described with reference to FIG. 15 or FIG. 16 may be formed in the display panel forming region 300. That is, the computer function can be set in the display device. In addition, a display device capable of input/output date without contact can be manufactured.

Therefore, various electrical devices can be fabricated using the semiconductor substrate 100. Electrical equipment includes: cameras such as cameras and digital cameras; navigation systems, sound reproduction systems (car audio systems, audio components, etc.), computers, game consoles; mobile information terminals (mobile computers, mobile phones, mobile games, e-books) And the like, such as a display device that displays image data of an image reproducing device (specifically, a digital versatile disk (DVD)) provided with a recording medium.

A specific embodiment of an electrical device is described with reference to Figures 20A through 20C. FIG. 20 is an external view showing the mobile phone 901. The mobile phone 901 has a structure in which a display portion 902, an operation switch 903, and the like are included. By applying the liquid crystal display device shown in FIGS. 18A and 18B or the EL display device shown in FIGS. 19A and 19B to the display portion 902, the display portion 902 can have superior image quality with almost no display unevenness.

FIG. 20B is an external view showing a structural example of the digital player 911. The digital player 911 includes a display portion 912, an operation portion 913, a headphone 914, and the like. Alternatively, a headset or a wireless headset can be used instead of the headset 914. By applying the liquid crystal display device shown in Figs. 18A and 18B or the EL display device shown in Figs. 19A and 19B to the display portion 912, it can be displayed even in the case where the screen size is about 0.3 inch to 2 inches. High-precision images and a lot of text information.

FIG. 20C is an external view of the electronic book 921. The electronic book 921 includes a display portion 922 and an operation switch 923. The data machine can be incorporated into the electronic book 921, or the semiconductor device of FIG. 16 can be combined such that the electronic book 921 has a structure by which information can be wirelessly transmitted and received. By applying the liquid crystal display device shown in Figs. 18A and 18B or the EL display device shown in Figs. 19A and 19B to the display portion 922, display of high image quality can be performed.

Embodiment 5

In the present embodiment, a disk for manufacturing a substrate provided with a semiconductor film is described. The disk 10 of Figure 3 has a plurality of recesses 11, each for storing a single crystal semiconductor substrate. Alternatively, the substrate provided with the semiconductor film can be fabricated by placing a plurality of single crystal semiconductor substrates into one recess of the disk.

An example of a disk having such a structure is shown in FIG. The disk 20 is a plate-like member formed of a material similar to the material of the disk 10. A recess 21 for fixing the single crystal semiconductor substrate 111 is formed. The recess 21 has a shape in which a plurality of single crystal semiconductor substrates 111 can be arranged without a space therebetween. On the disk 20 of, for example, Fig. 21, the concave portion 11 in the case where the 3 × 3 array of the single crystal semiconductor substrate 111 is shown as one block is shown.

The present application is based on Japanese Patent Application Serial No. 2007-245898, filed on

10. . . plate

11. . . Concave

20. . . plate

twenty one. . . Concave

100. . . Base

101. . . Bottom base

102. . . Insulation

111. . . Single crystal semiconductor substrate

112. . . Insulation

112a. . . Insulating film

112b. . . Insulating film

113. . . Damaged area

114. . . Bonding layer

115. . . Single crystal semiconductor layer

116. . . Single crystal semiconductor layer

117. . . Single crystal semiconductor substrate

117a. . . Convex

117b. . . Separation surface

118. . . Single crystal semiconductor substrate

121. . . Ion beam

122. . . Laser beam

200. . . microprocessor

201. . . Arithmetic logic unit

202. . . ALU controller

203. . . Instruction decoder

204. . . Interrupt controller

205. . . Timing controller

206. . . Register

207. . . Register controller

208. . . Bus interface

209. . . Read only memory

210. . . Memory interface

211. . . Semiconductor device

212. . . Analog circuit part

213. . . Digital circuit part

214. . . Resonant circuit

215. . . Rectifier circuit

216. . . Constant voltage circuit

217. . . Reset circuit

218. . . Oscillation circuit

219. . . Demodulation circuit

220. . . Modulation circuit

221. . . RF interface

222. . . Control register

223. . . Clock controller

224. . . interface

225. . . Central processing unit

226. . . Random access memory

227. . . Read only memory

228. . . antenna

229. . . Capacitor

230. . . Power management circuit

300. . . Display panel forming area

301. . . Scan line driver circuit forming region

302. . . Signal line driver circuit forming region

303. . . Pixel forming region

310. . . Base

311. . . Semiconductor layer

312. . . Channel formation region

313. . . N-type impurity region

322. . . Scanning line

323. . . Signal line

324. . . Photoelectrode

325. . . TFT

327. . . Interlayer insulating film

328. . . electrode

329. . . Cylindrical septum

330. . . Oriented film

332. . . Relative base

333. . . Relative electrode

335. . . Liquid crystal layer

400. . . Base

401. . . Select transistor

402. . . Display control transistor

403. . . Semiconductor layer

404. . . Semiconductor layer

405. . . Scanning line

406. . . Signal line

407. . . power cable

408. . . Photoelectrode

411. . . electrode

412. . . Gate electrode

413. . . electrode

427. . . Interlayer insulating film

428. . . Insulating partition

429. . . EL layer

430. . . Relative electrode

430. . . Relative base

432. . . Resin layer

451. . . Channel formation region

452. . . P-type impurity region

603. . . Semiconductor film

604. . . Semiconductor film

606. . . Gate insulating film

607. . . electrode

608. . . P-type high concentration impurity region

609. . . N-type high concentration impurity region

610. . . Channel formation region

611. . . Channel formation region

612. . . Side wall

614. . . N-type high concentration impurity region

617. . . P-channel transistor

618. . . N-channel transistor

619. . . Insulating film

620. . . Insulating film

621. . . Conductive film

622. . . Conductive film

901. . . mobile phone

902. . . Display section

903. . . Operation switch

911. . . Digital player

912. . . Display section

913. . . Operation part

914. . . headset

921. . . E-book

922. . . Display section

923. . . Operation switch

In the drawing:

1 is an external view showing one example of a structure of a substrate provided with a semiconductor film;

2 is an external view showing one example of a structure of a single crystal semiconductor film substrate;

3 is an external view showing one example of a structure of a disk;

4 is an external view showing a plurality of single crystal semiconductor substrates disposed on a disk;

5A and 5B are each a plan view showing a structural example of a disk;

6A and 6B are each a plan view showing a structural example of a disk;

7A-7D are cross-sectional views showing a method of fabricating a substrate provided with a semiconductor film;

8A and 8B are cross-sectional views showing a method of manufacturing a substrate provided with a semiconductor film;

9 is a cross-sectional view showing a method of manufacturing a substrate provided with a semiconductor film;

10A and 10B are cross-sectional views showing a method of manufacturing a substrate provided with a semiconductor film;

11A-11D are diagrams illustrating a reworking process of a single crystal semiconductor substrate;

12A-12D are cross-sectional views illustrating a method of fabricating a semiconductor device;

13A-13C are cross-sectional views illustrating a method of fabricating a semiconductor device;

Figure 14 is a cross-sectional view and a plan view of a semiconductor device;

Figure 15 is a block diagram showing one example of the structure of a microprocessor;

16 is a block diagram showing one example of a structure of a semiconductor device;

Figure 17 is a perspective view showing a main portion of a substrate provided with a semiconductor film;

18A is a plan view of a pixel of the liquid crystal display device, and FIG. 18B is a cross-sectional view taken along a line J-K of FIG. 18A;

Figure 19A is a plan view of a pixel of the electroluminescence display device, and Figure 19B is a cross-sectional view of Figure 19A;

20A-20C are perspective views of a mobile phone, a digital player, and an e-book, respectively;

21 is a perspective view showing one example of the structure of a disk.

10. . . plate

101. . . Bottom base

111. . . Single crystal semiconductor substrate

112. . . Insulation

112a. . . Insulating film

112b. . . Insulating film

113. . . Damaged area

114. . . Bonding layer

115. . . Single crystal semiconductor layer

117. . . Single crystal semiconductor substrate

Claims (25)

A method of fabricating a substrate provided with a semiconductor film, comprising: preparing a bottom substrate and a plurality of single crystal semiconductor substrates, the single crystal semiconductor substrate including a damaged region formed at a desired depth in each of the single crystal semiconductor substrates And a bonding layer formed on an upper surface of each of said single crystal semiconductor substrates; arranging said plurality of single crystal semiconductor substrates on a disk; and said plurality of single crystal semiconductor substrates disposed on said disk The bottom substrate is in close contact with the bonding layer interposed therebetween to bond one surface of the bonding layer and one surface of the bottom substrate, thereby bonding the bottom substrate and the plurality of single crystal semiconductor substrates to each other And generating a crack in the damaged region by heating the plurality of single crystal semiconductor substrates placed on the disk, thereby separating a plurality of single crystal semiconductor layers separated from the single crystal semiconductor substrate The bottom substrate is in intimate contact. A method of manufacturing a substrate provided with a semiconductor film according to the first aspect of the invention, wherein the bonding layer is formed on an insulating layer formed in contact with the single crystal semiconductor substrate. A method of manufacturing a substrate provided with a semiconductor film according to the first aspect of the invention, wherein the plurality of single crystal semiconductor layers in close contact with the bottom substrate are irradiated with a laser beam. A method of manufacturing a substrate provided with a semiconductor film according to the first aspect of the invention, wherein the bottom substrate is a glass substrate. A method of fabricating a substrate provided with a semiconductor film, comprising: preparing a bottom substrate and a plurality of single crystal semiconductor substrates, the single crystal semiconductor The bulk substrate includes a damaged region formed at a desired depth in each of the single crystal semiconductor substrates, and an insulating layer formed on an upper surface of each of the single crystal semiconductor substrates, and formed on the insulating layer a bonding layer; arranging the plurality of single crystal semiconductor substrates on a first disk; bringing the plurality of single crystal semiconductor substrates placed on the first disk into close contact with the bottom substrate with the a bonding layer to bond one surface of the bonding layer and one surface of the bottom substrate such that the bottom substrate and the plurality of single crystal semiconductor substrates are bonded to each other; and by heating the plurality of sheets The crystalline semiconductor substrate generates a crack in the damaged region such that a plurality of single crystal semiconductor layers separated from the single crystal semiconductor substrate are in close contact with the bottom substrate, wherein the step of forming the insulating layer includes the single crystal Forming a single layer or two or more layers on the semiconductor substrate while the plurality of single crystal semiconductor substrates are placed on the second disk, wherein the step of forming the damaged region includes exciting Gas generating plasma and irradiating the single crystal semiconductor substrate with an ion species included in the plasma to form the damaged region in the single crystal semiconductor substrate while the plurality of single crystal semiconductor substrates are placed a third disk; wherein the forming step of the bonding layer comprises forming the bonding layer on the single crystal semiconductor substrate with the insulating layer interposed therebetween, and the insulating layer and the damaged region formed therein Each of the plurality of single crystal semiconductor substrates is placed on a fourth disk; wherein the same or different disks are used as the second disk, the third disk, and The fourth disk; and wherein the same or different disks are used as the first disk and the fourth disk. A method of manufacturing a substrate provided with a semiconductor film according to the fifth aspect of the invention, wherein the plurality of single crystal semiconductor layers in close contact with the base substrate are irradiated with a laser beam. A method of manufacturing a substrate provided with a semiconductor film according to the fifth aspect of the invention, wherein the bottom substrate is a glass substrate. A method of fabricating a substrate provided with a semiconductor film, comprising: preparing a bottom substrate and a plurality of single crystal semiconductor substrates, the single crystal semiconductor substrate including a damaged region formed at a desired depth in each of the single crystal semiconductor substrates And an insulating layer formed on an upper surface of each of the single crystal semiconductor substrates, and a bonding layer formed on the insulating layer; the plurality of single crystal semiconductor substrates are disposed on the first disk; The plurality of single crystal semiconductor substrates on the first disk are in close contact with the bottom substrate with the bonding layer interposed therebetween to bond one surface of the bonding layer and one surface of the bottom substrate, thereby Bonding the bottom substrate and the plurality of single crystal semiconductor substrates to each other; and generating a crack in the damaged region by heating the plurality of single crystal semiconductor substrates, thereby causing the single crystal semiconductor substrate a plurality of separate single crystal semiconductor layers in close contact with the bottom substrate, wherein the step of forming the insulating layer includes forming a single layer on the plurality of single crystal semiconductor substrates Two or more layers, while the plurality of single crystal semiconductor substrate is placed on the second disc, Wherein the forming step of the bonding layer includes forming the bonding layer on the plurality of single crystal semiconductor substrates with the insulating layer interposed therebetween, and simultaneously forming the plurality of single crystal semiconductor substrates in which the insulating layer is formed Placed on the third disk; wherein the forming of the damaged region includes generating plasma by exciting the source gas and illuminating the plurality of single crystal semiconductor substrates with ion species included in the plasma Forming the damaged region in a plurality of single crystal semiconductor substrates while the plurality of single crystal semiconductor substrates on which the insulating layer and the bonding layer are formed are placed on a third disk; wherein the same or different disks are Used as the second disk, the third disk; and wherein the same or different disks are used as the first disk. A method of manufacturing a substrate provided with a semiconductor film according to the eighth aspect of the invention, wherein the plurality of single crystal semiconductor layers in close contact with the base substrate are irradiated with a laser beam. A method of manufacturing a substrate provided with a semiconductor film according to the eighth aspect of the invention, wherein the bottom substrate is a glass substrate. A method of fabricating a substrate provided with a semiconductor film, comprising: preparing a bottom substrate and a plurality of single crystal semiconductor substrates, the single crystal semiconductor substrate including a damaged region formed at a desired depth in each of the single crystal semiconductor substrates And an insulating layer formed on an upper surface of each of the single crystal semiconductor substrates, and a bonding layer formed on the insulating layer; the plurality of single crystal semiconductor substrates are disposed on the first disk; The plurality of single crystal semiconductor substrates on the first disk The bottom substrate is in intimate contact with the bonding layer interposed therebetween to bond one surface of the bonding layer and one surface of the bottom substrate, thereby bonding the bottom substrate and the plurality of single crystal semiconductor substrates to each other And generating a crack in the damaged region by heating the plurality of single crystal semiconductor substrates, thereby bringing a plurality of single crystal semiconductor layers separated from the single crystal semiconductor substrate into close contact with the bottom substrate, wherein The step of forming the damaged region includes forming a plasma in the excitation source gas and doping the single crystal semiconductor substrate with an ion species included in the plasma to form the plurality of single crystal semiconductor substrates The damaged region while the plurality of single crystal semiconductor substrates are placed on the second disk; wherein the forming of the insulating layer comprises forming a single layer or two or more on the plurality of single crystal semiconductor substrates a layer, wherein each of the plurality of single crystal semiconductor substrates in which the damaged region is formed is placed on a third disk, wherein the step of forming the bonding layer includes the plurality of single crystals Forming the bonding layer on the bulk substrate with the insulating layer interposed therebetween, and each of the plurality of single crystal semiconductor substrates in which the damaged region and the insulating layer are formed are placed on the fourth disk; The same or different discs are used as the second disc, the third disc, and the fourth disc; and wherein the same or different discs are used as the first disc and the fourth disc. A method of manufacturing a substrate provided with a semiconductor film according to claim 11, wherein the laser beam is irradiated with the bottom substrate The plurality of single crystal semiconductor layers in close contact. A method of manufacturing a substrate provided with a semiconductor film according to the invention of claim 11, wherein the bottom substrate is a glass substrate. A method of fabricating a substrate provided with a semiconductor film, comprising: preparing a bottom substrate and a plurality of single crystal semiconductor substrates, the single crystal semiconductor substrate including a damaged region formed at a desired depth in each of the single crystal semiconductor substrates And an insulating layer formed on an upper surface of each of the single crystal semiconductor substrates, and a bonding layer formed on the insulating layer; the plurality of single crystal semiconductor substrates are disposed on the first disk; The plurality of single crystal semiconductor substrates on the first disk are in close contact with the bottom substrate with the bonding layer interposed therebetween to bond one surface of the bonding layer and one surface of the bottom substrate, thereby Bonding the bottom substrate and the plurality of single crystal semiconductor substrates to each other; and generating cracks in the damaged region by heating the plurality of single crystal semiconductor substrates, and the plurality of single crystal semiconductor substrates And disposed on the first disk such that a plurality of first single crystal semiconductor layers separated from the single crystal semiconductor substrate are in close contact with the bottom substrate, wherein the insulating layer The step of introducing a process gas into the reaction chamber by introducing the plurality of single crystal semiconductor substrates placed on the second disk in a reaction chamber containing a fluoride gas or a fluorine gas, by exciting the process gas to generate a plasma, and a chemical reaction that initiates an active species included in the plasma to form a single layer or two or more layers on the plurality of single crystal semiconductor substrates, and Where the same or different discs are used as the first disc and the second disc. A method of manufacturing a substrate provided with a semiconductor film according to claim 14, wherein the plurality of single crystal semiconductor layers in close contact with the base substrate are irradiated with a laser beam. A method of manufacturing a substrate provided with a semiconductor film according to claim 14, wherein the bottom substrate is a glass substrate. A method of fabricating a substrate provided with a semiconductor film, comprising: preparing a bottom substrate and a plurality of single crystal semiconductor substrates, the single crystal semiconductor substrate including a damaged region formed at a desired depth in each of the single crystal semiconductor substrates And an insulating layer formed on an upper surface of each of the single crystal semiconductor substrates, and a bonding layer formed on the insulating layer; the plurality of single crystal semiconductor substrates are disposed on the first disk; The plurality of single crystal semiconductor substrates on the first disk are in close contact with the bottom substrate with the bonding layer interposed therebetween to bond one surface of the bonding layer and one surface of the bottom substrate, thereby Bonding the bottom substrate and the plurality of single crystal semiconductor substrates to each other; and generating a crack in the damaged region by heating the plurality of single crystal semiconductor substrates, thereby causing the single crystal semiconductor substrate a plurality of separate first single crystal semiconductor layers in close contact with the bottom substrate, wherein the step of forming the insulating layer comprises reacting by a fluoride gas or fluorine gas Providing a plurality of single crystal semiconductor substrate is placed on the second disc, the process gas is introduced into the reaction chamber, the processing gas to generate excited by plasma, and the plasma initiated within chemically active species include Reacting to form a single layer or two or more layers on the plurality of single crystal semiconductor substrates, and wherein the step of forming the damaged region comprises generating a plasma by exciting a source gas and using the plasma The included ion species illuminate the single crystal semiconductor substrate to form the damaged region in the plurality of single crystal semiconductor substrates while the plurality of single crystal semiconductor substrates on which the insulating layer is formed are placed a third disk; wherein the forming step of the bonding layer comprises forming the bonding layer on the plurality of single crystal semiconductor substrates with the insulating layer interposed therebetween, and wherein the damaged region and the Each of the plurality of single crystal semiconductor substrates of the insulating layer is placed on a fourth disk; wherein the same or different disks are used as the second disk, the third disk, and the fourth disk; and wherein the same or Different disks are used as the first disk and the fourth disk. A method of manufacturing a substrate provided with a semiconductor film according to claim 17, wherein the plurality of single crystal semiconductor layers in close contact with the base substrate are irradiated with a laser beam. A method of manufacturing a substrate provided with a semiconductor film according to claim 17, wherein the bottom substrate is a glass substrate. A method of fabricating a substrate provided with a semiconductor film, comprising: preparing a bottom substrate and a plurality of single crystal semiconductor substrates, the single crystal semiconductor substrate including a damaged region formed at a desired depth in each of the single crystal semiconductor substrates And an insulating layer formed on an upper surface of each of the single crystal semiconductor substrates, and a bonding layer formed on the insulating layer; Arranging the plurality of single crystal semiconductor substrates on a first disk; bringing the plurality of single crystal semiconductor substrates placed on the first disk into close contact with the bottom substrate with the bonding layer interposed therebetween Bonding one surface of the bonding layer and one surface of the bottom substrate such that the bottom substrate and the plurality of single crystal semiconductor substrates are bonded to each other; and by heating the plurality of single crystal semiconductor substrates Forming a crack in the damaged region such that a plurality of first single crystal semiconductor layers separated from the single crystal semiconductor substrate are in close contact with the bottom substrate, wherein the step of forming the insulating layer includes a reaction chamber of a compound gas or a fluorine gas, the plurality of single crystal semiconductor substrates placed on the second tray, a process gas introduced into the reaction chamber, a plasma generated by exciting the processing gas, and the electricity being induced a chemical reaction of an active species included in the slurry to form a single layer or two or more layers on the plurality of single crystal semiconductor substrates, and wherein the forming step of the bonding layer is included in the plurality of sheets Forming the bonding layer on the semiconductor substrate with the insulating layer interposed therebetween, while the plurality of single crystal semiconductor substrates on which the insulating layer is formed are placed on the third disk; wherein the damaged region is formed The step includes forming the damaged region in the plurality of single crystal semiconductor substrates by generating a plasma by exciting a source gas and irradiating the single crystal semiconductor substrate with an ion species included in the plasma, and simultaneously thereon The plurality of single crystal semiconductor substrates formed with the insulating layer and the bonding layer are placed on a third disk; Where the same or different discs are used as the second disc, the third disc; and wherein the same or different discs are used as the first disc. A method of manufacturing a substrate provided with a semiconductor film according to claim 20, wherein the plurality of single crystal semiconductor layers in close contact with the base substrate are irradiated with a laser beam. A method of manufacturing a substrate provided with a semiconductor film according to claim 20, wherein the bottom substrate is a glass substrate. A method of fabricating a substrate provided with a semiconductor film, comprising: preparing a bottom substrate and a plurality of single crystal semiconductor substrates, the single crystal semiconductor substrate including a damaged region formed at a desired depth in each of the single crystal semiconductor substrates And an insulating layer formed on an upper surface of each of the single crystal semiconductor substrates, and a bonding layer formed on the insulating layer; the plurality of single crystal semiconductor substrates are disposed on the first disk; The plurality of single crystal semiconductor substrates on the first disk are in close contact with the bottom substrate with the bonding layer interposed therebetween to bond one surface of the bonding layer and one surface of the bottom substrate, thereby Bonding the bottom substrate and the plurality of single crystal semiconductor substrates to each other; and generating a crack in the damaged region by heating the plurality of single crystal semiconductor substrates, thereby causing the single crystal semiconductor substrate Separate plurality of first single crystal semiconductor layers are in close contact with the bottom substrate, wherein the step of forming the damaged region comprises generating a plasma and a source by exciting the source gas Irradiating the crystal ionic species included in the plasma half a conductor substrate to form the damaged region in the plurality of single crystal semiconductor substrates while the plurality of single crystal semiconductor substrates are placed on the second disk, wherein the step of forming the insulating layer includes a reaction chamber of a compound gas or a fluorine gas, the plurality of single crystal semiconductor substrates each having the damaged region formed thereon and placed on a third disk, introducing a processing gas into the reaction chamber, by exciting the Processing a gas to generate a plasma, and initiating a chemical reaction of an active species included in the plasma to form a single layer or two or more layers on the plurality of single crystal semiconductor substrates, wherein the formation of the bonding layer The method includes forming the bonding layer on the plurality of single crystal semiconductor substrates with the insulating layer interposed therebetween, and each of the plurality of single crystal semiconductors in which the damaged region and the insulating layer are formed a substrate placed on the fourth disk; wherein the same or different disks are used as the second disk, the third disk, and the fourth disk; and wherein the same or different disks are used as the first disk and Said the fourth set. A method of manufacturing a substrate provided with a semiconductor film according to claim 23, wherein the plurality of single crystal semiconductor layers in close contact with the base substrate are irradiated with a laser beam. A method of manufacturing a substrate provided with a semiconductor film according to claim 23, wherein the bottom substrate is a glass substrate.