JP4834750B2 - 半導体記憶装置 - Google Patents
半導体記憶装置 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims description 57
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 59
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 59
- 229910052710 silicon Inorganic materials 0.000 claims description 53
- 239000010703 silicon Substances 0.000 claims description 53
- 238000003860 storage Methods 0.000 claims description 53
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 52
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 38
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 38
- 239000000758 substrate Substances 0.000 claims description 30
- 238000003949 trap density measurement Methods 0.000 claims description 22
- 239000002159 nanocrystal Substances 0.000 claims description 8
- UMVBXBACMIOFDO-UHFFFAOYSA-N [N].[Si] Chemical compound [N].[Si] UMVBXBACMIOFDO-UHFFFAOYSA-N 0.000 claims description 7
- 239000002184 metal Substances 0.000 claims description 6
- 229910052751 metal Inorganic materials 0.000 claims description 6
- 239000004020 conductor Substances 0.000 claims description 4
- 238000009413 insulation Methods 0.000 claims description 3
- 239000010408 film Substances 0.000 description 244
- 238000000034 method Methods 0.000 description 31
- 238000002955 isolation Methods 0.000 description 23
- 230000000694 effects Effects 0.000 description 18
- 230000005684 electric field Effects 0.000 description 17
- 239000007789 gas Substances 0.000 description 15
- 238000011068 loading method Methods 0.000 description 14
- 238000004519 manufacturing process Methods 0.000 description 12
- LPQOADBMXVRBNX-UHFFFAOYSA-N ac1ldcw0 Chemical compound Cl.C1CN(C)CCN1C1=C(F)C=C2C(=O)C(C(O)=O)=CN3CCSC1=C32 LPQOADBMXVRBNX-UHFFFAOYSA-N 0.000 description 9
- 239000010409 thin film Substances 0.000 description 9
- MROCJMGDEKINLD-UHFFFAOYSA-N dichlorosilane Chemical compound Cl[SiH2]Cl MROCJMGDEKINLD-UHFFFAOYSA-N 0.000 description 8
- 230000008569 process Effects 0.000 description 6
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 4
- 229910021417 amorphous silicon Inorganic materials 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 4
- 230000004048 modification Effects 0.000 description 4
- 238000012986 modification Methods 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 230000005641 tunneling Effects 0.000 description 4
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 3
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 3
- 239000000470 constituent Substances 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 3
- 229910000077 silane Inorganic materials 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 229910021529 ammonia Inorganic materials 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 241000588731 Hafnia Species 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000002425 crystallisation Methods 0.000 description 1
- 230000008025 crystallization Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000010574 gas phase reaction Methods 0.000 description 1
- 229910052735 hafnium Inorganic materials 0.000 description 1
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen group Chemical group [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 description 1
- 229910000069 nitrogen hydride Inorganic materials 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 150000003376 silicon Chemical class 0.000 description 1
- 238000003892 spreading Methods 0.000 description 1
- 230000007480 spreading Effects 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 229910052726 zirconium Inorganic materials 0.000 description 1
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42324—Gate electrodes for transistors with a floating gate
- H01L29/42332—Gate electrodes for transistors with a floating gate with the floating gate formed by two or more non connected parts, e.g. multi-particles flating gate
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
- H01L29/7926—Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
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- H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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Description
まず、図1を参照して本発明が適用されるNANDストリングを有する一括加工型3次元積層メモリについて説明する。
第1の実施形態は、NANDストリング10におけるメモリセルトランジスタMTrのMONOS構造において、電荷蓄積層のトラップ密度を上部側と下部側とで変化させることにより、メモリセル特性の向上を図る例である。
図2は、第1の実施形態に係るNANDストリング10の構成を示している。
図4乃至図10は、本実施形態に係るNANDストリング10の製造工程を示している。
上述したような、下部から上部に向けてトラップ密度が大きくなる電荷蓄積層121の構成について、図11乃至図13を参照して説明する。
図11(a)は、本実施形態に係るメモリセルトランジスタMTrにおけるメモリ膜124の構成1を示している。
図12は、本実施形態に係るメモリセルトランジスタMTrにおけるメモリ膜124の構成2を示している。
図13は、本実施形態に係るメモリセルトランジスタMTrにおけるメモリ膜124の構成3を示している。
上記第1の実施形態によれば、一括加工型3次元積層メモリにおけるトンネル電界が小さい上部側とトンネル電界が大きい下部側とを有するNANDストリング10を構成するメモリ膜124の電荷蓄積層121は、上部側で電荷のトラップ密度が大きく、下部側でトラップ密度が小さくなっている。すなわち、本実施形態では、トンネル電界が小さく、書き込み及び消去速度が遅い上部側の電荷蓄積層121のトラップ密度を大きくし、トンネル電界が大きく、書き込み及び消去速度が速い上部側の電荷蓄積層121のトラップ密度を小さくしている。これにより、NANDストリング10の上部側と下部側において、書き込み及び消去速度のばらつきを低減することができ、デバイスの高速動作を実現することができる。
第1の実施形態は、メモリセルトランジスタのMONOS構造において、電荷蓄積層のトラップ密度を上部側と下部側とで変化させた。これに対し、第2の実施形態は、MONOS構造において、トンネル絶縁膜の正孔の通過効率を上部側と下部側とで変化させることにより、メモリセル特性の向上を図る例である。尚、第2の実施形態において、第1の実施形態と同様の点については説明を省略し、異なる点について詳説する。
図14は、第2の実施形態に係るNANDストリング10の構成を示している。
本実施形態におけるNANDストリング10の製造方法においては、第1の実施形態と同様に、半導体基板表面に低抵抗層CSが形成され、この低抵抗層CS上に下部選択トランジスタLST、メモリセルトランジスタMTr、上部選択トランジスタUST、素子分離絶縁膜118及びビットラインBLが順に形成される。
上述したような、下部から上部に向けて正孔の通過効率が大きくなるトンネル絶縁膜222の構成について、図16を参照して説明する。
上記第2の実施形態によれば、一括加工型3次元積層メモリにおけるトンネル電界が小さい上部側とトンネル電界が大きい下部側とを有するNANDストリング10を構成するメモリ膜224のトンネル絶縁膜222は、上部側で正孔の通過効率が大きく、下部側で正孔の通過効率が小さくなっている。すなわち、本実施形態では、トンネル電界が小さく、書き込み及び消去速度が遅い上部側のトンネル絶縁膜222の正孔の通過効率を大きくし、トンネル電界が大きく、書き込み及び消去速度が速い上部側のトンネル絶縁膜222の正孔の通過効率を小さくしている。これにより、NANDストリング10の上部側と下部側において、書き込み速度とともに特に消去速度のばらつきを低減することができ、デバイスの高速動作を実現することができる。
Claims (6)
- 半導体基板と、
前記半導体基板上に形成された第1選択トランジスタと、
前記第1選択トランジスタ上に積層され、直列に接続された複数のメモリセルトランジスタと、
前記複数のメモリセルトランジスタ上に形成された第2選択トランジスタと、
を具備し、
前記複数のメモリセルトランジスタは、前記第1選択トランジスタから前記第2選択トランジスタに向けて径が大きくなるテーパー形状の柱状半導体と、前記柱状半導体の側面に形成されたトンネル絶縁膜と、前記トンネル絶縁膜の側面に形成され、前記第1選択トランジスタ側から前記第2選択トランジスタ側に向けて電荷のトラップ密度が大きくなる電荷蓄積層と、前記電荷蓄積層の側面に形成されたブロック絶縁膜と、前記ブロック絶縁膜の側面に形成されたゲート電極としての複数の導電体膜と、を有することを特徴とする半導体記憶装置。 - 前記電荷蓄積層は、前記第1選択トランジスタ側から前記第2選択トランジスタ側に向けてシリコンの組成比が大きくなるシリコン窒化膜を主成分とする第1シリコン窒素含有膜で構成されることを特徴とする請求項1記載の半導体記憶装置。
- 前記電荷蓄積層は、前記トンネル絶縁膜の側面に形成されたシリコン窒化膜を主成分とする第2シリコン窒素含有膜と、前記第2シリコン窒素含有膜の側面に形成され、前記第1選択トランジスタ側から前記第2選択トランジスタ側に向けて膜厚が大きくなる高誘電率絶縁膜と、で構成されることを特徴とする請求項1記載の半導体記憶装置。
- 前記電荷蓄積層は、金属又はシリコンで構成され、前記第1選択トランジスタ側から前記第2選択トランジスタ側に向けて存在密度が大きくなるナノクリスタルを含むシリコン窒化膜を主成分とする第3シリコン窒素含有膜で構成されることを特徴とする請求項1記載の半導体記憶装置。
- 半導体基板と、
前記半導体基板上に形成された第1選択トランジスタと、
前記第1選択トランジスタ上に前記半導体基板表面に積層され、直列に接続された複数のメモリセルトランジスタと、
前記複数のメモリセルトランジスタ上に形成された第2選択トランジスタと、
を具備し、
前記複数のメモリセルトランジスタは、前記第1選択トランジスタから前記第2選択トランジスタに向けて径が大きくなるテーパー形状の柱状半導体と、前記柱状半導体の側面に形成され、前記第1選択トランジスタから前記第2選択トランジスタに向けて正孔の通過効率が大きくなるトンネル絶縁膜と、前記トンネル絶縁膜の側面に形成された電荷蓄積層と、前記電荷蓄積層の側面に形成されたブロック絶縁膜と、前記ブロック絶縁膜の側面に形成されたゲート電極としての複数の導電体膜と、を有することを特徴とする半導体記憶装置。 - 前記トンネル絶縁膜は、前記柱状半導体の側面に形成されたシリコン酸化膜を主成分とする第1絶縁膜と、前記第1絶縁膜の側面に形成され、前記第1選択トランジスタから前記第2選択トランジスタに向けて膜厚が大きくなるシリコン窒化膜を主成分とする第2絶縁膜と、前記第2絶縁膜の側面に形成されたシリコン酸化膜を主成分とする第3絶縁膜と、で構成されることを特徴とする請求項5記載の半導体記憶装置。
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US10658376B2 (en) | 2015-12-09 | 2020-05-19 | Toshiba Memory Corporation | Semiconductor device including a blocking layer having a varying thickness |
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JP2011029234A (ja) * | 2009-07-21 | 2011-02-10 | Toshiba Corp | 不揮発性半導体記憶装置 |
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US10658376B2 (en) | 2015-12-09 | 2020-05-19 | Toshiba Memory Corporation | Semiconductor device including a blocking layer having a varying thickness |
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