JP4819516B2 - 導電性ペースト及びその導電性ペーストを用いたセラミック多層回路基板 - Google Patents

導電性ペースト及びその導電性ペーストを用いたセラミック多層回路基板 Download PDF

Info

Publication number
JP4819516B2
JP4819516B2 JP2006025826A JP2006025826A JP4819516B2 JP 4819516 B2 JP4819516 B2 JP 4819516B2 JP 2006025826 A JP2006025826 A JP 2006025826A JP 2006025826 A JP2006025826 A JP 2006025826A JP 4819516 B2 JP4819516 B2 JP 4819516B2
Authority
JP
Japan
Prior art keywords
powder
conductive paste
multilayer circuit
circuit board
ceramic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP2006025826A
Other languages
English (en)
Japanese (ja)
Other versions
JP2007207604A (ja
Inventor
雅利 末廣
博 越智
信雄 落合
仁人 西川
宏昌 三好
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyoto Elex Co Ltd
Original Assignee
Kyoto Elex Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyoto Elex Co Ltd filed Critical Kyoto Elex Co Ltd
Priority to JP2006025826A priority Critical patent/JP4819516B2/ja
Priority to TW095110878A priority patent/TW200731293A/zh
Priority to KR1020060032083A priority patent/KR101118361B1/ko
Publication of JP2007207604A publication Critical patent/JP2007207604A/ja
Application granted granted Critical
Publication of JP4819516B2 publication Critical patent/JP4819516B2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/09—Use of materials for the conductive, e.g. metallic pattern
    • H05K1/092—Dispersed materials, e.g. conductive pastes or inks
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4007—Surface contacts, e.g. bumps
    • H05K3/4015—Surface contacts, e.g. bumps using auxiliary conductive elements, e.g. pieces of metal foil, metallic spheres
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4623—Manufacturing multilayer circuits by laminating two or more circuit boards the circuit boards having internal via connections between two or more circuit layers before lamination, e.g. double-sided circuit boards
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4626—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials
    • H05K3/4629—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials laminating inorganic sheets comprising printed circuits, e.g. green ceramic sheets
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4664—Adding a circuit layer by thick film methods, e.g. printing techniques or by other techniques for making conductive patterns by using pastes, inks or powders

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Inorganic Chemistry (AREA)
  • Dispersion Chemistry (AREA)
  • Conductive Materials (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)
  • Manufacturing Of Printed Wiring (AREA)
JP2006025826A 2006-02-02 2006-02-02 導電性ペースト及びその導電性ペーストを用いたセラミック多層回路基板 Expired - Lifetime JP4819516B2 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2006025826A JP4819516B2 (ja) 2006-02-02 2006-02-02 導電性ペースト及びその導電性ペーストを用いたセラミック多層回路基板
TW095110878A TW200731293A (en) 2006-02-02 2006-03-29 Conductive glue and ceramics multi-layer circuit substrate using such conductive glue
KR1020060032083A KR101118361B1 (ko) 2006-02-02 2006-04-07 도전성 페이스트 및 그 도전성 페이스트를 이용한 세라믹 다층회로기판 제조방법

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2006025826A JP4819516B2 (ja) 2006-02-02 2006-02-02 導電性ペースト及びその導電性ペーストを用いたセラミック多層回路基板

Publications (2)

Publication Number Publication Date
JP2007207604A JP2007207604A (ja) 2007-08-16
JP4819516B2 true JP4819516B2 (ja) 2011-11-24

Family

ID=38486870

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006025826A Expired - Lifetime JP4819516B2 (ja) 2006-02-02 2006-02-02 導電性ペースト及びその導電性ペーストを用いたセラミック多層回路基板

Country Status (3)

Country Link
JP (1) JP4819516B2 (enExample)
KR (1) KR101118361B1 (enExample)
TW (1) TW200731293A (enExample)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100866577B1 (ko) * 2007-09-28 2008-11-03 삼성전기주식회사 인쇄회로기판의 층간 도통방법
US8968608B2 (en) 2008-01-17 2015-03-03 Nichia Corporation Method for producing conductive material, conductive material obtained by the method, electronic device containing the conductive material, light-emitting device, and method for producing light-emitting device
JP5313526B2 (ja) * 2008-03-17 2013-10-09 京都エレックス株式会社 低温焼成多層基板用導電性ペースト
KR100946589B1 (ko) * 2008-04-03 2010-03-09 엘지이노텍 주식회사 반도체 소자 제조용 접착 페이스트 조성물
JP5814204B2 (ja) * 2012-09-10 2015-11-17 京都エレックス株式会社 Ｌｅｄ用セラミックパッケージ用ペースト
JP5849036B2 (ja) * 2012-09-27 2016-01-27 富士フイルム株式会社 導電ペースト、プリント配線基板
CN118342158B (zh) * 2024-03-14 2025-04-11 广州汉源微电子封装材料有限公司 一种大面积封装互连用银焊膏及其制备方法与应用

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0613756A (ja) * 1992-06-25 1994-01-21 Matsushita Electric Ind Co Ltd 導体ペースト組成物
JP2001307549A (ja) 2000-04-21 2001-11-02 Furuya Kinzoku:Kk 銀ペースト及びその製造方法
JP3757211B2 (ja) * 2003-03-14 2006-03-22 富士通株式会社 配線基板及びその製造方法
JP2005293851A (ja) * 2004-03-10 2005-10-20 Toyobo Co Ltd 導電性ペースト
JP2005267900A (ja) * 2004-03-16 2005-09-29 Sumitomo Osaka Cement Co Ltd 導電性ペースト及びその製造方法

Also Published As

Publication number Publication date
KR101118361B1 (ko) 2012-03-09
TW200731293A (en) 2007-08-16
TWI322995B (enExample) 2010-04-01
JP2007207604A (ja) 2007-08-16
KR20070079548A (ko) 2007-08-07

Similar Documents

Publication Publication Date Title
WO2000060613A1 (en) Conductive paste, ceramic multilayer substrate, and method for manufacturing ceramic multilayer substrate
JP3422233B2 (ja) バイアホール用導電性ペースト、およびそれを用いた積層セラミック基板の製造方法
JP4819516B2 (ja) 導電性ペースト及びその導電性ペーストを用いたセラミック多層回路基板
JPH10172345A (ja) 導電ペースト及びそれを用いたセラミック基板の製造方法
JP2004047856A (ja) 導体ペースト及び印刷方法並びにセラミック多層回路基板の製造方法
JP5364833B1 (ja) 導体ペースト及びそれを用いたセラミック基板
JP5385070B2 (ja) ペースト組成物
JPH06100377A (ja) 多層セラミック基板の製造方法
JP4024787B2 (ja) フェライト多層回路基板の導電部形成用導電性ペースト及びその導電性ペーストを用いたフェライト多層回路基板
JP4732227B2 (ja) 導電性ペースト及びその導電性ペーストを用いたセラミック多層回路基板並びにそのセラミック多層回路基板の製造方法
JP2001291959A (ja) 多層セラミック基板の製造方法および銅系導電性ペースト
EP4310066A1 (en) Composite substrate
JP3929989B2 (ja) 導電性ペースト及びその導電性ペーストを用いたセラミック多層回路基板。
JP4293444B2 (ja) 導電性ペースト
JP3216260B2 (ja) 低温焼成セラミックス多層基板及びその製造方法
JP4948459B2 (ja) ペースト組成物
JP4021787B2 (ja) 導電性ペースト及びその導電性ペーストを用いたセラミック多層回路基板
JP4099097B2 (ja) ビアホール充填用導電性ペースト及びその導電性ペーストを用いたセラミック多層回路基板
JP2013118119A (ja) 導電ペースト及びそれを用いた低温焼成セラミック多層基板
JP4298558B2 (ja) 低温焼成セラミック多層回路基板用導電性ペースト及びその導電性ペーストを用いた低温焼成セラミック多層回路基板
JP4820149B2 (ja) 導電性ペーストの製造方法および配線基板の製造方法
JP2005116337A (ja) 導電性ペースト、ビアホール導体及び多層セラミック基板
JP2008192401A (ja) 導電性ペースト
JP2006080363A (ja) 導電性ペースト
JPH0554718B2 (enExample)

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20080828

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20100922

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20100928

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20101116

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20110830

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20110901

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20140909

Year of fee payment: 3

R150 Certificate of patent or registration of utility model

Ref document number: 4819516

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

Free format text: JAPANESE INTERMEDIATE CODE: R150