JP4819516B2 - Conductive paste and ceramic multilayer circuit board using the conductive paste - Google Patents

Conductive paste and ceramic multilayer circuit board using the conductive paste Download PDF

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JP4819516B2
JP4819516B2 JP2006025826A JP2006025826A JP4819516B2 JP 4819516 B2 JP4819516 B2 JP 4819516B2 JP 2006025826 A JP2006025826 A JP 2006025826A JP 2006025826 A JP2006025826 A JP 2006025826A JP 4819516 B2 JP4819516 B2 JP 4819516B2
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powder
conductive paste
multilayer circuit
circuit board
ceramic
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JP2007207604A (en
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雅利 末廣
博 越智
信雄 落合
仁人 西川
宏昌 三好
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Kyoto Elex Co Ltd
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    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/09Use of materials for the conductive, e.g. metallic pattern
    • H05K1/092Dispersed materials, e.g. conductive pastes or inks
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4007Surface contacts, e.g. bumps
    • H05K3/4015Surface contacts, e.g. bumps using auxiliary conductive elements, e.g. pieces of metal foil, metallic spheres
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4611Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4623Manufacturing multilayer circuits by laminating two or more circuit boards the circuit boards having internal via connections between two or more circuit layers before lamination, e.g. double-sided circuit boards
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4611Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4626Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials
    • H05K3/4629Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials laminating inorganic sheets comprising printed circuits, e.g. green ceramic sheets
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4644Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4664Adding a circuit layer by thick film methods, e.g. printing techniques or by other techniques for making conductive patterns by using pastes, inks or powders

Description

本発明は、高密度配線回路基板の製造に用いられるセラミック多層回路基板の導体材料として使用される導電性ペースト及びその導電性ペーストを用いて導体部分を形成してなるセラミック多層回路基板に関する。   The present invention relates to a conductive paste used as a conductor material of a ceramic multilayer circuit board used for manufacturing a high-density wiring circuit board, and a ceramic multilayer circuit board formed with a conductive portion using the conductive paste.

高密度配線回路基板としてセラミック多層回路基板が幅広く用いられている。そのセラミック多層回路基板は一般にセラミックグリーンシート積層法によって、例えば、次のような手順で製造されている。   Ceramic multilayer circuit boards are widely used as high-density wiring circuit boards. The ceramic multilayer circuit board is generally manufactured by the ceramic green sheet lamination method, for example, in the following procedure.

まず、複数枚のセラミックグリーンシートに層間接続用にビアホールをパンチング、レーザー加工などで形成した後、それぞれのセラミックグリーンシートのビアホールに穴埋め印刷法にて導電性ペーストを充填してビア導体を形成し、その後、各セラミックグリーンシート上に導電性ペーストを用いてスクリーン印刷法などにより配線パターンを形成し、さらに、その複数枚のセラミックグリーンシートを積層圧着し、その積層物を焼成してセラミック多層回路基板が製造されている。   First, via holes are punched in multiple ceramic green sheets for interlayer connection, formed by laser processing, etc., and via conductors are filled into the via holes of each ceramic green sheet by hole-filling printing to form via conductors. Thereafter, a wiring pattern is formed on each ceramic green sheet by a screen printing method using a conductive paste, and the ceramic green sheets are laminated and pressure-bonded, and the laminate is fired to form a ceramic multilayer circuit. The substrate is manufactured.

現在用いられているセラミック多層回路基板は、アルミナ等の1300℃以上で焼成される高温焼成セラミック多層回路基板と、約1000℃以下で焼成される低温焼成セラミック多層回路基板に大別される。   Currently used ceramic multilayer circuit boards are roughly classified into high-temperature fired ceramic multilayer circuit boards such as alumina fired at 1300 ° C. or higher and low-temperature fired ceramic multilayer circuit boards fired at approximately 1000 ° C. or lower.

高温焼成セラミック多層回路基板用導体材料としては、Mo、W等が用いられているが、これらの金属を用いる場合、還元雰囲気または不活性雰囲気で焼成しなければならず、これらの金属の電気抵抗は比較的高い。   Mo, W, etc. are used as conductor materials for high-temperature fired ceramic multilayer circuit boards, but when these metals are used, they must be fired in a reducing or inert atmosphere, and the electrical resistance of these metals Is relatively expensive.

一方、低温焼成セラミック多層回路基板用導体材料としては、電気抵抗値の低いAg、Ag−Pt、Ag−Pdなどが使用されており、これらの金属は電気特性に優れているとともに空気中で焼成できるという利点がある。   On the other hand, Ag, Ag-Pt, Ag-Pd, etc., which have low electrical resistance values, are used as conductor materials for low-temperature fired ceramic multilayer circuit boards. These metals have excellent electrical properties and are fired in air. There is an advantage that you can.

しかし、空気中で焼成できる低温焼成セラミック多層回路基板においても、グリーンシートに大量に含まれる導電性ペーストのバインダー成分を基板の焼成前に除去できない場合、そのバインダーを形成する有機化合物が基板の焼成時にガスとなって蒸発し、導電性ペーストからなる配線パターンとセラミック基板の間に隙間やクラックが発生してしまうことがある。そこで、このような問題が生じないように、従来の低温焼成セラミック多層回路基板の製造工程においては、基板の焼成前にバインダー成分を十分に除去するための脱バインダー処理を数時間から数十時間かけて実行した後、基板を焼成していた。   However, even in a low-temperature fired ceramic multilayer circuit board that can be fired in air, if the binder component of the conductive paste contained in a large amount in the green sheet cannot be removed before firing the board, the organic compound that forms the binder is fired on the board. Occasionally, the gas evaporates and a gap or a crack may be generated between the wiring pattern made of the conductive paste and the ceramic substrate. Therefore, in order to prevent such a problem from occurring, in the manufacturing process of the conventional low-temperature fired ceramic multilayer circuit board, the binder removal process for sufficiently removing the binder component before firing the board is performed for several hours to several tens of hours. Then, the substrate was baked.

しかし、長時間の脱バインダー処理は生産性を著しく低下させ、大幅なコスト上昇を招いてしまうので、特許文献1と2には、熱分解しやすいバインダー成分を採用することにより脱バインダー性を改良した導電性ペーストが提案されている。   However, since long-time debinding treatment significantly reduces productivity and causes a significant increase in cost, Patent Documents 1 and 2 improve debinding properties by employing a binder component that is easily thermally decomposed. Conductive pastes have been proposed.

すなわち、特許文献1には、バインダー成分として、アクリル樹脂とアルキド樹脂とを、アクリル樹脂を2〜4重量部、アルキド樹脂を1重量部の割合で含有する導電性ペーストが開示されている。   That is, Patent Document 1 discloses a conductive paste containing acrylic resin and alkyd resin as binder components in a ratio of 2 to 4 parts by weight of acrylic resin and 1 part by weight of alkyd resin.

また、特許文献2には、ずり速度0.2sec-1における粘度をηとし、バインダーを形成する有機化合物の重量平均分子量をMaとするとき、0<Ma<1010の範囲で、Ma>McであればηがManに比例し(ただしn>1)、Ma≦McであればηがMaに比例するような値Mcが存在するバインダー成分を含有する導電性ペーストが開示されている。
特開平5−234424号公報 特開2000−76931号公報
Further, in Patent Document 2, when the viscosity at a shear rate of 0.2 sec −1 is η and the weight average molecular weight of the organic compound forming the binder is Ma, Ma> Mc in the range of 0 <Ma <10 10. if proportional to eta is Ma n (provided that n> 1), conductive paste, if Ma ≦ Mc eta contains a binder component present value Mc as proportional to Ma is disclosed.
JP-A-5-234424 JP 2000-76931 A

しかしながら、特許文献1の導電性ペーストのバインダー成分として使用されるアクリル樹脂は強い曳糸性と粘着性を有しているため、このバインダー成分を含む導電性ペーストを用いて配線パターンを形成する際に、スクリーンメッシュの形状が配線パターンに転写されやすく、その結果、配線パターン表面に凹凸が生じることがある。特に、ライン幅20〜100μm程度の微細な配線パターンを形成する場合、パターン表面の凹凸は基板焼成時にパターンが断線する原因となり、致命的な欠陥である。   However, since the acrylic resin used as the binder component of the conductive paste of Patent Document 1 has strong spinnability and adhesiveness, when forming a wiring pattern using the conductive paste containing this binder component In addition, the shape of the screen mesh is easily transferred to the wiring pattern, and as a result, irregularities may occur on the surface of the wiring pattern. In particular, when a fine wiring pattern having a line width of about 20 to 100 μm is formed, irregularities on the pattern surface cause the pattern to be disconnected when the substrate is baked, which is a fatal defect.

また、特許文献2に記載された導電性ペーストの場合、粘度と分子量との特殊な関係で決定されるバインダー成分を用いる必要があり、極めて煩雑な準備が必要となる。   Moreover, in the case of the electrically conductive paste described in Patent Document 2, it is necessary to use a binder component determined by a special relationship between the viscosity and the molecular weight, which requires extremely complicated preparation.

本発明は従来の技術の有するこのような問題点に鑑みてなされたものであって、その目的は、導体ペーストとセラミックグリーンシートを同時に焼成しても、配線パターンとセラミック基板との間に隙間やクラックが発生せず、信頼性の高いセラミック多層回路基板を容易に得ることができる導電性ペースト及びその導電性ペーストを用いて導体部分を形成してなるセラミック多層回路基板を提供することにある。   The present invention has been made in view of such problems of the prior art, and its purpose is to provide a gap between the wiring pattern and the ceramic substrate even if the conductor paste and the ceramic green sheet are fired simultaneously. An object is to provide a conductive paste capable of easily obtaining a highly reliable ceramic multilayer circuit board without generating cracks and a ceramic multilayer circuit board formed with a conductor portion using the conductive paste. .

上記目的を達成するために本発明の導電性ペーストは、セラミックグリーンシートを積層してから焼成して得られるセラミック多層回路基板における、前記セラミックグリーンシートのビア導体及び配線パターンの少なくともいずれかの形成に用いられ、導電性粉末と、有機化合物からなるバインダー成分と、有機溶剤とを含み、前記セラミックグリーンシートの焼成前に、400〜450℃での脱バインダー処理が行われることによって前記バインダー成分が除去される、導電性ペーストにおいて、導電性粉末として銀粉末と酸化銀粉末とを含有しており、酸化銀粉末がAg 2 O粉末およびAgO粉末の中から選択されたものであり、前記銀粉末を55〜89.9重量%、前記酸化銀粉末を0.1〜15.0重量%含有している構成である。 In order to achieve the above object, the conductive paste of the present invention forms at least one of via conductors and wiring patterns of the ceramic green sheet in a ceramic multilayer circuit board obtained by laminating and firing ceramic green sheets. used, the conductive powder, a binder component consisting of an organic compound, and an organic solvent seen including, prior to firing of the ceramic green sheet, the binder component by debinding at 400 to 450 ° C. is performed The conductive paste contains silver powder and silver oxide powder as the conductive powder, and the silver oxide powder is selected from Ag 2 O powder and AgO powder, and the silver powder from 55 to 89.9 wt%, in the configuration that the silver oxide powder containing 0.1 to 15.0 wt%

銀粉末の平均粒径が0.3〜10.0μmの範囲にあることが好ましい。   The average particle size of the silver powder is preferably in the range of 0.3 to 10.0 μm.

上記導電性ペーストを用いてセラミック多層回路基板の導体部分を形成することが好ましい。   It is preferable to form a conductor portion of the ceramic multilayer circuit board using the conductive paste.

本発明の導電性ペーストは、導電性粉末として銀粉末と酸化銀粉末とを含有しており、酸化銀は、約400℃で次のような反応を起こす。   The conductive paste of the present invention contains silver powder and silver oxide powder as conductive powder, and silver oxide causes the following reaction at about 400 ° C.

2Ag2O→4Ag+O2
2AgO→2Ag+O2
すなわち、酸化銀は約400℃で還元反応を起こすので、基板の焼成前に酸化銀が還元反応を起こすような温度において熱処理(脱バインダー処理)を行うことにより、還元反応の結果生成する酸素(O2)がバインダー成分である有機化合物を分解し、脱バインダーが促進される。その結果、後続する基板の焼成時に配線パターンと基板の間に隙間やクラックが発生しにくい、信頼性の高いセラミック多層回路基板を得ることができる。
2Ag 2 O → 4Ag + O 2
2AgO → 2Ag + O 2
That is, since silver oxide undergoes a reduction reaction at about 400 ° C., by performing a heat treatment (debinding treatment) at a temperature at which the silver oxide undergoes a reduction reaction before firing the substrate, oxygen produced as a result of the reduction reaction ( O 2 ) decomposes the organic compound as the binder component, and the debinding is promoted. As a result, it is possible to obtain a highly reliable ceramic multilayer circuit board in which gaps and cracks are unlikely to occur between the wiring pattern and the board during subsequent firing of the board.

この場合、銀粉末の平均粒径が0.3μm未満では微細なライン幅の配線パターンの印刷は可能だが、焼成時に焼きちぢれを起こし、断線しやすいという不都合がある。一方、銀粉末の平均粒径が10.0μmを超えると、100μm以下のライン幅とライン間隔を有する微細なライン幅の配線パターンの印刷が難しくなるという不都合がある。そこで、銀粉末の平均粒径を0.3〜10.0μmの範囲にすることにより、焼成時に断線することなく微細なライン幅の配線パターンを形成することができる。なお、本願における平均粒径とは、粉末の長径と短径の算術平均値をマイクロトラック社製レーザー回折式粒度分布測定装置で測定したときの累積グラフにおける50容積%での粒径をいう。   In this case, if the average particle diameter of the silver powder is less than 0.3 μm, it is possible to print a wiring pattern with a fine line width, but there is a disadvantage that it is burnt and burnt during firing. On the other hand, when the average particle diameter of the silver powder exceeds 10.0 μm, there is a disadvantage that it becomes difficult to print a wiring pattern having a fine line width having a line width of 100 μm or less and a line interval. Therefore, by setting the average particle size of the silver powder in the range of 0.3 to 10.0 μm, it is possible to form a wiring pattern with a fine line width without disconnection during firing. In addition, the average particle diameter in this application means the particle diameter in 50 volume% in an accumulation graph when the arithmetic mean value of the major axis and minor axis of a powder is measured with the laser diffraction type particle size distribution measuring apparatus by Microtrac.

酸化銀粉末が0.1重量%未満ではバインダー成分の熱分解のための酸素供給源としての効果が十分に期待できないことがある。一方、酸化銀粉末が15.0重量%を超えると、セラミック基板と導体の焼結時の収縮率に不整合を生じ、基板の反りが発生するという不都合がある。そこで、酸化銀粉末を0.1〜15.0重量%含有することにより、かかる不都合がなく、脱バインダー促進効果が十分に期待できる。酸化銀粉末として、Ag2O粉末、AgO粉末のいずれにも脱バインダー促進効果は期待できるので、いずれか一方を単独で用いることもできるが、Ag2O粉末およびAgO粉末の両方を併用することもできる。 If the silver oxide powder is less than 0.1% by weight, the effect as an oxygen supply source for thermal decomposition of the binder component may not be sufficiently expected. On the other hand, when the silver oxide powder exceeds 15.0% by weight, there is a disadvantage in that the shrinkage rate during sintering of the ceramic substrate and the conductor is inconsistent and the substrate is warped. Therefore, by containing 0.1 to 15.0% by weight of silver oxide powder, there is no such inconvenience, and the effect of promoting binder removal can be sufficiently expected. As silver oxide powder, both Ag 2 O powder and AgO powder can be expected to promote binder removal, so either one can be used alone, but both Ag 2 O powder and AgO powder should be used in combination. You can also.

そして、上記の導電性ペーストを用いてセラミック多層回路基板の導体部分を形成すれば、配線パターンとセラミック基板との間に隙間やクラックが発生せず、信頼性の高いセラミック多層回路基板を得ることができる。   Then, if the conductive portion of the ceramic multilayer circuit board is formed using the conductive paste, a highly reliable ceramic multilayer circuit board can be obtained without generating a gap or a crack between the wiring pattern and the ceramic board. Can do.

次ぎに、本発明の導電性ペーストを用いて低温焼成セラミック多層回路基板の導体部分を形成する方法の一例を工程順に説明する。
(1)低温焼成セラミックグリーンシートの成形
低温焼成セラミックのグリーンシートを、ドクターブレード法等でテープ成形する。この際、低温焼成セラミックとしては、例えば、CaO−SiO2−Al23−B23 系ガ ラス50〜65重量%とアルミナ35〜50重量%との混合物を用いることができる。この他、例えば、PbO−SiO2−B23 系ガラスとアルミナの混合物、MgO−Al23−SiO2−B23 系ガラス、コージェライト系結晶化ガラス等の低温焼成セラミック材料を用いることもできる。
(2)グリーンシートの切断とビアホールの形成
次ぎに、テープ成形した低温焼成セラミックグリーンシートを所定の寸法に切断した後、所定の位置にビアホールをパンチング加工する。
(3)ビアホールへの導電性ペーストの充填と配線パターンの印刷
次ぎに、ビアホールへの導電性ペーストの穴埋め印刷法による充填とセラミックグリーンシート上への導電性ペーストによる配線パターンの印刷を行う。
Next, an example of a method for forming a conductor portion of a low-temperature fired ceramic multilayer circuit board using the conductive paste of the present invention will be described in the order of steps.
(1) Molding of low-temperature fired ceramic green sheet A green sheet of low-temperature fired ceramic is tape-molded by a doctor blade method or the like. At this time, as the low-temperature fired ceramic, for example, a mixture of CaO—SiO 2 —Al 2 O 3 —B 2 O 3 glass 50 to 65 wt% and alumina 35 to 50 wt% can be used. In addition, for example, low-temperature fired ceramic materials such as a mixture of PbO—SiO 2 —B 2 O 3 glass and alumina, MgO—Al 2 O 3 —SiO 2 —B 2 O 3 glass, cordierite crystallized glass, etc. Can also be used.
(2) Cutting of green sheet and formation of via hole Next, the tape-formed low-temperature fired ceramic green sheet is cut into a predetermined dimension, and then a via hole is punched at a predetermined position.
(3) Filling the via hole with the conductive paste and printing the wiring pattern Next, filling the via hole with the conductive paste filling method and printing the wiring pattern with the conductive paste on the ceramic green sheet.

このときに使用する銀系導電性ペーストにおける銀粉末と酸化銀粉末からなる導電性粉末と、バインダー成分を有機溶媒に溶解してなる有機ビヒクルとの配合比率は、一般的な配合比率を採用することができる。例えば、重量比で、(70/30)≦(導電性粉末/有機ビヒクル)≦(90/10)とすることができる。導電性粉末が70重量部未満(有機ビヒクルが30重量部超)では、十分な導電性を確保できず、一方、導電性粉末が90重量部超(有機ビヒクルが10重量部未満)では、適正なペースト粘度が得られず、ビアホールへの充填および配線パターン印刷の作業効率が低下するので好ましくない。   The mixing ratio of the conductive powder composed of silver powder and silver oxide powder in the silver-based conductive paste used at this time and the organic vehicle formed by dissolving the binder component in an organic solvent adopts a general mixing ratio. be able to. For example, the weight ratio can satisfy (70/30) ≦ (conductive powder / organic vehicle) ≦ (90/10). If the conductive powder is less than 70 parts by weight (the organic vehicle is more than 30 parts by weight), sufficient conductivity cannot be secured, while the conductive powder is more than 90 parts by weight (the organic vehicle is less than 10 parts by weight). This is not preferable because a high paste viscosity cannot be obtained, and work efficiency in filling via holes and wiring pattern printing is reduced.

本発明の効果を発揮し、良好な電気特性を得るための導電性ペーストの好ましい配合は、合計を100重量部とした場合、銀粉末が55〜89.9重量部、酸化銀粉末が0.1〜15.0重量部、有機ビヒクルが10〜30重量部であり、銀粉末に比べて酸化銀粉末の配合比率は少なくてよいので、電気特性に及ぼす酸化銀粉末の粒径の効果は銀粉末に比べて相対的に小さいと思われるが、焼成時に断線することなく微細なライン幅の配線パターンを形成するためには、酸化銀粉末の平均粒径も銀粉末と同じように、0.3〜10.0μmの範囲にすることが好ましい。   The preferable composition of the conductive paste for exhibiting the effects of the present invention and obtaining good electrical characteristics is that when the total is 100 parts by weight, the silver powder is 55 to 89.9 parts by weight, and the silver oxide powder is 0.00. 1 to 15.0 parts by weight, organic vehicle is 10 to 30 parts by weight, and the blending ratio of silver oxide powder may be less than silver powder, so the effect of the particle size of silver oxide powder on electrical characteristics is silver It seems to be relatively small compared to the powder, but in order to form a fine line width wiring pattern without disconnection during firing, the average particle diameter of the silver oxide powder is 0. It is preferable to make it the range of 3-10.0 micrometers.

有機ビヒクルを構成するバインダー成分としては、限定されるものではないが、エチルセルロースを使用し、有機溶剤としては、 エチルカルビトールアセテート、ブチルカルビトールアセテート、ターピネオール等を使用することができる。   Although it does not limit as a binder component which comprises an organic vehicle, Ethyl cellulose can be used and an ethyl carbitol acetate, a butyl carbitol acetate, a terpineol etc. can be used as an organic solvent.

例えば、上記導電性粉末80重量部に対して、エチルセルロースをターピネオールで溶解した有機ビヒクルを20重量部を添加したものを、3本ロール装置を用いて十分に混練・分散することにより導電性ペーストを得ることができる。   For example, by adding 20 parts by weight of an organic vehicle in which ethyl cellulose is dissolved in terpineol to 80 parts by weight of the conductive powder, the conductive paste is sufficiently kneaded and dispersed using a three-roll apparatus. Obtainable.

配線パターン印刷用の導電性ペーストに含まれる銀粉末とビアホール充填用の導電性ペーストに含まれる銀粉末は必ずしも同じものを用いる必要はなく、前者銀粉末を比較的小
粒径(0.3〜3.0μm)とし、後者銀粉末を比較的大粒径(3.0〜10.0μm)とすることもできる。このようにすれば、小粒径の銀粉末を用いたペーストは微細配線の形成が可能で、大粒径の銀粉末を用いたペーストは低コスト化が可能であるという効果がある。
The silver powder contained in the conductive paste for wiring pattern printing and the silver powder contained in the conductive paste for filling via holes are not necessarily the same, and the former silver powder has a relatively small particle size (0.3 to 3.0 μm), and the latter silver powder can also have a relatively large particle size (3.0-10.0 μm). In this way, the paste using the silver powder having a small particle diameter can form fine wiring, and the paste using the silver powder having a large particle diameter can reduce the cost.

さらに、導電性ペーストとセラミック基板との接着性を向上するために、ガラス成分を導電性ペースト中に0.1重量%以上含有することもできるが、ガラス成分を1.0重量%超添加すると半田濡れ性が悪くなることがあるので、必要に応じてガラス成分を所定量添加するのが好ましい。   Furthermore, in order to improve the adhesiveness between the conductive paste and the ceramic substrate, a glass component can be contained in the conductive paste in an amount of 0.1% by weight or more. Since solder wettability may deteriorate, it is preferable to add a predetermined amount of a glass component as necessary.

また、耐半田食われ性を改善するために、導電性ペースト中にPt粉末またはPd粉末を0.1重量%以上含有することもできるが、Pt粉末またはPd粉末を0.5重量部超添加しても、その効果は飽和する一方、製造コストを上昇させるので、必要に応じてPt粉末またはPd粉末を所定量添加するのが好ましい。
(4)積層と圧着
ビアホールへの導電性ペーストの充填と配線パターンの印刷終了後、各層のグリーンシートを積層圧着して一体化する。
(5)脱バインダー処理
上記積層物を焼成する前に約400〜450℃に積層物を加熱して1〜2時間保持することにより、有機化合物からなるバインダー成分を酸化銀の還元反応の結果生成する酸素により熱分解して除去する。脱バインダー促進のため酸化銀粉末としてAg2O粉末およびAgO粉末の両方を含む場合の比率は、Ag2O粉末が20重量部でAgO粉末が80重量部である比率からAg2O粉末が80重量部でAgO粉末が20重量部である比率の範囲に含まれるのが好ましい。
(6)焼成
脱バインダー処理した積層物を、焼成ピーク温度800〜950℃(好ましくは、900℃前後)とし、ピーク温度で20〜60分間保持の条件で焼成し、低温焼成セラミック多層回路基板を得ることができる。
In order to improve solder corrosion resistance, the conductive paste can contain 0.1 wt% or more of Pt powder or Pd powder, but more than 0.5 parts by weight of Pt powder or Pd powder is added. Even if the effect is saturated, the manufacturing cost is increased. Therefore, it is preferable to add a predetermined amount of Pt powder or Pd powder as necessary.
(4) Lamination and pressure bonding After filling the via holes with the conductive paste and printing the wiring pattern, the green sheets of each layer are laminated and pressure-bonded to be integrated.
(5) Debinder treatment Before firing the laminate, the laminate is heated to about 400 to 450 ° C. and held for 1 to 2 hours to produce a binder component composed of an organic compound as a result of the silver oxide reduction reaction. It is removed by thermal decomposition with oxygen. The ratio of the case of including both of Ag 2 O powder and AgO powder as silver oxide powder for binder removal promotion, Ag 2 O powder is Ag 2 O powder from the ratio AgO powder 20 parts by weight is 80 parts by weight 80 It is preferable that AgO powder is contained in the range of the ratio which is 20 weight part by weight.
(6) Firing The laminate after the binder removal treatment is fired at a firing peak temperature of 800 to 950 ° C. (preferably around 900 ° C.) and held at the peak temperature for 20 to 60 minutes to obtain a low-temperature fired ceramic multilayer circuit board. Obtainable.

図1は、上記のようなプロセスを経て製造した低温焼成セラミック多層回路基板の一例の断面図であり、1は配線パターン、2は導電性ペーストを充填したビアホール、3はセラミックグリーンシートを示す。   FIG. 1 is a cross-sectional view of an example of a low-temperature fired ceramic multilayer circuit board manufactured through the process as described above, where 1 is a wiring pattern, 2 is a via hole filled with a conductive paste, and 3 is a ceramic green sheet.

なお、焼成工程でグリーンシート積層物の両面にアルミナグリーンシートを積層・圧着し、加圧しながら800〜950℃で焼成し、焼成後に両面のアルミナグリーンシートを除去して低温焼成セラミック多層回路基板を製造することもできる。このようにすることで、導体とセラミックとの熱収縮挙動の差に基づく基板の反りや導体の剥がれを抑制することができる。   In addition, alumina green sheets are laminated and pressure-bonded on both sides of the green sheet laminate in the firing step, fired at 800 to 950 ° C. while applying pressure, and after firing, the alumina green sheets on both sides are removed to form a low-temperature fired ceramic multilayer circuit board. It can also be manufactured. By doing in this way, the curvature of a board | substrate based on the difference of the thermal contraction behavior of a conductor and a ceramic and peeling of a conductor can be suppressed.

以下に本発明の実施例を説明するが、本発明は下記実施例に限定されるものではなく、本発明の技術的範囲を逸脱しない範囲において、適宜変更と修正が可能である。   Examples of the present invention will be described below. However, the present invention is not limited to the following examples, and can be appropriately changed and modified without departing from the technical scope of the present invention.

以下の表1に示す平均粒径を有する銀粉末と、酸化銀粉末と、エチルセルロースをターピネオールで溶解した有機ビヒクルとを表1記載のように配合したものを3本ロール装置を用いて混練・分散して導電性ペーストを得、セラミックグリーンシートとして、CaO−Al23−SiO2−B23系ガラス60重量%とアルミナ40重量%を混合してなる正方形状(1インチ×1インチ×300μm厚み)のものを使用した。 Using a three-roll apparatus, a silver powder having an average particle size shown in Table 1 below, a silver oxide powder, and an organic vehicle in which ethyl cellulose is dissolved in terpineol are blended as shown in Table 1 and kneaded and dispersed. As a ceramic green sheet, a square shape (1 inch × 1 inch) obtained by mixing 60 wt% CaO—Al 2 O 3 —SiO 2 —B 2 O 3 glass and 40 wt% alumina is obtained. × 300 μm thickness).

そして、上記セラミックグリーンシートに上記導電性ペーストを用いてスクリーン印刷により図2に示すような配線パターンを形成した後、ベルト式焼成炉にて、そのセラミックグリーンシートに400℃で1時間保持の大気雰囲気条件での加熱処理を施した後に室温まで冷却し、次に、同ベルト式焼成炉にて、ピーク温度890℃、ピーク温度保持時間20分の大気雰囲気条件にて焼成した。そして、その結果得られたセラミック回路基板における配線パターンと基板との隙間ならびに基板の反りを評価した。図2において、Lはライン幅、Sはライン間隔を示す。なお、後記する表1に記載した配線パターンと基板との隙間ならびに基板の反りの評価は、以下に説明するような評価方法に基づくものである。   A wiring pattern as shown in FIG. 2 is formed on the ceramic green sheet by screen printing using the conductive paste, and then the ceramic green sheet is kept at 400 ° C. for 1 hour in a belt-type firing furnace. After heat treatment under atmospheric conditions, the mixture was cooled to room temperature, and then baked in the same belt-type baking furnace under atmospheric conditions at a peak temperature of 890 ° C. and a peak temperature holding time of 20 minutes. And the clearance gap between the wiring pattern and a board | substrate in the ceramic circuit board obtained as a result, and the curvature of the board | substrate were evaluated. In FIG. 2, L indicates the line width, and S indicates the line interval. Note that the evaluation of the gap between the wiring pattern and the substrate and the warpage of the substrate described in Table 1 described later is based on an evaluation method as described below.

配線パターンと基板との隙間の評価方法としては、焼成後のセラミック基板を定盤上に載置して目視観察した結果、配線パターンの全域において基板との間に隙間が認められなかったものを隙間無し(記号○)とし、配線パターンの一部の領域において基板との間に隙間が認められたものをやや隙間有り(記号△)とし、配線パターンのほぼ全域において基板との間に隙間が認められたものを隙間有り(記号×)とした。   As a method of evaluating the gap between the wiring pattern and the substrate, the ceramic substrate after firing was placed on a surface plate and visually observed, and as a result, no gap was found between the wiring pattern and the substrate. There is no gap (symbol ○), and there is a slight gap (symbol △) when there is a gap with the board in a part of the wiring pattern, and there is a gap between the board and the board in almost the entire area of the wiring pattern. What was recognized was defined as a gap (symbol x).

基板の反りの評価方法としては、図3に示すように、焼成後のセラミック基板4を定盤5上に載置して、基板4の下面4aと定盤5の上面5aとの間隔の最大値hを隙間ゲージで測定し、その間隔の最大値hが20μm以下のものを良好(記号○)とし、その間隔の最大値hが25ないし35μmのものをやや不良(記号△)とし、その間隔の最大値hが50μm以上のものを不良(記号×)とした。上記間隔の最大値hが20μm以下のものが実用に適した良好なレベルである。   As shown in FIG. 3, the substrate warpage is evaluated by placing the fired ceramic substrate 4 on the surface plate 5 and maximizing the distance between the lower surface 4 a of the substrate 4 and the upper surface 5 a of the surface plate 5. When the value h is measured with a gap gauge, when the maximum value h of the interval is 20 μm or less, the value is good (symbol ○), and when the maximum value h of the interval is 25 to 35 μm, the value is slightly bad (symbol Δ). Those having a maximum interval h of 50 μm or more were defined as defective (symbol x). When the maximum value h of the interval is 20 μm or less, it is a good level suitable for practical use.

Figure 0004819516
Figure 0004819516

表1に示すように、本発明の実施例1ないし11に係るものは、配線パターンと基板の間に隙間がなく、基板の反りも実用に適した良好なレベルであり、信頼性の高いセラミック回路基板である。   As shown in Table 1, according to Examples 1 to 11 of the present invention, there is no gap between the wiring pattern and the substrate, the warpage of the substrate is a good level suitable for practical use, and a highly reliable ceramic. It is a circuit board.

しかし、比較例1ないし5に係るものは、導電性ペーストにAg2Oが配合されていないので、基板の焼成前にバインダー成分を熱分解することができず、基板の焼成時にバインダー成分がガスとなって蒸発し、配線パターンと基板の間に隙間が生じ、基板にも反りが見られた。 However, in Comparative Examples 1 to 5, since Ag 2 O is not blended in the conductive paste, the binder component cannot be thermally decomposed before the substrate is baked, and the binder component is a gas when the substrate is baked. It evaporated and a gap was formed between the wiring pattern and the substrate, and the substrate was also warped.

比較例6は導電性ペーストにAg2Oを過剰に配合したものであるから、基板の焼成前にバインダー成分を熱分解して除去することができ、配線パターンと基板の間に隙間は生じなかったものの、導体ペーストとセラミック基板との焼結タイミングと収縮率に不整合を生じ、基板に反りが発生した。 In Comparative Example 6, since Ag 2 O is excessively blended in the conductive paste, the binder component can be thermally decomposed and removed before firing the substrate, and no gap is generated between the wiring pattern and the substrate. However, there was a mismatch in the sintering timing and shrinkage rate between the conductor paste and the ceramic substrate, and the substrate warped.

比較例7には導電性ペーストにAg2Oが配合されているが、その配合量が少ないので、基板の焼成前の熱分解によるバインダー除去量が少なくて、残存するバインダー成分が基板の焼成時にガスとなって蒸発し、配線パターンと基板の間に隙間が発生した。 In Comparative Example 7, Ag 2 O is blended in the conductive paste, but since the blending amount is small, the amount of binder removed by thermal decomposition before firing the substrate is small, and the remaining binder component is present during firing of the substrate. The gas evaporated and a gap was generated between the wiring pattern and the substrate.

なお、比較例6および7の場合において、Ag2Oに代えてAgOを使用した場合においても上記と同じ結果が得られた。 In Comparative Examples 6 and 7, the same results as above were obtained when AgO was used instead of Ag 2 O.

低温焼成セラミック多層回路基板の一例の断面図である。It is sectional drawing of an example of a low-temperature baking ceramic multilayer circuit board. スクリーン印刷による配線パターンの一例を示す図である。It is a figure which shows an example of the wiring pattern by screen printing. 基板の反りの評価方法を説明する図である。It is a figure explaining the evaluation method of the curvature of a substrate.

符号の説明Explanation of symbols

1 配線パターン
2 ビアホール
3 セラミックグリーンシート
4 セラミック基板
5 定盤
1 Wiring pattern 2 Via hole 3 Ceramic green sheet 4 Ceramic substrate 5 Surface plate

Claims (3)

セラミックグリーンシートを積層してから焼成して得られるセラミック多層回路基板における、前記セラミックグリーンシートのビア導体及び配線パターンの少なくともいずれかの形成に用いられ、導電性粉末と、有機化合物からなるバインダー成分と、有機溶剤とを含み、前記セラミックグリーンシートの焼成前に、400〜450℃での脱バインダー処理が行われることによって前記バインダー成分が除去される、導電性ペーストにおいて、
導電性粉末として銀粉末と酸化銀粉末とを含有しており、
酸化銀粉末がAg 2 O粉末およびAgO粉末の中から選択されたものであり、
前記銀粉末を55〜89.9重量%、前記酸化銀粉末を0.1〜15.0重量%含有していることを特徴とする導電性ペースト。
In a ceramic multilayer circuit board obtained by laminating ceramic green sheets and firing, the binder component is used for forming at least one of via conductors and wiring patterns of the ceramic green sheets, and made of conductive powder and an organic compound. When, viewed contains an organic solvent, prior to firing of the ceramic green sheet, wherein the binder component is removed by debinding at 400 to 450 ° C. is performed, in the conductive paste,
Contains silver powder and silver oxide powder as conductive powder ,
The silver oxide powder is selected from Ag 2 O powder and AgO powder;
A conductive paste comprising 55 to 89.9% by weight of the silver powder and 0.1 to 15.0% by weight of the silver oxide powder .
銀粉末の平均粒径が0.3〜10.0μmの範囲にあることを特徴とする請求項1記載の導電性ペースト。   The conductive paste according to claim 1, wherein the average particle size of the silver powder is in the range of 0.3 to 10.0 µm. 請求項1または2記載の導電性ペーストを用いて導体部分を形成してなるセラミック多層回路基板。 A ceramic multilayer circuit board obtained by forming a conductor portion using the conductive paste according to claim 1 .
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