JP4812058B2 - Ｆｉｆｏ管理方法及びパイプラインプロセッサシステム - Google Patents

Ｆｉｆｏ管理方法及びパイプラインプロセッサシステム Download PDF

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Publication number
JP4812058B2
JP4812058B2 JP2001036104A JP2001036104A JP4812058B2 JP 4812058 B2 JP4812058 B2 JP 4812058B2 JP 2001036104 A JP2001036104 A JP 2001036104A JP 2001036104 A JP2001036104 A JP 2001036104A JP 4812058 B2 JP4812058 B2 JP 4812058B2
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JP
Japan
Prior art keywords
fifo
processing module
external memory
downstream
information
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Expired - Fee Related
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JP2001036104A
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English (en)
Japanese (ja)
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JP2001256200A (ja
JP2001256200A5 (enExample
Inventor
トゥワン リー コック
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Canon Inc
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Canon Inc
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Publication of JP2001256200A5 publication Critical patent/JP2001256200A5/ja
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2205/00—Indexing scheme relating to group G06F5/00; Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F2205/10—Indexing scheme relating to groups G06F5/10 - G06F5/14
    • G06F2205/108—Reading or writing the data blockwise, e.g. using an extra end-of-block pointer

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Information Transfer Systems (AREA)
  • Advance Control (AREA)
JP2001036104A 2000-02-11 2001-02-13 Ｆｉｆｏ管理方法及びパイプラインプロセッサシステム Expired - Fee Related JP4812058B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
AUPQ5557A AUPQ555700A0 (en) 2000-02-11 2000-02-11 Fifo overflow management
AU5557 2000-02-11
AUPQ5557 2000-02-11

Publications (3)

Publication Number Publication Date
JP2001256200A JP2001256200A (ja) 2001-09-21
JP2001256200A5 JP2001256200A5 (enExample) 2008-04-03
JP4812058B2 true JP4812058B2 (ja) 2011-11-09

Family

ID=3819676

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001036104A Expired - Fee Related JP4812058B2 (ja) 2000-02-11 2001-02-13 Ｆｉｆｏ管理方法及びパイプラインプロセッサシステム

Country Status (3)

Country Link
US (1) US6725299B2 (enExample)
JP (1) JP4812058B2 (enExample)
AU (1) AUPQ555700A0 (enExample)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070260777A1 (en) * 2003-11-25 2007-11-08 Timpe Barrie R Queues for information processing and methods thereof
KR100568115B1 (ko) * 2004-06-30 2006-04-05 삼성전자주식회사 점진적 머지 방법 및 그것을 이용한 메모리 시스템
JP4810090B2 (ja) * 2004-12-20 2011-11-09 キヤノン株式会社 データ処理装置
US8232991B1 (en) 2006-11-03 2012-07-31 Nvidia Corporation Z-test result reconciliation with multiple partitions
US20080208727A1 (en) * 2007-02-28 2008-08-28 Netdeposit, Inc. Endorsement image processing system, method and program product
WO2010122613A1 (ja) * 2009-04-24 2010-10-28 パナソニック株式会社 Ｆｉｆｏバッファ装置
JP5555116B2 (ja) 2010-09-29 2014-07-23 キヤノン株式会社 情報処理装置、及び、プロセッサ間通信制御方法
US9685207B2 (en) 2012-12-04 2017-06-20 Nvidia Corporation Sequential access memory with master-slave latch pairs and method of operating
US20140244921A1 (en) * 2013-02-26 2014-08-28 Nvidia Corporation Asymmetric multithreaded fifo memory
US9811455B2 (en) * 2013-03-15 2017-11-07 The Boeing Company Accessing different types of memory by respective distinct command with different timing requirements
US9223542B2 (en) * 2013-05-20 2015-12-29 Advanced Micro Devices, Inc. Variable-sized buffers mapped to hardware registers
US10141930B2 (en) 2013-06-04 2018-11-27 Nvidia Corporation Three state latch

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0561795A (ja) * 1991-09-04 1993-03-12 Nec Eng Ltd 通信制御装置
JPH05257878A (ja) * 1992-03-16 1993-10-08 Matsushita Electric Ind Co Ltd バッファ装置
JP3810449B2 (ja) * 1994-07-20 2006-08-16 富士通株式会社 キュー装置
US5696990A (en) * 1995-05-15 1997-12-09 Nvidia Corporation Method and apparatus for providing improved flow control for input/output operations in a computer system having a FIFO circuit and an overflow storage area
US5893924A (en) * 1995-07-28 1999-04-13 International Business Machines Corporation System and method for overflow queue processing
IL117134A (en) * 1996-02-14 2000-01-31 Galileo Technology Ltd First-in first-out (fifo) buffer
US6044419A (en) * 1997-09-30 2000-03-28 Intel Corporation Memory handling system that backfills dual-port buffer from overflow buffer when dual-port buffer is no longer full

Also Published As

Publication number Publication date
JP2001256200A (ja) 2001-09-21
US6725299B2 (en) 2004-04-20
AUPQ555700A0 (en) 2000-03-02
US20010018734A1 (en) 2001-08-30

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