JP4810504B2 - 自己整合方式でリセスゲートmosトランジスタ素子を製作する方法 - Google Patents
自己整合方式でリセスゲートmosトランジスタ素子を製作する方法 Download PDFInfo
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- JP4810504B2 JP4810504B2 JP2007155416A JP2007155416A JP4810504B2 JP 4810504 B2 JP4810504 B2 JP 4810504B2 JP 2007155416 A JP2007155416 A JP 2007155416A JP 2007155416 A JP2007155416 A JP 2007155416A JP 4810504 B2 JP4810504 B2 JP 4810504B2
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- 238000000034 method Methods 0.000 title claims description 55
- 238000004519 manufacturing process Methods 0.000 title claims description 30
- 125000006850 spacer group Chemical group 0.000 claims description 37
- 239000004065 semiconductor Substances 0.000 claims description 28
- 239000000758 substrate Substances 0.000 claims description 28
- 238000005530 etching Methods 0.000 claims description 22
- 239000003990 capacitor Substances 0.000 claims description 17
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 17
- 229920005591 polysilicon Polymers 0.000 claims description 17
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 10
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 10
- 239000012535 impurity Substances 0.000 claims description 9
- 238000005468 ion implantation Methods 0.000 claims description 9
- 238000001312 dry etching Methods 0.000 claims description 8
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 6
- 238000009792 diffusion process Methods 0.000 claims description 5
- 239000000463 material Substances 0.000 claims description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims 3
- 229910052710 silicon Inorganic materials 0.000 claims 3
- 239000010703 silicon Substances 0.000 claims 3
- 229910021417 amorphous silicon Inorganic materials 0.000 claims 1
- 230000001590 oxidative effect Effects 0.000 claims 1
- 230000000694 effects Effects 0.000 description 6
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 6
- 230000010354 integration Effects 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/038—Making the capacitor or connections thereto the capacitor being in a trench in the substrate
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/05—Making the transistor
- H10B12/053—Making the transistor the transistor being at least partially in a trench in the substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
- H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Semiconductor Memories (AREA)
Description
11 表面
12 パッド酸化膜
14 パッド窒化シリコン膜
20a、20b トレンチキャパシタ構造
22a、22b キャパシタ溝
24a、24b 側壁キャパシタ誘電膜
26a、26b、74 ドープポリシリコン膜
28a、28b SSBS
30a、30b TTO
42 エッチングストップ膜
44 遮蔽膜
44a、44b 遮蔽スペーサ
50a、50b チルト角イオン注入工程
54 酸化シリコンスペーサ
60、160 ゲート溝
72 犠牲酸化膜
82 窒化シリコンライナー膜
88 ドープ領域
92 誘電ライナー膜
100 メモリアレイ領域
110 ゲート酸化膜
120 ゲート材料膜
180 ドレイン/ゲートドープ領域
Claims (10)
- リセスゲートMOSトランジスタ素子の製作方法であって、
主表面と、アレイ領域と、サポート回路領域を有する半導体基板を設け、
上記半導体基板の主表面から突き出ているTTO(トレンチトップ酸化膜)に覆われる複数のトレンチキャパシタを半導体基板に形成し、
TTOの側壁にスペーサ遮蔽部を形成し、
スペーサ遮蔽部をエッチングハードマスクとして半導体基板をドライエッチングし、自己整合式の溝を形成し、
自己整合式の溝の内面に薄い誘電膜を形成し、
ドープソース/ドレイン領域を形成し、
上記自己整合式の溝の側壁と底部に誘電ライナー膜を形成し、
ドライエッチング工程で上記自己整合式の溝の底部にある誘電ライナー膜と半導体基板をエッチングし、ドープソース/ドレイン領域をソース拡散領域及びドレイン拡散領域と二分するゲート溝を形成し、
ゲート溝の表面にゲート酸化膜を形成し、
上記ゲート酸化膜の上にゲート材料膜を形成するステップからなることを特徴とするMOSトランジスタ素子の製作方法。 - 前記半導体基板は主表面にパッド酸化膜とパッド窒化シリコン膜が形成されることを特徴とする請求項1記載のMOSトランジスタ素子の製作方法。
- 前記TTOはシリコン酸化膜であることを特徴とする請求項1記載のMOSトランジスタ素子の製作方法。
- 前記TTOの側壁にスペーサ遮蔽部を形成するステップは更に、
前記パッド膜とTTOを被覆するようにエッチングストップ膜を半導体基板に堆積し、
エッチングストップ膜に遮蔽膜を堆積し、
遮蔽膜を異方性エッチングしてTTOの側壁に遮蔽スペーサを形成し、
チルト角イオン注入工程でTTOの両側にある遮蔽スペーサに不純物を注入し、
選択的エッチング工程でイオン注入を受けていない遮蔽スペーサを除去してポリシリコンハードマスクを形成し、
ポリシリコンハードマスクを酸化させてスペーサ遮蔽部を形成するステップを含むことを特徴とする請求項1記載のMOSトランジスタ素子の製作方法。 - 前記エッチングストップ膜は窒化シリコンを含むことを特徴とする請求項1記載のMOSトランジスタ素子の製作方法。
- 前記エッチングストップ膜は膜厚50〜500Åであることを特徴とする請求項1記載のMOSトランジスタ素子の製作方法。
- 前記遮蔽膜はポリシリコンまたは非晶質シリコン膜であることを特徴とする請求項4記載のMOSトランジスタ素子の製作方法。
- 前記遮蔽膜は膜厚50〜500Åであることを特徴とする請求項4記載のMOSトランジスタ素子の製作方法。
- 前記チルト角イオン注入工程で利用される不純物は、BF2、P + 、As + 、In + 、Ar + またはその他注入領域と非注入領域のエッチングレートを選択的にする不純物であることを特徴とする請求項4記載のMOSトランジスタ素子の製作方法。
- 前記ドープソース/ドレイン領域を形成するステップは、
自己整合式の溝にドープシリコン膜を埋め込み、
熱工程でドープシリコン膜の不純物を半導体基板に拡散させて拡散領域を形成し、
ドープシリコン膜を除去するステップを含むことを特徴とする請求項1記載のMOSトランジスタ素子の製作方法。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW095114100A TWI323498B (en) | 2006-04-20 | 2006-04-20 | Recessed gate mos transistor device and method of making the same |
US11/696,163 US7679137B2 (en) | 2006-04-20 | 2007-04-03 | Method for fabricating recessed gate MOS transistor device |
US11/696,163 | 2007-04-03 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2008258556A JP2008258556A (ja) | 2008-10-23 |
JP4810504B2 true JP4810504B2 (ja) | 2011-11-09 |
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JP2007155416A Active JP4810504B2 (ja) | 2006-04-20 | 2007-06-12 | 自己整合方式でリセスゲートmosトランジスタ素子を製作する方法 |
Country Status (5)
Country | Link |
---|---|
US (1) | US7679137B2 (ja) |
JP (1) | JP4810504B2 (ja) |
CN (1) | CN101281886B (ja) |
DE (1) | DE102007018760B4 (ja) |
TW (1) | TWI323498B (ja) |
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TWI302355B (en) * | 2006-04-20 | 2008-10-21 | Promos Technologies Inc | Method of fabricating a recess channel array transistor |
TWI278043B (en) * | 2006-05-12 | 2007-04-01 | Nanya Technology Corp | Method for fabricating self-aligned recessed-gate MOS transistor device |
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TWI373101B (en) * | 2007-10-18 | 2012-09-21 | Nanya Technology Corp | Method for fabricating self-aligned recess gate trench |
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TWI368297B (en) * | 2007-11-27 | 2012-07-11 | Nanya Technology Corp | Recessed channel device and method thereof |
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KR102274765B1 (ko) * | 2014-12-17 | 2021-07-09 | 에스케이하이닉스 주식회사 | 전자 장치 및 그 제조 방법 |
KR102212393B1 (ko) | 2014-12-17 | 2021-02-04 | 삼성전자주식회사 | 반도체 소자 및 이의 제조 방법 |
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2006
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2007
- 2007-04-03 US US11/696,163 patent/US7679137B2/en active Active
- 2007-04-20 DE DE102007018760A patent/DE102007018760B4/de active Active
- 2007-06-11 CN CN2007101099813A patent/CN101281886B/zh active Active
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JP2008258556A (ja) | 2008-10-23 |
DE102007018760A1 (de) | 2008-11-06 |
TW200741981A (en) | 2007-11-01 |
CN101281886A (zh) | 2008-10-08 |
US7679137B2 (en) | 2010-03-16 |
DE102007018760B4 (de) | 2011-03-03 |
CN101281886B (zh) | 2010-04-07 |
TWI323498B (en) | 2010-04-11 |
US20070246755A1 (en) | 2007-10-25 |
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