JP4773304B2

JP4773304B2 - Inspection apparatus and inspection method

Info

Publication number: JP4773304B2
Application number: JP2006238539A
Authority: JP
Inventors: 浩山嵜
Original assignee: Hioki EE Corp
Current assignee: Hioki EE Corp
Priority date: 2006-09-04
Filing date: 2006-09-04
Publication date: 2011-09-14
Anticipated expiration: 2026-09-04
Also published as: JP2008058254A

Description

本発明は、各導体パターンの電気的検査に際して、所定の向きに沿って複数の信号線が並設された平形の接続ケーブルを介して検査対象の各導体パターン間に直流電圧を印加して電気的パラメータを測定する検査装置および検査方法に関するものである。 In the electrical inspection of each conductor pattern, the present invention applies an electrical voltage by applying a DC voltage between each conductor pattern to be inspected via a flat connection cable in which a plurality of signal lines are arranged in parallel along a predetermined direction. The present invention relates to an inspection apparatus and an inspection method for measuring a physical parameter.

この種の検査方法に従って導体パターンを検査する検査装置として、複数のプローブ（プローブピン）を検査対象の回路基板における導体パターン（回路パターン）に接触させた状態において所定の電気的検査を実行する検査装置が特開２００３−６６０８８号公報に開示されている。この検査装置では、接続ケーブル（プリント配線基板）を介して各プローブと判定部とが相互に電気的に接続されて、接続ケーブルの各信号線および各プローブを介して判定部から各導体パターンに検査用信号を出力することにより、回路基板の導通、断線、絶縁および短絡等を検査する構成が採用されている。この場合、この検査装置では、上記の接続ケーブルとして、複数の信号線が所定の方向で並設されたフレキシブル回路基板（平形の接続ケーブル）が採用されている。 As an inspection device for inspecting a conductor pattern according to this type of inspection method, an inspection is performed in which a plurality of probes (probe pins) are in contact with a conductor pattern (circuit pattern) on a circuit board to be inspected. An apparatus is disclosed in Japanese Patent Laid-Open No. 2003-66088. In this inspection apparatus, each probe and the determination unit are electrically connected to each other via a connection cable (printed wiring board), and each determination signal is transmitted from the determination unit to each conductor pattern via each signal line and each probe of the connection cable. A configuration is employed in which a circuit board is inspected for continuity, disconnection, insulation, short circuit, and the like by outputting a test signal. In this case, in this inspection apparatus, a flexible circuit board (flat connection cable) in which a plurality of signal lines are arranged in a predetermined direction is employed as the connection cable.

この検査装置を用いて、例えば検査対象の回路基板における各導体パターン間の絶縁を検査する際には、図５に示すように、各プローブ３ａｘ〜３ｈｘを検査対象基板１０ｘの各導体パターンＰａｘ〜Ｐｈｘに接触させる。なお、以下の説明においては、従来の検査装置に関連する構成要素、および検査対象の各構成要素に対して符号の末尾に「ｘ」を付して説明する。また、本発明についての理解を容易とするために、導体パターンＰａｘ〜Ｐｈｘの８つを有する検査対象基板１０ｘを対象としてプローブ３ａｘ〜３ｈｘの８本を使用して電気的検査を実行する例について説明する。この場合、この検査装置では、８本の導体パターンＰａｘ〜Ｐｈｘを対象とする絶縁検査に際して、判定部が、各信号線５ａｘ〜５ｈｘの判定部に対する接続態様を３回に亘って切り替えて、その都度、各導体パターンＰａｘ〜Ｐｈｘ間に直流電圧を印加することで、各導体パターンＰａｘ〜Ｐｈｘの相互間の絶縁状態を検査する。 For example, when inspecting the insulation between the conductor patterns on the circuit board to be inspected using this inspection apparatus, the probes 3ax to 3hx are connected to the conductor patterns Pax to 3x of the inspection target board 10x as shown in FIG. Contact Phx. In the following description, components related to a conventional inspection apparatus and components to be inspected will be described with “x” at the end of the reference numerals. In addition, in order to facilitate understanding of the present invention, an example in which an electrical inspection is performed using eight probes 3ax to 3hx for an inspection target substrate 10x having eight conductor patterns Pax to Phx. explain. In this case, in this inspection apparatus, in the insulation inspection for the eight conductor patterns Pax to Phx, the determination unit switches the connection mode of the signal lines 5ax to 5hx to the determination unit three times, Each time, a DC voltage is applied between the conductor patterns Pax to Phx to inspect the insulation state between the conductor patterns Pax to Phx.

具体的には、判定部は、図示しない接続切替部を制御して、一例として信号線５ａｘ，５ｃｘ，５ｅｘ，５ｇｘを高電位（Ｈレベル）に接続すると共に、信号線５ｂｘ，５ｄｘ，５ｆｘ，５ｈｘを低電位（Ｌレベル）に接続することにより、信号線５ａｘ，５ｃｘ，５ｅｘ，５ｇｘと信号線５ｂｘ，５ｄｘ，５ｆｘ，５ｈｘとの間に直流電圧を印加する。この際に、例えば導体パターンＰａｘ，Ｐｂｘ間に絶縁不良が生じている場合には、プローブ３ａｘ，３ｂｘの間を電流が導通する。したがって、判定部は、直流電圧を印加した状態において、プローブ３ａｘ，３ｃｘ，３ｅｘ，３ｇｘとプローブ３ｂｘ，３ｄｘ，３ｆｘ，３ｈｘとの間を基準値を超える電流が導通するか否かに基づき、導体パターンＰａｘ，Ｐｃｘ，Ｐｅｘ，Ｐｇｘと導体パターンＰｂｘ，Ｐｄｘ，Ｐｆｘ，Ｐｈｘとの相互間の絶縁を検査する。 Specifically, the determination unit controls a connection switching unit (not shown) to connect the signal lines 5ax, 5cx, 5ex, and 5gx to a high potential (H level) as an example, and the signal lines 5bx, 5dx, 5fx, By connecting 5hx to a low potential (L level), a DC voltage is applied between the signal lines 5ax, 5cx, 5ex, 5gx and the signal lines 5bx, 5dx, 5fx, 5hx. At this time, for example, when an insulation failure occurs between the conductor patterns Pax and Pbx, a current is conducted between the probes 3ax and 3bx. Therefore, the determination unit determines whether a current exceeding the reference value is conducted between the probes 3ax, 3cx, 3ex, 3gx and the probes 3bx, 3dx, 3fx, 3hx in a state where a DC voltage is applied. The insulation between the patterns Pax, Pcx, Pex, Pgx and the conductor patterns Pbx, Pdx, Pfx, Phx is inspected.

次いで、図６に示すように、判定部は、一例として信号線５ａｘ，５ｂｘ，５ｅｘ，５ｆｘを高電位（Ｈレベル）に接続すると共に、信号線５ｃｘ，５ｄｘ，５ｇｘ，５ｈｘを低電位（Ｌレベル）に接続することにより、信号線５ａｘ，５ｂｘ，５ｅｘ，５ｆｘと信号線５ｃｘ，５ｄｘ，５ｇｘ，５ｈｘとの間に直流電圧を印加する。この際に、例えば導体パターンＰｂｘ，Ｐｃｘ間に絶縁不良が生じている場合には、プローブ３ｂｘ，３ｃｘの間を電流が導通する。したがって、判定部は、直流電圧を印加した状態において、プローブ３ａｘ，３ｂｘ，３ｅｘ，３ｆｘとプローブ３ｃｘ，３ｄｘ，３ｇｘ，３ｈｘとの間を基準値を超える電流が導通するか否かに基づき、導体パターンＰａｘ，Ｐｂｘ，Ｐｅｘ，Ｐｆｘと導体パターンＰｃｘ，Ｐｄｘ，Ｐｇｘ，Ｐｈｘとの相互間の絶縁を検査する。 Next, as illustrated in FIG. 6, as an example, the determination unit connects the signal lines 5ax, 5bx, 5ex, and 5fx to a high potential (H level), and connects the signal lines 5cx, 5dx, 5gx, and 5hx to a low potential (L By connecting to the signal line 5ax, 5bx, 5ex, 5fx and the signal line 5cx, 5dx, 5gx, 5hx, a DC voltage is applied. At this time, for example, when an insulation failure occurs between the conductor patterns Pbx and Pcx, a current is conducted between the probes 3bx and 3cx. Therefore, the determination unit determines whether a current exceeding the reference value is conducted between the probes 3ax, 3bx, 3ex, 3fx and the probes 3cx, 3dx, 3gx, 3hx in a state where a DC voltage is applied. The insulation between the patterns Pax, Pbx, Pex, Pfx and the conductor patterns Pcx, Pdx, Pgx, Phx is inspected.

続いて、図７に示すように、判定部は、信号線５ａｘ〜５ｄｘを高電位（Ｈレベル）に接続すると共に、信号線５ｅｘ〜５ｈｘを低電位（Ｌレベル）に接続することにより、信号線５ａｘ〜５ｄｘと信号線５ｅｘ〜５ｈｘとの間に直流電圧を印加する。この際に、例えば導体パターンＰｄｘ，Ｐｅｘ間に絶縁不良が生じている場合には、プローブ３ｄｘ，３ｅｘの間を電流が導通する。したがって、判定部は、直流電圧を印加した状態において、プローブ３ａｘ〜３ｄｆとプローブ３ｅｘ〜３ｈｘとの間を基準値を超える電流が導通するか否かに基づき、導体パターンＰａｘ〜Ｐｄｘと導体パターンＰｅｘ〜Ｐｈｘとの相互間の絶縁を検査する。以上の一例の検査により、検査対象基板１０ｘ上の各導体パターンＰａｘ〜Ｐｈｘの相互間の絶縁が検査される。
特開２００３−６６０８８号公報（第４−８頁、第１−４図） Subsequently, as illustrated in FIG. 7, the determination unit connects the signal lines 5ax to 5dx to a high potential (H level) and connects the signal lines 5ex to 5hx to a low potential (L level). A DC voltage is applied between the lines 5ax to 5dx and the signal lines 5ex to 5hx. At this time, for example, if an insulation failure occurs between the conductor patterns Pdx and Pex, a current is conducted between the probes 3dx and 3ex. Therefore, the determination unit determines whether or not the current exceeding the reference value is conducted between the probes 3ax to 3df and the probes 3ex to 3hx in a state where the DC voltage is applied, based on whether or not the conductor patterns Pax to Pdx and the conductor pattern Pex are present. Test the insulation between ~ Phx. The insulation between the conductor patterns Pax to Phx on the inspection target substrate 10x is inspected by the above example inspection.
JP 2003-66088 A (page 4-8, Fig. 1-4)

ところが、従来の検査装置には、以下の問題点が存在する。すなわち、従来の検査装置では、各導体パターンＰａｘ〜Ｐｈｘに接触させるプローブ３ａｘ〜３ｈｘと判定部との間を、フレキシブル回路基板（複数の信号線５ａｘ〜５ｈｘが所定の方向で並設された平形の接続ケーブル）を用いて電気的に接続する構成が採用されている。この場合、図５に示すように、例えば導体パターンＰａｘ，Ｐｃｘ，Ｐｅｘ，Ｐｇｘと導体パターンＰｂｘ，Ｐｄｘ，Ｐｆｘ，Ｐｈｘとの相互間の絶縁検査に際して信号線５ａｘ，５ｃｘ，５ｅｘ，５ｇｘと信号線５ｂｘ，５ｄｘ，５ｆｘ，５ｈｘとの間に直流電圧を印加したときには、信号線５ａｘ，５ｂｘの間、信号線５ｂｘ，５ｃｘの間、信号線５ｃｘ，５ｄｘの間、信号線５ｄｘ，５ｅｘの間、信号線５ｅｘ，５ｆｘの間、信号線５ｆｘ，５ｇｘの間および信号線５ｇｘ，５ｈｘの間に線間浮遊容量Ｃ１ｘ〜Ｃ７ｘが生じる。なお、以下の説明において、信号線５ａｘ〜５ｈｘを区別しないときには、信号線５ｘともいう。 However, the conventional inspection apparatus has the following problems. That is, in the conventional inspection apparatus, a flexible circuit board (a flat type in which a plurality of signal lines 5ax to 5hx are arranged in parallel in a predetermined direction) is provided between the probes 3ax to 3hx brought into contact with the conductor patterns Pax to Phx and the determination unit. The connection cable is electrically connected using a connection cable). In this case, as shown in FIG. 5, for example, when the conductor patterns Pax, Pcx, Pex, Pgx and the conductor patterns Pbx, Pdx, Pfx, Phx are subjected to an insulation test, the signal lines 5ax, 5cx, 5ex, 5gx and the signal lines When a DC voltage is applied between 5bx, 5dx, 5fx, and 5hx, between the signal lines 5ax and 5bx, between the signal lines 5bx and 5cx, between the signal lines 5cx and 5dx, between the signal lines 5dx and 5ex, Line stray capacitances C1x to C7x are generated between the signal lines 5ex and 5fx, between the signal lines 5fx and 5gx, and between the signal lines 5gx and 5hx. In the following description, when the signal lines 5ax to 5hx are not distinguished, they are also referred to as signal lines 5x.

また、図６に示すように、導体パターンＰａｘ，Ｐｂｘ，Ｐｅｘ，Ｐｆｘと導体パターンＰｃｘ，Ｐｄｘ，Ｐｇｘ，Ｐｈｘとの相互間の絶縁検査に際して信号線５ａｘ，５ｂｘ，５ｅｘ，５ｆｘと信号線５ｃｘ，５ｄｘ，５ｇｘ，５ｈｘとの間に直流電圧を印加したときには、信号線５ｂｘ，５ｃｘの間、信号線５ｄｘ，５ｅｘの間および信号線５ｆｘ，５ｇｘの間に線間浮遊容量Ｃ１１ｘ〜Ｃ１３ｘが生じる。さらに、図７に示すように、導体パターンＰａｘ〜Ｐｄｘと導体パターンＰｅｘ〜Ｐｈｘとの相互間の絶縁検査に際して信号線５ａｘ〜５ｄｘと信号線５ｅｘ〜５ｈｘとの間に直流電圧を印加したときには、信号線５ｄｘ，５ｅｘの間に線間浮遊容量Ｃ２１ｘが生じる。 Further, as shown in FIG. 6, signal lines 5 ax, 5 bx, 5 ex, 5 fx and signal lines 5 cx, 5 cx, 5 fx and signal lines 5 cx, When a DC voltage is applied between 5dx, 5gx, and 5hx, line-to-line stray capacitances C11x to C13x are generated between the signal lines 5bx and 5cx, between the signal lines 5dx and 5ex, and between the signal lines 5fx and 5gx. Further, as shown in FIG. 7, when a DC voltage is applied between the signal lines 5ax to 5dx and the signal lines 5ex to 5hx in the insulation inspection between the conductor patterns Pax to Pdx and the conductor patterns Pex to Phx, A stray capacitance C21x between lines is generated between the signal lines 5dx and 5ex.

この場合、この種の検査装置では、上記の各信号線５ａｘ〜５ｈｘの長さが数ｍ程度と非常に長いため、上記の線間浮遊容量Ｃ１ｘ〜Ｃ７ｘ，Ｃ１１ｘ〜Ｃ１３ｘ，Ｃ２１ｘが比較的大きな容量となっている。このため、各信号線５ａｘ〜５ｈｘ間に直流電圧を印加した際には、上記の線間浮遊容量Ｃ１ｘ〜Ｃ７ｘ，Ｃ１１ｘ〜Ｃ１３ｘ，Ｃ２１ｘがチャージされるまで、高電位に接続されている各信号線５ｘと低電位に接続されている各信号線５ｘとの間に比較的大きな電流が導通することとなる。したがって、直流電圧を印加した直後に電流値を測定した場合、各導体パターンＰａｘ〜Ｐｈｘ間が正常に絶縁されている状態であったとしても、基準値を超える電流が測定されて、いずれかの導体パターンＰｘ，Ｐｘ間に絶縁不良が生じていると誤判定を招くおそれがある。 In this case, in the inspection apparatus of this type, the length of each of the signal lines 5ax to 5hx is as long as several meters, so that the inter-line stray capacitances C1x to C7x, C11x to C13x, and C21x are relatively large. It is capacity. For this reason, when a DC voltage is applied between the signal lines 5ax to 5hx, the signals connected to a high potential until the above-described inter-line stray capacitances C1x to C7x, C11x to C13x, and C21x are charged. A relatively large current is conducted between the line 5x and each signal line 5x connected to a low potential. Therefore, when the current value is measured immediately after the DC voltage is applied, even if the conductor patterns Pax to Phx are normally insulated, the current exceeding the reference value is measured, If an insulation failure occurs between the conductor patterns Px and Px, an erroneous determination may be caused.

このため、従来の検査装置では、上記の線間浮遊容量Ｃ１ｘ〜Ｃ７ｘ，Ｃ１１ｘ〜Ｃ１３ｘ，Ｃ２１ｘへのチャージに際して導通する電流に起因していずれかの導体パターンＰｘ，Ｐｘ間に絶縁不良が生じているとの誤判定が生じるのを回避するために、直流電圧の印加を開始してから、高電位に接続されている各信号線５ｘと低電位に接続されている各信号線５ｘとの間が十分にチャージされるまで待機した後に電流を測定し、その測定結果に基づいて絶縁検査する構成が採用されている。したがって、従来の検査装置には、線間浮遊容量Ｃ１ｘ〜Ｃ７ｘ，Ｃ１１ｘ〜Ｃ１３ｘ，Ｃ２１ｘへのチャージが完了するまでの待機時間が長いことに起因して、すべての導体パターンＰａｘ〜Ｐｈｘの絶縁検査を完了するまでの時間が非常に長いという問題点がある。 For this reason, in the conventional inspection apparatus, an insulation failure occurs between any of the conductor patterns Px and Px due to a current that is conducted when charging the above-described line-to-line stray capacitances C1x to C7x, C11x to C13x, and C21x. In order to avoid the occurrence of a false determination that there is a difference between the signal line 5x connected to the high potential and the signal line 5x connected to the low potential after the application of the DC voltage is started. A configuration is adopted in which the current is measured after waiting until the battery is sufficiently charged, and the insulation test is performed based on the measurement result. Therefore, the conventional inspection apparatus has an insulation inspection of all the conductor patterns Pax to Phx due to a long waiting time until the charge to the line stray capacitances C1x to C7x, C11x to C13x, and C21x is completed. There is a problem that the time to complete is very long.

本発明は、かかる問題点に鑑みてなされたものであり、導体パターン間の絶縁検査に要する検査時間を短縮し得る検査装置および検査方法を提供することを主目的とする。 The present invention has been made in view of such problems, and a main object of the present invention is to provide an inspection apparatus and an inspection method capable of shortening the inspection time required for insulation inspection between conductor patterns.

上記目的を達成すべく請求項１記載の検査装置は、所定の向きに沿って複数の信号線が並設された平形の接続ケーブルを介して検査対象の各導体パターン間に直流電圧を印加して電気的パラメータを測定する測定部と、前記各信号線と高電位および低電位のいずれかの電位との接続を切り替える切替部と、Ｎ（Ｎは、４以上の整数）本の前記導体パターンを検査する際に、前記切替部を制御して前記各信号線の接続切替えを（（Ｍ−１）＜ｌｏｇ_２Ｎ≦Ｍ（Ｍは整数））の条件を満たすＭ回行うと共に、当該各切り替えた状態において前記高電位に接続された当該各導体パターンと前記低電位に接続された当該各導体パターンとの間の前記電気的パラメータを前記測定部に測定させて当該Ｎ本の導体パターンについての電気的検査を実行する制御部とを備え、前記制御部は、前記Ｍ回の各電気的検査において、前記切替部を制御して、前記各信号線のうちの前記所定の向きで隣接して検査対象の一対の前記導体パターンに接続されている一対の信号線の一方を前記高電位および前記低電位のいずれか一方の電位に接続させると共に当該一方の信号線に対して前記所定の向きとは逆向き側において隣接する他の信号線が存在するときには当該他の信号線を当該いずれか一方の電位に接続させ、かつ前記一対の信号線の他方を前記高電位および前記低電位のいずれか他方の電位に接続させると共に当該他方の信号線に対して前記所定の向き側において隣接する他の信号線が存在するときには当該他の信号線を当該いずれか他方の電位に接続させる。 In order to achieve the above object, the inspection apparatus according to claim 1 applies a DC voltage between the conductor patterns to be inspected via a flat connection cable in which a plurality of signal lines are arranged in parallel along a predetermined direction. A measuring unit that measures electrical parameters, a switching unit that switches connection between each signal line and one of a high potential and a low potential, and N (N is an integer of 4 or more) conductor patterns And switching the connection of each signal line by M times satisfying the condition of ((M−1) <log ₂ N ≦ M (M is an integer)). Regarding the N conductor patterns, the measurement unit measures the electrical parameter between the conductor patterns connected to the high potential and the conductor patterns connected to the low potential in the switched state. Perform electrical inspection of A control unit, wherein the control unit controls the switching unit in each of the M electrical inspections, and a pair of the inspection targets adjacent to each other in the predetermined direction among the signal lines. One of the pair of signal lines connected to the conductor pattern is connected to one of the high potential and the low potential, and is adjacent to the one signal line on the side opposite to the predetermined direction. When there is another signal line to be connected, the other signal line is connected to one of the potentials, and the other of the pair of signal lines is connected to the other potential of the high potential and the low potential. At the same time, when there is another signal line adjacent to the other signal line on the predetermined direction side, the other signal line is connected to the other potential.

また、請求項２記載の検査装置は、請求項１記載の検査装置において、前記制御部は、前記Ｎ（Ｎは、２^Ｍで表される８以上の整数）本の前記導体パターンを検査する際に、第Ｌ（Ｌは１からＭの各々）の前記電気的検査において、２^{（Ｍ−Ｌ）}対の前記導体パターンを検査対象として当該各電気的検査を順不同で実行し、当該第Ｌ（Ｌは１）の電気的検査において、前記切替部を制御して両端のＬ本の前記各信号線を前記いずれか一方の電位に接続させると共に残りの（Ｎ−２×Ｌ）本の前記各信号線を当該２^{（Ｍ−Ｌ）}対の導体パターンを検査可能に前記いずれかの電位に接続させ、当該第Ｌ（Ｌは２から（Ｍ−１）の各々）の電気的検査において、当該切替部を制御して両端において隣接する２^{（Ｌ−１）}本の前記各信号線を当該いずれか一方の電位に接続させると共に残りの隣接する（Ｎ−２×２×（Ｌ−１））本の前記各信号線を当該２^{（Ｍ−Ｌ）}対の導体パターンを検査可能に当該いずれかの電位に接続させ、当該第Ｌ（ＬはＭ）の電気的検査において、当該切替部を制御して一方の端側で隣接する２^{（Ｌ−１）}本の前記各信号線を当該いずれか一方の電位に接続させると共に他方の端側で隣接する２^{（Ｌ−１）}本の前記各信号線を前記いずれか他方の電位に接続させる。 The inspection device according to claim 2 is the inspection device according to claim 1, wherein the control unit inspects the N (N is an integer of 8 or more represented by ^2M ) conductor patterns. In this case, in the L-th electrical inspection (where L is 1 to M), each of the electrical inspections is performed in random order with 2 ^(ML) pairs of the conductor patterns as inspection targets. In the electrical inspection (L is 1), the switching unit is controlled to connect the L signal lines at both ends to the one of the potentials, and the remaining (N−2 × L) of the signal lines. Each signal line is connected to one of the potentials so that the 2 ^(ML) pairs of conductor patterns can be inspected, and in the L-th electrical inspection (L is from 2 to (M−1)), adjacent at both ends by controlling the switching unit 2 ^(L-1) the physician a book of the respective signal lines The remaining adjacent or causes connected to one potential Re (N-2 × 2 × ( L-1)) of the present of the respective signal lines either the 2 ^(M-L) inspect the pairs of conductive patterns can be the In the L-th (L is M) electrical inspection, the switching unit is controlled to connect the two ^(L-1) signal lines adjacent on one end side to any one of the potentials. The two ^(L-1) signal lines adjacent to each other are connected to one of the other potentials and connected to the other potential.

また、請求項３記載の検査方法は、所定の向きに沿って複数の信号線が並設された平形の接続ケーブルを介して検査対象の各導体パターン間に直流電圧を印加して電気的パラメータを測定する測定処理と、前記各信号線と高電位および低電位のいずれかの電位との接続を切り替える切替え処理とを実行してＮ（Ｎは、４以上の整数）本の前記導体パターンについての電気的検査を実行する際に、前記切替え処理を（（Ｍ−１）＜ｌｏｇ_２Ｎ≦Ｍ（Ｍは整数））の条件を満たすＭ回行うと共に、当該各切り替えた状態において前記測定処理として前記高電位に接続された当該各導体パターンと前記低電位に接続された当該各導体パターンとの間の前記電気的パラメータを測定する検査方法であって、
前記Ｍ回の各電気的検査において、前記切替え処理として、前記各信号線のうちの前記所定の向きで隣接して検査対象の一対の前記導体パターンに接続されている一対の信号線の一方を前記高電位および前記低電位のいずれか一方の電位に接続すると共に当該一方の信号線に対して前記所定の向きとは逆向き側において隣接する他の信号線が存在するときには当該他の信号線を当該いずれか一方の電位に接続し、かつ前記一対の信号線の他方を前記高電位および前記低電位のいずれか他方の電位に接続すると共に当該他方の信号線に対して前記所定の向き側において隣接する他の信号線が存在するときには当該他の信号線を当該いずれか他方の電位に接続する。 According to a third aspect of the present invention, there is provided an inspection method in which a DC voltage is applied between each conductor pattern to be inspected through a flat connection cable in which a plurality of signal lines are arranged in parallel along a predetermined direction. N (N is an integer greater than or equal to 4) conductor patterns by performing measurement processing for measuring and switching processing for switching connection between each signal line and one of a high potential and a low potential When the electrical inspection is performed, the switching process is performed M times satisfying the condition ((M−1) <log ₂ N ≦ M (M is an integer)), and the measurement process is performed in each switched state. As an inspection method for measuring the electrical parameter between each conductor pattern connected to the high potential and each conductor pattern connected to the low potential,
In each of the M electrical inspections, as the switching process, one of a pair of signal lines connected to the pair of conductor patterns to be inspected adjacent to each other in the predetermined direction among the signal lines. When there is another signal line that is connected to one of the high potential and the low potential and is adjacent to the one signal line in the direction opposite to the predetermined direction, the other signal line Is connected to one of the potentials, and the other of the pair of signal lines is connected to the other potential of the high potential and the low potential, and the predetermined direction side with respect to the other signal line When there is another signal line adjacent to the other signal line, the other signal line is connected to the other potential.

また、請求項４記載の検査方法は、請求項３記載の検査方法において、前記Ｎ（Ｎは、２^Ｍで表される８以上の整数）本の前記導体パターンを検査する際に、第Ｌ（Ｌは１からＭの各々）の前記電気的検査において２^{（Ｍ−Ｌ）}対の前記導体パターンを検査対象として当該各電気的検査を順不同で実行し、当該第Ｌ（Ｌは１）の電気的検査において、前記切替え処理として両端のＬ本の前記各信号線を前記いずれか一方の電位に接続すると共に残りの（Ｎ−２×Ｌ）本の前記各信号線を当該２^{（Ｍ−Ｌ）}対の導体パターンを検査可能に前記いずれかの電位に接続し、当該第Ｌ（Ｌは２から（Ｍ−１）の各々）の電気的検査において、当該切替え処理として両端において隣接する２^{（Ｌ−１）}本の前記各信号線を当該いずれか一方の電位に接続すると共に残りの隣接する（Ｎ−２×２×（Ｌ−１））本の前記各信号線を当該２^{（Ｍ−Ｌ）}対の導体パターンを検査可能に当該いずれかの電位に接続し、当該第Ｌ（ＬはＭ）の電気的検査において、当該切替え処理として一方の端側で隣接する２^{（Ｌ−１）}本の前記各信号線を当該いずれか一方の電位に接続すると共に他方の端側で隣接する２^{（Ｌ−１）}本の前記各信号線を前記いずれか他方の電位に接続する。 An inspection method according to claim 4 is the inspection method according to claim 3, wherein the N (N is an integer of 8 or more represented by 2 ^M ) inspecting the conductor pattern, In the electrical inspection (L is 1 to M), the electrical inspections are performed in random order with 2 ^(ML) pairs of the conductor patterns as inspection targets, and the Lth (L is 1) In the electrical inspection, as the switching process, the L signal lines at both ends are connected to one of the potentials and the remaining (N−2 × L) signal lines are connected to the 2 ^{(M− L) A} pair of conductor patterns are connected to any one of the potentials so that they can be inspected, and in the L-th electrical inspection (L is from 2 to (M-1)), 2 adjacent to both ends as the switching process. ^(L-1) contacting a book of the respective signal lines to the one of the potential Connected to the rest of the adjacent (N-2 × 2 × ( L-1)) of the present of the respective signal lines of either the 2 ^(M-L) inspect the pairs of conductive patterns can be the potential well as, In the L-th (L is M) electrical inspection, as the switching process, 2 ^(L−1) signal lines adjacent on one end side are connected to the potential of either one and the other The 2 ^(L-1) signal lines adjacent on the end side are connected to the other potential.

請求項１記載の検査装置および請求項３記載の検査方法では、（（Ｍ−１）＜ｌｏｇ_２Ｎ≦Ｍ（Ｍは整数））の条件を満たすＭ回の各電気的検査において、接続ケーブルの各信号線のうちの所定の向きで隣接して検査対象の一対の導体パターンに接続されている一対の信号線の一方を高電位および低電位のいずれか一方の電位に接続すると共に一方の信号線に対して所定の向きとは逆向き側において隣接する他の信号線が存在するときには他の信号線を上記のいずれか一方の電位に接続し、かつ一対の信号線の他方を高電位および低電位のいずれか他方の電位に接続すると共に他方の信号線に対して所定の向き側において隣接する他の信号線が存在するときには他の信号線を上記のいずれか他方の電位に接続する。 In the inspection apparatus according to claim 1, and the inspection method according to claim 3, in each of M electrical inspections satisfying a condition of ((M-1) <log ₂ N ≦ M (M is an integer)), the connection cable One of a pair of signal lines adjacent to each other in a predetermined direction and connected to a pair of conductor patterns to be inspected is connected to one of a high potential and a low potential and When there is another signal line adjacent to the signal line on the side opposite to the predetermined direction, the other signal line is connected to one of the above potentials, and the other of the pair of signal lines is set to the high potential. In addition, when there is another signal line adjacent to the other signal line in a predetermined direction, the other signal line is connected to one of the other potentials. .

したがって、請求項１記載の検査装置および請求項３記載の検査方法によれば、Ｍ回の各電気的検査のすべてにおいて、上記の一方の信号線と、その一方の信号線に対して所定の向きとは逆向き側において隣接する他の信号線との間に線間浮遊容量が生じることがなく、また、上記の他方の信号線と、その他方の信号線に対して所定の向き側において隣接する他の信号線との間に線間浮遊容量が生じることがないため、絶縁検査に際して直流電圧を印加した際に、各信号線間の線間浮遊容量へのチャージに要する時間を十分に短縮することができる。これにより、直流電圧の印加を開始してから十分に短い時間だけ待機しただけで電流値を測定したとしても、線間浮遊容量のチャージに起因する電流値を検出して各導体パターン間に絶縁不良が生じているとの誤判定を招くことなく、結果として、十分に短時間で各導体パターンの絶縁検査を行うことができる。 Therefore, according to the inspection apparatus according to claim 1 and the inspection method according to claim 3, in all of the M electrical inspections, the one signal line and the one signal line are predetermined. There is no stray capacitance between the other signal lines adjacent to the direction opposite to the direction, and the other signal line and the other signal line are on a predetermined direction side. Since no stray capacitance between lines is generated between other adjacent signal lines, sufficient time is required to charge the stray capacitance between the signal lines when a DC voltage is applied during an insulation test. It can be shortened. As a result, even if the current value is measured by simply waiting for a sufficiently short time after starting the application of the DC voltage, the current value resulting from the charge of the floating capacitance between the lines is detected and insulated between the conductor patterns. As a result, the insulation inspection of each conductor pattern can be performed in a sufficiently short time without causing an erroneous determination that a defect has occurred.

また、請求項２記載の検査装置および請求項４記載の検査方法では、Ｎ（Ｎは、２^Ｍで表される８以上の整数）本の導体パターンを検査する際に、第Ｌ（Ｌは１からＭの各々）の電気的検査において２^{（Ｍ−Ｌ）}対の導体パターンを検査対象として各電気的検査を順不同で実行し、第Ｌ（Ｌは１）の電気的検査において、両端のＬ本の各信号線を高電位および低電位のいずれか一方の電位に接続すると共に残りの（Ｎ−２×Ｌ）本の各信号線を２^{（Ｍ−Ｌ）}対の導体パターンを検査可能に高電位および低電位のいずれかの電位に接続し、第Ｌ（Ｌは２から（Ｍ−１）の各々）の電気的検査において、両端において隣接する２^{（Ｌ−１）}本の各信号線を上記のいずれか一方の電位に接続すると共に残りの隣接する（Ｎ−２×２×（Ｌ−１））本の各信号線を２^{（Ｍ−Ｌ）}対の導体パターンを検査可能に上記のいずれかの電位に接続し、第Ｌ（ＬはＭ）の電気的検査において、一方の端側で隣接する２^{（Ｌ−１）}本の各信号線を上記のいずれか一方の電位に接続すると共に他方の端側で隣接する２^{（Ｌ−１）}本の各信号線を高電位および低電位のいずれか他方の電位に接続する。 In the inspection apparatus according to claim 2 and the inspection method according to claim 4, when inspecting N (N is an integer of 8 or more represented by 2 ^M ) conductor patterns, Lth (L is In each of the electrical inspections 1 to M), each of the electrical inspections is performed in random order with 2 ^(ML) pairs of conductor patterns as inspection targets. In the Lth electrical inspection (L is 1), Connect each of the L signal lines to either the high potential or the low potential and inspect the remaining (N−2 × L) signal lines for 2 ^(ML) pairs of conductor patterns Are connected to either the high potential or the low potential, and in the L-th electrical test (L is from 2 to (M-1)), 2 ^(L-1) signals adjacent to each other at both ends Connect the wire to one of the above potentials and the remaining adjacent (N−2 × 2 × (L−1)) 2 ^(M−L) pairs of conductor patterns are connected to any one of the above potentials so as to be inspected, and in the L-th (L is M) electrical inspection, two adjacent signal lines are adjacent on one end side. ^(L-1) Connect each signal line to any one of the above potentials, and connect 2 ^(L-1) each signal line adjacent to the other end to either the high potential or the low potential. Connect to the potential.

したがって、請求項２記載の検査装置および請求項４記載の検査方法によれば、Ｍ回の各電気的検査のすべてにおいて、各信号線間に生じる線間浮遊容量を十分に小さくすることができる。これにより、各導体パターンの絶縁検査に要する時間を十分に短縮することができる。具体的には、例えば、８つの導体パターンを検査対象として、かつ各導体パターン間の線間浮遊容量が互いに等しいＣとしたときには、従来の検査装置では、１１×Ｃの線間浮遊容量をチャージする充電時間を要していたのに対して、この回路基板検査装置１では、７×Ｃの線間浮遊容量をチャージする充電時間まで短縮することができる。なお、検査対象の導体パターンの数が多くなればなるほど、充電時間を短縮することができるのは勿論である。 Therefore, according to the inspection apparatus according to claim 2 and the inspection method according to claim 4, the inter-line stray capacitance generated between the signal lines can be sufficiently reduced in all M electrical inspections. . Thereby, the time required for the insulation inspection of each conductor pattern can be sufficiently shortened. Specifically, for example, when eight conductor patterns are to be inspected and the line stray capacitance between the conductor patterns is C equal to each other, the conventional inspection apparatus charges 11 × C line stray capacitance. The circuit board inspection apparatus 1 can shorten the charging time for charging the 7 × C line-to-line stray capacitance. Of course, as the number of conductor patterns to be inspected increases, the charging time can be shortened.

以下、本発明に係る検査装置および検査方法の最良の形態について、添付図面を参照して説明する。 Hereinafter, the best mode of an inspection apparatus and an inspection method according to the present invention will be described with reference to the accompanying drawings.

最初に、回路基板検査装置１の構成について、図面を参照して説明する。 First, the configuration of the circuit board inspection apparatus 1 will be described with reference to the drawings.

図１に示す回路基板検査装置１は、本発明に係る検査方法に従って検査対象基板１０（図２〜４参照）を電気的に検査する検査装置であって、プローブ保持部２、Ｎ本のプローブ３ａ〜３Ｎ、測定部４、接続ケーブル５、切替部６、制御部７および記憶部８を備えている。この場合、この回路基板検査装置１は、検査対象基板１０に形成されている導体パターンＰ（図２〜４参照）の数に応じて、例えば１０００本程度のプローブ３ａ〜３Ｎを備えて構成されているが、本発明についての理解を容易とするために、一例として、検査対象基板１０に８つの導体パターンＰ（Ｐａ〜Ｐｈ）が形成され、この導体パターンＰａ〜Ｐｈの相互間の絶縁をプローブ３ａ〜３ｈ（Ｎ＝８の例）を用いて検査する例について以下に説明する。 A circuit board inspection apparatus 1 shown in FIG. 1 is an inspection apparatus that electrically inspects an inspection target substrate 10 (see FIGS. 2 to 4) according to an inspection method according to the present invention, and includes a probe holder 2 and N probes. 3a to 3N, a measurement unit 4, a connection cable 5, a switching unit 6, a control unit 7, and a storage unit 8. In this case, the circuit board inspection apparatus 1 includes, for example, about 1000 probes 3a to 3N according to the number of conductor patterns P (see FIGS. 2 to 4) formed on the inspection target substrate 10. However, in order to facilitate understanding of the present invention, as an example, eight conductor patterns P (Pa to Ph) are formed on the substrate 10 to be inspected, and the conductor patterns Pa to Ph are insulated from each other. An example of inspection using the probes 3a to 3h (example of N = 8) will be described below.

プローブ保持部２は、プローブ３ａ〜３ｈの基端部を保持する。プローブ３ａ〜３ｈは、いわゆる伸縮型のピンプローブであって、その基端部がプローブ保持部２によって保持されると共に接続ケーブル５および切替部６を介して測定部４に電気的に接続される。なお、図２〜４では、本発明についての理解を容易とするために、各プローブ３ａ〜３ｈが横一列に並んだ状態を図示しているが、実際には、プローブ３ａ〜３ｈを接触させるべき各導体パターンＰａ〜Ｐｈの検査対象基板１０上における位置に対応する位置においてプローブ保持部２によって保持されている。測定部４は、制御部７からの制御信号Ｓ２に従い、後述するように、接続ケーブル５を介してプローブ３ａ〜３ｈに検査用信号としての直流電圧を印加した状態において、高電位に接続されているプローブ３と低電位に接続されているプローブ３との間を導通する電流を測定して、その測定値Ｄ１を制御部７に出力する。 The probe holding unit 2 holds the base end portions of the probes 3a to 3h. The probes 3a to 3h are so-called telescopic pin probes, and their base ends are held by the probe holding unit 2 and are electrically connected to the measuring unit 4 via the connection cable 5 and the switching unit 6. . 2 to 4 show a state in which the probes 3a to 3h are arranged in a horizontal row in order to facilitate understanding of the present invention, the probes 3a to 3h are actually brought into contact with each other. Each of the power conductor patterns Pa to Ph is held by the probe holding unit 2 at a position corresponding to the position on the inspection target substrate 10. In accordance with the control signal S2 from the control unit 7, the measurement unit 4 is connected to a high potential in a state where a DC voltage as an inspection signal is applied to the probes 3a to 3h via the connection cable 5, as will be described later. The current conducted between the probe 3 and the probe 3 connected to a low potential is measured, and the measured value D1 is output to the control unit 7.

接続ケーブル５は、プローブ３ａ〜３ｈの本数（この例では、８本）に応じた数の信号線５ａ〜５Ｎ（この例では、信号線５ａ〜５ｈの８本）が横一列に並設された（所定の向きに沿って並設された）いわゆるフラットケーブル（本発明における平形ケーブル）であって、信号線５ａ〜５ｈの各一端部がプローブ３ａ〜３ｈに接続される共に、他端部が切替部６を介して測定部４に電気的に接続される。なお、図２〜４では、同図における左から右への向きが本発明における「所定の向き」に相当する。切替部６は、図１に示すように、別個独立して切り替えが可能なスイッチ６ａ〜６Ｎ（この例では、スイッチ６ａ〜６ｈの８つ）を備え、制御部７からの制御信号Ｓ１に従い、信号線５ａ〜５ｈのうちの所定の４本を測定部４から測定用信号を出力する高電位側端子（本明細書では単に高電位（Ｈレベル）ともいう）に接続すると共に、信号線５ａ〜５ｈのうちの他の４本を測定部４から測定用信号を出力する低電位側端子（本明細書では単に低電位（Ｌレベル）ともいう）に接続する。 The connection cable 5 includes a number of signal lines 5a to 5N (in this example, 8 signal lines 5a to 5h) corresponding to the number of probes 3a to 3h (eight in this example) arranged in a horizontal row. A so-called flat cable (flat cable in the present invention) (in parallel with a predetermined direction), each end of the signal lines 5a to 5h being connected to the probes 3a to 3h, and the other end Are electrically connected to the measuring unit 4 via the switching unit 6. 2 to 4, the direction from left to right in the figure corresponds to the “predetermined direction” in the present invention. As shown in FIG. 1, the switching unit 6 includes switches 6 a to 6 N (in this example, eight switches 6 a to 6 h) that can be switched independently and in accordance with a control signal S <b> 1 from the control unit 7. Predetermined four of the signal lines 5a to 5h are connected to a high potential side terminal (in this specification, also simply referred to as a high potential (H level)) that outputs a measurement signal from the measurement unit 4, and the signal line 5a The other four of ˜5h are connected to a low potential side terminal (also simply referred to as a low potential (L level) in this specification) that outputs a measurement signal from the measurement unit 4.

制御部７は、回路基板検査装置１を総括的に制御する。具体的には、制御部７は、切替部６を制御して各信号線５ａ〜５ｈを測定部４の高電位および低電位のいずれかに接続させる接続切替え処理を実行する。この場合、制御部７は、Ｎ（この例では、Ｎ＝８）本の導体パターンＰａ〜Ｐｈを検査する際に、切替部６を制御して上記の接続切替え処理を（（Ｍ−１）＜ｌｏｇ_２Ｎ≦Ｍ（Ｍは整数））の条件を満たすＭ（この例では、Ｍ＝３）回実行する。また、制御部７は、測定部４を制御して、導体パターンＰａ〜Ｐｈ間に直流電圧を印加させた状態において高電位に接続されているプローブ３と低電位に接続されているプローブ３との間を導通する電流値（電気的パラメータの一例）を測定させる測定処理を実行させる。さらに、制御部７は、測定部４から出力された測定値Ｄ１と記憶部８に記憶されている検査用基準データＤ２とに基づき、各導体パターンＰａ〜Ｐｈ間の絶縁状態を電気的に検査する。記憶部８は、上記の検査用基準データＤ２や制御部７の動作プログラムなどを記憶する。 The control unit 7 comprehensively controls the circuit board inspection apparatus 1. Specifically, the control unit 7 executes connection switching processing for controlling the switching unit 6 to connect the signal lines 5 a to 5 h to either the high potential or the low potential of the measurement unit 4. In this case, when inspecting N (N = 8 in this example) conductor patterns Pa to Ph, the control unit 7 controls the switching unit 6 to perform the connection switching process ((M−1)). <Log ₂ N ≦ M (M is an integer)) is executed M (in this example, M = 3) times. Moreover, the control part 7 controls the measurement part 4, and the probe 3 connected to the high potential and the probe 3 connected to the low potential in a state where the DC voltage is applied between the conductor patterns Pa to Ph. A measurement process for measuring a current value (an example of an electrical parameter) that conducts between the two is executed. Further, the control unit 7 electrically inspects the insulation state between the conductor patterns Pa to Ph based on the measurement value D1 output from the measurement unit 4 and the inspection reference data D2 stored in the storage unit 8. To do. The storage unit 8 stores the inspection reference data D2, the operation program of the control unit 7, and the like.

次に、回路基板検査装置１による検査対象基板１０の検査方法について、図面を参照して説明する。 Next, an inspection method of the inspection target substrate 10 by the circuit board inspection apparatus 1 will be described with reference to the drawings.

まず、図２に示すように、各プローブ３ａ〜３ｈを検査対象基板１０の各導体パターンＰａ〜Ｐｈに接触させる。次いで、制御部７は、切替部６を制御して測定部４に対する信号線５ａ〜５ｈの接続を切り替える上記の接続切替え処理と、測定部４を制御して上記の測定処理を実行させて測定値Ｄ１を出力させる処理とを３回に亘って実行することで、導体パターンＰａ〜Ｐｈの相互間の絶縁状態を電気的に検査する。 First, as shown in FIG. 2, the probes 3 a to 3 h are brought into contact with the conductor patterns Pa to Ph of the inspection target substrate 10. Next, the control unit 7 controls the switching unit 6 to switch the connection of the signal lines 5a to 5h to the measurement unit 4, and controls the measurement unit 4 to execute the measurement process to perform measurement. By performing the process of outputting the value D1 over three times, the insulation state between the conductor patterns Pa to Ph is electrically inspected.

具体的には、第１回目の電気的検査として、制御部７は、切替部６に制御信号Ｓ１を出力することにより、一例として信号線５ａ，５ｄ，５ｅ，５ｈを高電位（Ｈレベル）に接続すると共に、信号線５ｂ，５ｃ，５ｆ，５ｇを低電位（Ｌレベル）に接続させる。この接続形態では、信号線５ａ，５ｂ、信号線５ｃ，５ｄ、信号線５ｅ，５ｆおよび信号線５ｇ，５ｈがそれぞれ本発明における「一対の信号線」に相当する。また、この接続形態では、信号線５ｂ，５ｄ，５ｆが本発明における「一方の信号線に対して所定の向きとは逆向き側において隣接する他の信号線」に相当し、信号線５ｃ，５ｅ，５ｇが本発明における「他方の信号線に対して所定の向き側において隣接する他の信号線」に相当する。さらに、この第１回目の電気的検査を本発明における「第Ｌ（Ｌ＝１）の電気的検査」とした場合、信号線５ａおよび信号線５ｅが本発明における「Ｌの信号線」（この例では、１本）に相当し、信号線５ｂ〜５ｇが本発明における「（Ｎ−２×Ｌ）本の信号線」（この例では、６本）に相当する。 Specifically, as a first electrical inspection, the control unit 7 outputs a control signal S1 to the switching unit 6, thereby causing the signal lines 5a, 5d, 5e, and 5h to have a high potential (H level) as an example. And the signal lines 5b, 5c, 5f, and 5g are connected to a low potential (L level). In this connection form, the signal lines 5a and 5b, the signal lines 5c and 5d, the signal lines 5e and 5f, and the signal lines 5g and 5h respectively correspond to “a pair of signal lines” in the present invention. In this connection form, the signal lines 5b, 5d, and 5f correspond to the “other signal lines adjacent to the one signal line on the side opposite to the predetermined direction” in the present invention. 5e and 5g correspond to “other signal lines adjacent to the other signal line in a predetermined direction” in the present invention. Further, when the first electrical inspection is the “Lth (L = 1) electrical inspection” in the present invention, the signal line 5 a and the signal line 5 e are “L signal lines” (this In the example, it corresponds to one), and the signal lines 5b to 5g correspond to “(N−2 × L) signal lines” (six in this example) in the present invention.

次いで、制御部７は、測定部４に制御信号Ｓ２を出力することにより、切替部６の各スイッチ６ａ〜６ｈを介して高電位側に接続された信号線５ａ，５ｄ，５ｅ，５ｈと、低電位側に接続された信号線５ｂ，５ｃ，５ｆ，５ｇとの間に一例として、所定電圧の直流電圧を検査用信号として印加させる。続いて、測定部４は、信号線５ａ〜５ｈ間に生じる線間浮遊容量へのチャージが完了するまでの所定時間だけ待機した後に、プローブ３ａ，３ｄ，３ｅ，３ｈとプローブ３ｂ，３ｃ，３ｆ，３ｇとの間を導通する電流値を測定して測定値Ｄ１を制御部７に出力する（本発明における「測定処理」の実行）。 Next, the control unit 7 outputs a control signal S2 to the measurement unit 4, thereby connecting the signal lines 5a, 5d, 5e, and 5h connected to the high potential side through the switches 6a to 6h of the switching unit 6, For example, a DC voltage of a predetermined voltage is applied as an inspection signal between the signal lines 5b, 5c, 5f, and 5g connected to the low potential side. Subsequently, the measurement unit 4 waits for a predetermined time until the charge to the inter-line stray capacitance generated between the signal lines 5a to 5h is completed, and then the probes 3a, 3d, 3e, and 3h and the probes 3b, 3c, and 3f. , 3g, and the measured value D1 is output to the control unit 7 (execution of “measurement processing” in the present invention).

この場合、この回路基板検査装置１では、第１回目の電気的に検査に際して接続ケーブル５およびプローブ３ａ〜３ｈを介して各導体パターンＰａ〜Ｐｈ間に直流電圧を印加した状態において、信号線５ａ，５ｂの間、信号線５ｃ，５ｄの間、信号線５ｅ，５ｆの間および信号線５ｇ，５ｈの間に線間浮遊容量Ｃ１〜Ｃ４が生じる。その一方で、信号線５ｂ，５ｃが互いに同電位に接続され、信号線５ｄ，５ｅが互いに同電位に接続され、かつ信号線５ｆ，５ｇが互いに同電位に接続されているため、信号線５ｂ，５ｃの間、信号線５ｄ，５ｅの間および信号線５ｆ，５ｇの間に線間浮遊容量が生じない。このため、上記の線間浮遊容量Ｃ１〜Ｃ４の合成容量が、従来の検査装置における第１回目の電気的検査（図５参照）時に信号線５ａｘ〜５ｈｘ間に生じる線間浮遊容量Ｃ１ｘ〜Ｃ７ｘの合成容量よりも十分に小さくなっており、短時間でチャージが完了する。したがって、測定部４は、従来の検査装置における第１回目の電気的検査のときよりも短い所定時間だけ待機した後に電流値を測定する。 In this case, in this circuit board inspection apparatus 1, in the state where a DC voltage is applied between the conductor patterns Pa to Ph via the connection cable 5 and the probes 3a to 3h in the first electrical inspection, the signal line 5a , 5b, between signal lines 5c and 5d, between signal lines 5e and 5f, and between signal lines 5g and 5h, line-to-line stray capacitances C1 to C4 are generated. On the other hand, the signal lines 5b and 5c are connected to the same potential, the signal lines 5d and 5e are connected to the same potential, and the signal lines 5f and 5g are connected to the same potential. , 5c, between the signal lines 5d and 5e, and between the signal lines 5f and 5g, no inter-line stray capacitance occurs. For this reason, the combined capacitance of the above-mentioned line stray capacitances C1 to C4 is the line stray capacitance C1x to C7x generated between the signal lines 5ax to 5hx during the first electrical inspection (see FIG. 5) in the conventional inspection apparatus. Therefore, the charging is completed in a short time. Therefore, the measurement unit 4 measures the current value after waiting for a predetermined time shorter than that in the first electrical inspection in the conventional inspection apparatus.

一方、制御部７は、測定部４から出力された測定値Ｄ１と記憶部８に記憶されている検査用基準データＤ２とに基づき、測定部４によって測定された電流値が基準値以内の値であるか否かを判定する。この際に、例えば導体パターンＰａ，Ｐｂ間に絶縁不良が生じている場合には、プローブ３ａ，３ｂの間を電流が導通する。したがって、制御部７は、直流電圧を印加した状態において、プローブ３ａ，３ｄ，３ｅ，３ｈとプローブ３ｂ，３ｃ，３ｆ，３ｇとの間を基準値を超える電流が導通するか否かに基づき、導体パターンＰａ，Ｐｄ，Ｐｅ，Ｐｈと導体パターンＰｂ，Ｐｃ，Ｐｆ，Ｐｇとの相互間の絶縁を検査する。具体的には、制御部７は、基準値を超える電流が導通したときには、導体パターンＰａ，Ｐｂの間、導体パターンＰｃ，Ｐｄの間、導体パターンＰｅ，Ｐｆの間および導体パターンＰｇ，Ｐｈの間のいずれかに絶縁不良が生じている（短絡が生じている）と判別し、電流が基準値以下のときには、いずれにも短絡が生じておらず良好な絶縁状態であると判別する。これにより、検査対象基板１０についての第１回目の電気的検査が完了する。 On the other hand, the control unit 7 determines that the current value measured by the measurement unit 4 is a value within the reference value based on the measurement value D1 output from the measurement unit 4 and the inspection reference data D2 stored in the storage unit 8. It is determined whether or not. At this time, for example, if an insulation failure occurs between the conductor patterns Pa and Pb, a current is conducted between the probes 3a and 3b. Therefore, the control unit 7 determines whether a current exceeding the reference value is conducted between the probes 3a, 3d, 3e, and 3h and the probes 3b, 3c, 3f, and 3g in a state where a DC voltage is applied. The insulation between the conductor patterns Pa, Pd, Pe, Ph and the conductor patterns Pb, Pc, Pf, Pg is inspected. Specifically, when a current exceeding the reference value is conducted, the control unit 7 determines that the conductor patterns Pa and Pb, the conductor patterns Pc and Pd, the conductor patterns Pe and Pf, and the conductor patterns Pg and Ph It is determined that an insulation failure has occurred in any of them (short circuit has occurred), and when the current is below the reference value, it is determined that no short circuit has occurred and that the insulation state is good. Thereby, the first electrical inspection on the inspection target substrate 10 is completed.

次いで、制御部７は、導体パターンＰａ〜Ｐｈに対するプローブ３ａ〜３ｈの接続を維持した状態において、第２回目の電気的検査として、切替部６に制御信号Ｓ１を出力することにより、図３に示すように、一例として信号線５ａ，５ｂ，５ｇ，５ｈを高電位（Ｈレベル）に接続すると共に、信号線５ｃ〜５ｆを低電位（Ｌレベル）に接続させる。この接続形態では、信号線５ｂ，５ｃおよび信号線５ｆ，５ｇがそれぞれ本発明における「一対の信号線」に相当する。また、この接続形態では、信号線５ａおよび信号線５ｃ〜５ｅが本発明における「一方の信号線に対して所定の向きとは逆向き側において隣接する他の信号線」に相当し、信号線５ｄ〜５ｆおよび信号線５ｈが本発明における「他方の信号線に対して所定の向き側において隣接する他の信号線」に相当する。さらに、この第２回目の電気的検査を本発明における「第Ｌ（Ｌ＝２〜（Ｍ−１）：この例では、Ｌ＝２）の電気的検査」とした場合、信号線５ａ，５ｂおよび信号線５ｇ，５ｈが本発明における「両端において隣接する２^{（Ｌ−１）}本の信号線」（この例では、２本）に相当し、信号線５ｃ〜５ｆが本発明における「（Ｎ−２×２×（Ｌ−１））本の信号線」（この例では、４本）に相当する。 Next, the control unit 7 outputs the control signal S1 to the switching unit 6 as a second electrical inspection in a state where the connections of the probes 3a to 3h with respect to the conductor patterns Pa to Ph are maintained, so that FIG. As shown, the signal lines 5a, 5b, 5g, and 5h are connected to a high potential (H level) and the signal lines 5c to 5f are connected to a low potential (L level) as an example. In this connection form, each of the signal lines 5b and 5c and the signal lines 5f and 5g corresponds to a “pair of signal lines” in the present invention. In this connection configuration, the signal line 5a and the signal lines 5c to 5e correspond to “another signal line adjacent to one signal line on the side opposite to the predetermined direction” in the present invention. 5d to 5f and the signal line 5h correspond to “another signal line adjacent to the other signal line in a predetermined direction” in the present invention. Further, when the second electrical inspection is the “Lth (L = 2 to (M−1): L = 2 in this example) electrical inspection” in the present invention, the signal lines 5a and 5b. The signal lines 5g and 5h correspond to “2 ^(L−1) signal lines adjacent at both ends” (two in this example) in the present invention, and the signal lines 5c to 5f correspond to “(N −2 × 2 × (L−1)) signal lines ”(4 in this example).

続いて、制御部７は、測定部４に制御信号Ｓ２を出力することにより、切替部６の各スイッチ６ａ〜６ｈを介して高電位側に接続された信号線５ａ，５ｂ，５ｇ，５ｈと、低電位側に接続された信号線５ｃ〜５ｆとの間に直流電圧を印加させる。また、測定部４は、信号線５ａ〜５ｈ間に生じる線間浮遊容量へのチャージが完了するまでの所定時間だけ待機した後に、プローブ３ａ，３ｂ，３ｇ，３ｈとプローブ３ｃ〜３ｆとの間を導通する電流値を測定して測定値Ｄ１を制御部７に出力する（本発明における「測定処理」の実行）。 Subsequently, the control unit 7 outputs the control signal S2 to the measurement unit 4 to thereby connect the signal lines 5a, 5b, 5g, 5h connected to the high potential side through the switches 6a to 6h of the switching unit 6. A DC voltage is applied between the signal lines 5c to 5f connected to the low potential side. In addition, the measurement unit 4 waits for a predetermined time until the charge to the inter-line floating capacitance generated between the signal lines 5a to 5h is completed, and then between the probes 3a, 3b, 3g, and 3h and the probes 3c to 3f. Is measured and the measured value D1 is output to the control unit 7 (execution of “measurement processing” in the present invention).

この場合、この回路基板検査装置１では、第２回目の電気的に検査に際して接続ケーブル５およびプローブ３ａ〜３ｈを介して各導体パターンＰａ〜Ｐｈ間に直流電圧を印加した状態において、信号線５ｂ，５ｃの間および信号線５ｆ，５ｇの間に線間浮遊容量Ｃ１１，Ｃ１２が生じる。その一方、信号線５ａ，５ｂが互いに同電位に接続され、信号線５ｃ〜５ｆが互いに同電位に接続され、かつ信号線５ｇ，５ｈが互いに同電位に接続されているため、信号線５ａ，５ｂの間、信号線５ｃ，５ｄの間、信号線５ｄ，５ｅの間、信号線５ｅ，５ｆの間および信号線５ｇ，５ｈの間に線間浮遊容量が生じない。 In this case, in the circuit board inspection apparatus 1, the signal line 5b is applied in a state where a DC voltage is applied between the conductor patterns Pa to Ph via the connection cable 5 and the probes 3a to 3h in the second electrical inspection. , 5c and between the signal lines 5f and 5g, stray capacitances C11 and C12 are generated between the lines. On the other hand, the signal lines 5a and 5b are connected to the same potential, the signal lines 5c to 5f are connected to the same potential, and the signal lines 5g and 5h are connected to the same potential. Between the signal lines 5c and 5d, between the signal lines 5d and 5e, between the signal lines 5e and 5f, and between the signal lines 5g and 5h, no inter-line stray capacitance is generated.

このため、信号線５ｄ，５ｅの間に線間浮遊容量が生じていない分だけ、上記の線間浮遊容量Ｃ１１，Ｃ１２の合成容量が、従来の検査装置における第２回目の電気的検査（図６参照）時に信号線５ａｘ〜５ｈｘ間に生じる線間浮遊容量Ｃ１１ｘ〜Ｃ１３ｘの合成容量よりも十分に小さくなっており、短時間でチャージが完了する。したがって、測定部４は、従来の検査装置における第２回目の電気的検査のときよりも短い所定時間だけ待機した後に電流値を測定する。一方、制御部７は、測定部４から出力された測定値Ｄ１と記憶部８に記憶されている検査用基準データＤ２とに基づき、上記したように、測定部４によって測定された電流値が基準値以内の値であるか否かを判定する。これにより、検査対象基板１０についての第２回目の電気的検査が完了する。 For this reason, the combined capacitance of the above-described inter-line stray capacitances C11 and C12 is equivalent to the second electrical inspection in the conventional inspection apparatus (see FIG. 5) because the inter-line stray capacitance is not generated between the signal lines 5d and 5e. 6) is sufficiently smaller than the combined capacitance of the line stray capacitances C11x to C13x generated between the signal lines 5ax to 5hx, and charging is completed in a short time. Therefore, the measuring unit 4 measures the current value after waiting for a predetermined time shorter than the time of the second electrical inspection in the conventional inspection apparatus. On the other hand, based on the measurement value D1 output from the measurement unit 4 and the inspection reference data D2 stored in the storage unit 8, the control unit 7 determines the current value measured by the measurement unit 4 as described above. It is determined whether the value is within the reference value. Thereby, the second electrical inspection of the inspection target substrate 10 is completed.

次いで、制御部７は、導体パターンＰａ〜Ｐｈに対するプローブ３ａ〜３ｈの接続を維持した状態において、第３回目の電気的検査として、切替部６に制御信号Ｓ１を出力することにより、図４に示すように、一例として信号線５ａ〜５ｄを高電位（Ｈレベル）に接続すると共に、信号線５ｅ〜５ｈを低電位（Ｌレベル）に接続させる。この接続形態では、信号線５ｄ，５ｅが本発明における「一対の信号線」に相当する。また、この接続形態では、信号線５ａ〜５ｃが本発明における「一方の信号線に対して所定の向きとは逆向き側において隣接する他の信号線」に相当し、信号線５ｆ〜５ｈが本発明における「他方の信号線に対して所定の向き側において隣接する他の信号線」に相当する。さらに、この第３回目の電気的検査を本発明における「第Ｌ（Ｌ＝Ｍ）の電気的検査」とした場合、信号線５ａ〜５ｄが本発明における「一方の端側で隣接する２^{（Ｌ−１）}の各信号線」（この例では、４本）に相当し、信号線５ｅ〜５ｈが本発明における「他方の端側で隣接する２^{（Ｌ−１）}の各信号線」（この例では、４本）に相当する。 Next, the control unit 7 outputs a control signal S1 to the switching unit 6 as a third electrical inspection in a state in which the connection of the probes 3a to 3h to the conductor patterns Pa to Ph is maintained, thereby obtaining the configuration shown in FIG. As illustrated, the signal lines 5a to 5d are connected to a high potential (H level) as an example, and the signal lines 5e to 5h are connected to a low potential (L level). In this connection form, the signal lines 5d and 5e correspond to “a pair of signal lines” in the present invention. In this connection form, the signal lines 5a to 5c correspond to “another signal line adjacent to the one signal line on the side opposite to the predetermined direction” in the present invention, and the signal lines 5f to 5h are This corresponds to “another signal line adjacent to the other signal line in a predetermined direction” in the present invention. Furthermore, when the third electrical inspection is the “Lth (L = M) electrical inspection” in the present invention, the signal lines 5a to 5d are adjacent to each other on the one end side 2 ^{( L-1)} signal lines ”(4 lines in this example), and the signal lines 5e to 5h in the present invention are“ 2 ^(L-1) signal lines adjacent on the other end side ”( In this example, it corresponds to 4).

続いて、制御部７は、測定部４に制御信号Ｓ２を出力することにより、切替部６の各スイッチ６ａ〜６ｈを介して高電位側に接続された信号線５ａ〜５ｄと、低電位側に接続された信号線５ｅ〜５ｈとの間に直流電圧を印加させる。また、測定部４は、信号線５ａ〜５ｈ間に生じる線間浮遊容量へのチャージが完了するまでの所定時間だけ待機した後に、プローブ３ａ〜３ｄとプローブ３ｅ〜３ｈとの間を導通する電流値測定して測定値Ｄ１を制御部７に出力する（本発明における「測定処理」の実行）。 Subsequently, the control unit 7 outputs the control signal S2 to the measurement unit 4 to thereby connect the signal lines 5a to 5d connected to the high potential side via the switches 6a to 6h of the switching unit 6 and the low potential side. A DC voltage is applied between the signal lines 5e to 5h connected to. In addition, the measurement unit 4 waits for a predetermined time until the charge to the inter-line stray capacitance generated between the signal lines 5a to 5h is completed, and then conducts current between the probes 3a to 3d and the probes 3e to 3h. The value is measured and the measured value D1 is output to the control unit 7 (execution of “measurement processing” in the present invention).

この場合、この回路基板検査装置１では、第３回目の電気的に検査に際して接続ケーブル５およびプローブ３ａ〜３ｈを介して各導体パターンＰａ〜Ｐｈ間に直流電圧を印加した状態において、信号線５ｄ，５ｅの間に線間浮遊容量Ｃ２１が生じる。この線間浮遊容量Ｃ２１は、従来の検査装置における第３回目の電気的検査（図７参照）時に信号線５ａｘ〜５ｈｘ間に生じる線間浮遊容量Ｃ２１ｘと同等となっている。したがって、測定部４は、従来の検査装置における第３回目の電気的検査のときと同等の時間だけ待機した後に電流値を測定する。一方、制御部７は、測定部４から出力された測定値Ｄ１と記憶部８に記憶されている検査用基準データＤ２とに基づき、測定部４によって測定された電流値が基準値以内の値であるか否かを判定する。これにより、検査対象基板１０についての第３回目の電気的検査が完了する。 In this case, in the circuit board inspection apparatus 1, the signal line 5d is applied in the state where a DC voltage is applied between the conductor patterns Pa to Ph via the connection cable 5 and the probes 3a to 3h in the third electrical inspection. , 5e, a line-to-line stray capacitance C21 is generated. This inter-line stray capacitance C21 is equivalent to the inter-line stray capacitance C21x generated between the signal lines 5ax to 5hx during the third electrical inspection (see FIG. 7) in the conventional inspection apparatus. Therefore, the measuring unit 4 measures the current value after waiting for a time equivalent to the time of the third electrical inspection in the conventional inspection apparatus. On the other hand, the control unit 7 determines that the current value measured by the measurement unit 4 is a value within the reference value based on the measurement value D1 output from the measurement unit 4 and the inspection reference data D2 stored in the storage unit 8. It is determined whether or not. Thereby, the third electrical inspection of the inspection target substrate 10 is completed.

以上の３回に亘る検査により、検査対象基板１０上のすべての導体パターンＰａ〜Ｐｈの相互間の絶縁状態が検査される。具体的には、上記の３回の検査のすべてにおいて、基準値を超える電流値が測定されなかったときに、制御部７は、すべての導体パターンＰａ〜Ｐｈの相互間が良好な絶縁状態であると判別して、検査対象基板１０を良品と判定して一連の検査処理を終了する。 Through the above three inspections, the insulation state between all the conductor patterns Pa to Ph on the inspection target substrate 10 is inspected. Specifically, when the current value exceeding the reference value is not measured in all the above three inspections, the control unit 7 is in a good insulating state between all the conductor patterns Pa to Ph. When it is determined that there is, the inspection target substrate 10 is determined to be a non-defective product, and a series of inspection processing is completed.

このように、この回路基板検査装置１による検査対象基板１０の検査方法では、（（Ｍ−１）＜ｌｏｇ_２Ｎ≦Ｍ（Ｍは整数））の条件を満たすＭ回（この例では、３回）の各電気的検査（例えば、上記の１回目の検査）において、接続ケーブル５の各信号線５ａ〜５ｈのうちの所定の向きで隣接して検査対象の一対の導体パターンＰａ〜Ｐｈに接続されている一対の信号線（例えば、信号線５ｂ，５ｃ）の一方（例えば、信号線５ｂ）を高電位および低電位のいずれか一方の電位（例えば、高電位）に接続すると共に一方の信号線に対して所定の向きとは逆向き側において隣接する他の信号線が存在するときには他の信号線（この例では、信号線５ａ）を上記のいずれか一方の電位（この例では、高電位）に接続し、かつ一対の信号線の他方（この例では、信号線５ｃ）を高電位および低電位のいずれか他方の電位（この例では、低電位）に接続すると共に他方の信号線に対して所定の向き側において隣接する他の信号線が存在するときには他の信号線（この例では、信号線５ｄ）を上記のいずれか他方の電位（この例では、低電位）に接続する。 As described above, in the method for inspecting the inspection target substrate 10 by the circuit board inspection apparatus 1, M times (in this example, 3 times) satisfying the condition of ((M−1) <log ₂ N ≦ M (M is an integer)). In each electrical inspection (for example, the first inspection described above), the signal lines 5a to 5h of the connection cable 5 are adjacent to each other in a predetermined direction in a pair of conductor patterns Pa to Ph to be inspected. One of a pair of signal lines (for example, signal lines 5b and 5c) (for example, signal line 5b) is connected to one of a high potential and a low potential (for example, high potential) and When there is another signal line adjacent to the signal line on the side opposite to the predetermined direction, the other signal line (in this example, the signal line 5a) is connected to one of the potentials (in this example, Other than a pair of signal lines (In this example, the signal line 5c) is connected to either the high potential or the low potential (in this example, the low potential), and another signal adjacent to the other signal line on the predetermined direction side. When a line is present, another signal line (in this example, the signal line 5d) is connected to one of the other potentials (in this example, a low potential).

したがって、この回路基板検査装置１による検査対象基板１０の検査方法によれば、Ｍ回の各電気的検査のすべてにおいて、上記の一方の信号線と、その一方の信号線に対して所定の向きとは逆向き側において隣接する他の信号線との間に線間浮遊容量が生じることがなく、また、上記の他方の信号線と、その他方の信号線に対して所定の向き側において隣接する他の信号線との間に線間浮遊容量が生じることがないため、絶縁検査に際して直流電圧を印加した際に、信号線５ａ〜５ｈ間の線間浮遊容量へのチャージに要する時間を十分に短縮することができる。これにより、直流電圧の印加を開始してから十分に短い時間だけ待機しただけで電流値を測定したとしても、線間浮遊容量のチャージに起因する電流値を検出して導体パターンＰａ〜Ｐｈ間に絶縁不良が生じているとの誤判定を招くことなく、結果として、十分に短時間で導体パターンＰａ〜Ｐｈの絶縁検査を行うことができる。 Therefore, according to the inspection method of the inspection target substrate 10 by the circuit board inspection apparatus 1, in all the M electrical inspections, the one signal line and a predetermined direction with respect to the one signal line are provided. The line stray capacitance is not generated between other signal lines adjacent to the other signal line on the opposite side to the other signal line, and adjacent to the other signal line on the predetermined direction side with respect to the other signal line. As a result, no stray capacitance is generated between other signal lines, so that a sufficient time is required to charge the stray capacitance between the signal lines 5a to 5h when a DC voltage is applied during an insulation test. Can be shortened. As a result, even if the current value is measured only by waiting for a sufficiently short time after starting the application of the DC voltage, the current value resulting from the charge of the floating capacitance between the lines is detected and the conductor patterns Pa to Ph are detected. As a result, the insulation inspection of the conductor patterns Pa to Ph can be performed in a sufficiently short time without causing an erroneous determination that an insulation failure has occurred.

また、この回路基板検査装置１による検査対象基板１０の検査方法では、Ｎ（Ｎは、２^Ｍで表される８以上の整数：この例は、Ｎ＝８）本の導体パターンＰａ〜Ｐｈを検査する際に、第Ｌ（Ｌは１からＭの各々：この例では、Ｍ＝３）の電気的検査において、２^{（Ｍ−Ｌ）}対（この例では、１対〜３対）の導体パターンを検査対象として各電気的検査を順不同で実行し、第Ｌ（Ｌは１）の電気的検査（例えば、上記の第１回目の検査）において、両端のＬの各信号線（この例では、信号線５ａ，５ｈ）を高電位および低電位のいずれか一方の電位（この例では、高電位）に接続すると共に残りの（Ｎ−２×Ｌ）本の各信号線（この例では、信号線５ｂ〜５ｇの６本）を２^{（Ｍ−Ｌ）}対の導体パターン（この例では、導体パターンＰａ，Ｐｂ、Ｐｃ，Ｐｄ、Ｐｅ，Ｐｆ、Ｐｇ，Ｐｈの４対の導体パターン）を検査可能に高電位および低電位のいずれかの電位に接続し、第Ｌ（Ｌは２から（Ｍ−１）の各々）の電気的検査（例えば、上記の第２回目の検査）において、両端において隣接する２^{（Ｌ−１）}本の各信号線（この例では、信号線５ａ，５ｂおよび信号線５ｇ，５ｈ）を上記のいずれか一方の電位（この例では、高電位）に接続すると共に残りの隣接する（Ｎ−２×２×（Ｌ−１））本の各信号線（この例では、信号線５ｃ〜５ｆの４本）を２^{（Ｍ−Ｌ）}対の導体パターン（この例では、導体パターンＰｂ，Ｐｃ、Ｐｆ，Ｐｇの２対の導体パターン）を検査可能に上記のいずれかの電位に接続し、第Ｌ（ＬはＭ）の電気的検査（例えば、上記の第３回目の検査）において、一方の端側で隣接する２^{（Ｌ−１）}本の各信号線（この例では、信号線５ａ〜５ｄの４本）を上記のいずれか一方の電位（この例では、高電位）に接続すると共に他方の端側で隣接する２^{（Ｌ−１）}本の各信号線（この例では、信号線５ｅ〜５ｈの４本）を高電位および低電位のいずれか他方の電位（この例では、低電位）に接続する。 Further, in the inspection method for the inspection target substrate 10 by the circuit board inspection apparatus 1, N (N is an integer of 8 or more represented by ^2M : N = 8 in this example) conductor patterns Pa to Ph. In the inspection, 2 ^(ML) pairs (1 to 3 pairs in this example) of conductors in the ^Lth electrical test (L is 1 to M each: M = 3 in this example) The electrical inspections are performed in random order with the pattern as the inspection target, and in the Lth (L is 1) electrical inspection (for example, the first inspection described above), the L signal lines at both ends (in this example, , The signal lines 5a and 5h) are connected to one of a high potential and a low potential (in this example, a high potential) and the remaining (N−2 × L) signal lines (in this example, the conductor pattern (this example six) of the signal lines 5b~5g ^{2 (M-L)} pair, the conductor patterns Pa, Pb 4 conductor patterns of Pc, Pd, Pe, Pf, Pg, and Ph) are connected to either a high potential or a low potential so that they can be inspected, and the Lth (L is from 2 to (M−1)) ) Electrical inspection (for example, the second inspection described above), 2 ^(L-1) signal lines adjacent to both ends (in this example, signal lines 5a and 5b and signal lines 5g and 5h). Are connected to any one of the above-described potentials (in this example, high potential) and the remaining adjacent (N−2 × 2 × (L−1)) signal lines (in this example, the signal line 5c). To 5f) 2 ^(ML) pairs of conductor patterns (in this example, two pairs of conductor patterns Pb, Pc, Pf, and Pg) are connected to any of the above potentials In the L-th electrical inspection (L is M) (for example, the third inspection described above), 2 ^(L-1) signal lines (four signal lines 5a to 5d in this example ⁾ adjacent to each other on the end side of the signal line are connected to one of the above potentials (high potential in this example). In addition, 2 ^(L-1) signal lines adjacent to each other on the other end side (in this example, four signal lines 5e to 5h) are connected to either the high potential or the low potential (in this example, Low potential).

したがって、この回路基板検査装置１による検査対象基板１０の検査方法によれば、Ｍ回の各電気的検査のすべてにおいて、信号線５ａ〜５ｈ間に生じる線間浮遊容量を十分に小さくすることができる。これにより、導体パターンＰａ〜Ｐｈの絶縁検査に要する時間を十分に短縮することができる。具体的には、例えば、８つの導体パターンＰａ〜Ｐｈを検査対象として、かつ各導体パターンＰａ〜Ｐｈ間の線間浮遊容量が互いに等しいＣ１としたときには、従来の検査装置では、１１×Ｃ１の線間浮遊容量をチャージする充電時間を要していたのに対して、この回路基板検査装置１では、７×Ｃ１の線間浮遊容量をチャージする充電時間まで短縮することができる。なお、検査対象の導体パターンの数が多くなればなるほど、充電時間を短縮することができるのは勿論である。 Therefore, according to the inspection method of the inspection target substrate 10 by the circuit board inspection apparatus 1, the inter-line stray capacitance generated between the signal lines 5a to 5h can be sufficiently reduced in all the M electrical inspections. it can. Thereby, the time required for the insulation inspection of the conductor patterns Pa to Ph can be sufficiently shortened. Specifically, for example, when eight conductor patterns Pa to Ph are to be inspected and the line-to-line stray capacitances between the conductor patterns Pa to Ph are equal to each other, C1 is 11 × C1 in the conventional inspection apparatus. In contrast to the time required for charging the floating capacitance between the lines, the circuit board inspection apparatus 1 can reduce the charging time to charge the floating capacitance between 7 × C1. Of course, as the number of conductor patterns to be inspected increases, the charging time can be shortened.

なお、本発明は、上記の構成および方法に限定されない。例えば、導体パターンＰａ〜Ｐｈの８つを検査対象とする３回の電気的検査時における各回毎の高電位および低電位のいずれかに対する信号線５ａ〜５ｈの接続形態は、上記のように例示した接続形態に限定されない。例えば、上記の第３回目の電気的検査（図４参照）を最初に実行すると共に上記の第１回目（図２参照）の電気的検査を最後に実行する構成や、上記の第２回目の電気的検査（図５参照）を最初に実行すると共に上記の第１回目の電気的検査（図２参照）を最後に実行する構成を採用することができる。このように、本発明における第Ｌの電気的検査や第Ｍの電気的検査を実行する順序を適宜変更した（つまり順不同とした）としても、本発明のように信号線５ａ〜５ｈを高電位および低電位に接続することによって、Ｍ回の電気的検査の各回毎の線間浮遊容量を十分に小さくすることができる結果、絶縁検査に要する時間を十分に短縮することができる。 In addition, this invention is not limited to said structure and method. For example, the connection form of the signal lines 5a to 5h for each of the high potential and the low potential at the time of three electrical inspections in which eight conductor patterns Pa to Ph are inspected is exemplified as described above. It is not limited to the connected form. For example, a configuration in which the third electrical inspection (see FIG. 4) is first performed and the first electrical inspection (see FIG. 2) is performed last, or the second electrical inspection is performed. It is possible to employ a configuration in which the electrical inspection (see FIG. 5) is executed first and the first electrical inspection (see FIG. 2) is executed last. As described above, even if the order in which the L-th electrical test and the M-th electrical test are performed in the present invention is changed as appropriate (that is, in no particular order), the signal lines 5a to 5h are set to the high potential as in the present invention. By connecting to a low potential, the stray capacitance between the lines in each of the M electrical inspections can be sufficiently reduced, so that the time required for the insulation inspection can be sufficiently shortened.

また、プローブ３ａ〜３ｈを備えた回路基板検査装置１について説明したが、本発明における検査装置の構成はこれに限定されず、例えば、検査対象基板に配設された接続コネクタに対して、接続ケーブル５の一端部に設けた接続コネクタを挿入して検査対象基板上の導体パターンと接続ケーブル５とを接続して電気的検査を実行する構成を採用することができる。また、８（２^３）本の導体パターンＰａ〜Ｐｈを検査対象とする例について説明したが、これに限らず、より多くの本数の（例えば２^４，２^５，２^６等）導体パターンを検査対象とすることができる。 Moreover, although the circuit board inspection apparatus 1 provided with the probes 3a-3h was demonstrated, the structure of the inspection apparatus in this invention is not limited to this, For example, it connects with respect to the connection connector arrange | positioned at the test object board | substrate. It is possible to adopt a configuration in which a connection connector provided at one end of the cable 5 is inserted to connect the conductor pattern on the board to be inspected and the connection cable 5 to perform electrical inspection. Further, although an example in which 8 (2 ³ ) conductor patterns Pa to Ph are inspected has been described, the present invention is not limited thereto, and a larger number of conductor patterns (for example, 2 ⁴ , 2 ⁵ , 2 ^6, etc.) It can be the subject of inspection.

具体的には、例えば、２^４＝１６本の導体パターンを検査対象とした場合、本発明のＭ回の検査として、４回の電気的検査を実行する。この際には、本発明における第Ｌ（Ｌ＝１）の検査時には、本発明における切替え処理として、測定ケーブル５の各信号線を端部側から順に「Ｈ、Ｌ、Ｌ、Ｈ、Ｈ、Ｌ、Ｌ、Ｈ、Ｈ、Ｌ、Ｌ、Ｈ、Ｈ、Ｌ、Ｌ、Ｈ（Ｈは高電位、Ｌは低電位を表す）」のように接続し、本発明における第Ｌ（Ｌ＝２から（Ｍ−１）の各々：例えば、Ｌ＝２）の検査時には、本発明における切替え処理として、各信号線を端部側から順に「Ｈ、Ｈ、Ｌ、Ｌ、Ｌ、Ｌ、Ｈ、Ｈ、Ｈ、Ｈ、Ｌ、Ｌ、Ｌ、Ｌ、Ｈ、Ｈ」のように接続し、本発明における第Ｌ（Ｌ＝２から（Ｍ−１）の各々：例えば、Ｌ＝３）の検査時には、本発明における切替え処理として、各信号線を端部側から順に「Ｈ、Ｈ、Ｈ、Ｈ、Ｌ、Ｌ、Ｌ、Ｌ、Ｌ、Ｌ、Ｌ、Ｌ、Ｈ、Ｈ、Ｈ、Ｈ」のように接続し、本発明における第Ｌ（Ｌ＝Ｍ：この例では、Ｌ＝４）の検査時には、本発明における切替え処理として、各信号線を端部側から順に「Ｈ、Ｈ、Ｈ、Ｈ、Ｈ、Ｈ、Ｈ、Ｈ、Ｌ、Ｌ、Ｌ、Ｌ、Ｌ、Ｌ、Ｌ、Ｌ」のように接続することで、各電気的検査時において信号線の間に生じる線間浮遊容量を十分に小さくすることができる。 Specifically, for example, when 2 ⁴ = 16 conductor patterns are to be inspected, four electrical inspections are executed as M inspections according to the present invention. At this time, at the time of the L-th (L = 1) inspection in the present invention, as a switching process in the present invention, each signal line of the measurement cable 5 is “H, L, L, H, H, L, L, H, H, L, L, H, H, L, L, and H (H represents a high potential and L represents a low potential) ”. To (M-1): For example, at the time of inspection of L = 2), as a switching process in the present invention, each signal line is sequentially changed to “H, H, L, L, L, L, H, H, H, H, L, L, L, L, H, H ”, and the Lth inspection (each of L = 2 to (M−1): for example, L = 3) in the present invention. Sometimes, as a switching process in the present invention, each signal line is “H, H, H, H, L, L, L, L, L, L, L, L, H, H, H, H in order from the end side. ” In the L-th inspection (L = M: in this example, L = 4) according to the present invention, as a switching process according to the present invention, each signal line is sequentially switched from the end side to “H, H, H, H, H , H, H, H, L, L, L, L, L, L, L, L ”, the line stray capacitance generated between the signal lines at the time of each electrical inspection can be sufficiently increased. Can be small.

回路基板検査装置１の構成を示すブロック図である。1 is a block diagram showing a configuration of a circuit board inspection device 1. FIG. 回路基板検査装置１による第１回目の絶縁検査時における各信号線５ａ〜５ｈの各電位への接続形態と、信号線５ａ〜５ｈ間に生じる線間浮遊容量Ｃ１〜Ｃ４との関係について説明するための説明図である。The relationship between the connection form of each signal line 5a to 5h to each potential and the inter-line stray capacitances C1 to C4 generated between the signal lines 5a to 5h in the first insulation inspection by the circuit board inspection apparatus 1 will be described. It is explanatory drawing for. 回路基板検査装置１による第２回目の絶縁検査時における各信号線５ａ〜５ｈの各電位への接続形態と、信号線５ａ〜５ｈ間に生じる線間浮遊容量Ｃ１１，Ｃ１２との関係について説明するための説明図である。The relationship between the connection form of the signal lines 5a to 5h to each potential and the inter-line stray capacitances C11 and C12 generated between the signal lines 5a to 5h in the second insulation inspection by the circuit board inspection apparatus 1 will be described. It is explanatory drawing for. 回路基板検査装置１による第３回目の絶縁検査時における各信号線５ａ〜５ｈの各電位への接続形態と、信号線５ａ〜５ｈ間に生じる線間浮遊容量Ｃ２１との関係について説明するための説明図である。For explaining the relationship between the connection form of each signal line 5a to 5h to each potential and the inter-line stray capacitance C21 generated between the signal lines 5a to 5h in the third insulation inspection by the circuit board inspection apparatus 1 It is explanatory drawing. 従来の検査装置による第１回目の絶縁検査時における各信号線５ａｘ〜５ｈｘの各電位への接続形態と、信号線５ａｘ〜５ｈｘ間に生じる線間浮遊容量Ｃ１ｘ〜Ｃ７ｘとの関係について説明するための説明図である。To describe the relationship between the connection form of each signal line 5ax to 5hx to each potential and the inter-line stray capacitances C1x to C7x generated between the signal lines 5ax to 5hx in the first insulation test by the conventional inspection apparatus. It is explanatory drawing of. 従来の検査装置による第２回目の絶縁検査時における各信号線５ａｘ〜５ｈｘの各電位への接続形態と、信号線５ａｘ〜５ｈｘ間に生じる線間浮遊容量Ｃ１１ｘ〜Ｃ１３ｘとの関係について説明するための説明図である。In order to explain the relationship between the connection form of each signal line 5ax to 5hx to each potential and the inter-line stray capacitance C11x to C13x generated between the signal lines 5ax to 5hx in the second insulation inspection by the conventional inspection apparatus. It is explanatory drawing of. 従来の検査装置による第３回目の絶縁検査時における各信号線５ａｘ〜５ｈｘの各電位への接続形態と、信号線５ａｘ〜５ｈｘ間に生じる線間浮遊容量Ｃ２１ｘとの関係について説明するための説明図である。Explanation for explaining the relationship between the connection form of the signal lines 5ax to 5hx to each potential and the inter-line stray capacitance C21x generated between the signal lines 5ax to 5hx in the third insulation test by the conventional inspection apparatus. FIG.

Explanation of symbols

１回路基板検査装置
２プローブ保持部
３ａ〜３Ｎプローブ
４測定部
５接続ケーブル
５ａ〜５Ｎ信号線
６切替部６
６ａ〜６Ｎスイッチ
７制御部
１０検査対象基板
Ｃ１〜Ｃ４，Ｃ１１，Ｃ１２，Ｃ２１線間浮遊容量
Ｄ１測定値
Ｄ２検査用基準データ
Ｐａ〜Ｐｈ導体パターン
Ｓ１，Ｓ２制御信号 DESCRIPTION OF SYMBOLS 1 Circuit board inspection apparatus 2 Probe holding part 3a-3N Probe 4 Measuring part 5 Connection cable 5a-5N Signal line 6 Switching part 6
6a to 6N switch 7 control unit 10 inspection target board C1 to C4, C11, C12, C21 inter-line floating capacitance D1 measured value D2 inspection reference data Pa to Ph conductor pattern S1, S2 control signal

Claims

A measurement unit for measuring an electrical parameter by applying a DC voltage between the conductor patterns to be inspected via a flat connection cable in which a plurality of signal lines are arranged in parallel along a predetermined direction; and each of the signal lines And a switching unit that switches connection between a high potential and a low potential, and when inspecting N (N is an integer of 4 or more) conductor patterns, the switching unit is controlled to The signal line connection is switched M times satisfying the condition of ((M−1) <log ₂ N ≦ M (M is an integer)), and each conductor pattern connected to the high potential in each switched state. And a control unit that causes the measurement unit to measure the electrical parameter between each of the conductor patterns connected to the low potential and to perform an electrical inspection on the N conductor patterns,
The control unit controls the switching unit in each of the M electrical inspections and is connected to the pair of conductor patterns to be inspected adjacent to each other in the predetermined direction among the signal lines. One of the pair of signal lines is connected to one of the high potential and the low potential, and another signal line adjacent to the one signal line on the side opposite to the predetermined direction is When present, the other signal line is connected to one of the potentials, and the other of the pair of signal lines is connected to the other potential of the high potential and the low potential, and the other signal line is connected. In contrast, when there is another signal line adjacent on the predetermined direction side, the other signal line is connected to the other potential.

When the N (N is an integer greater than or equal to 8 represented by 2 ^M ) pieces of the conductor patterns are inspected, the control unit performs the Lth (L is 1 to M) in the electrical inspection. 2 ^(ML) pairs of the conductor patterns as inspection targets, and the electrical inspections are performed in random order. In the L-th electrical inspection (L is 1), the switching unit is controlled to The L signal lines are connected to any one of the potentials, and the remaining (N−2 × L) signal lines can be inspected for the 2 ^(ML) pairs of conductor patterns. In the L-th electrical inspection (L is from 2 to (M-1)), the switching unit is controlled to connect the two ^(L-1) pieces of adjacent ones at both ends. Each signal line is connected to one of the potentials and the remaining adjacent (N−2 × 2 × (L -1) The signal lines of the two are connected to any one of the potentials so that the 2 ^(ML) pairs of conductor patterns can be inspected. In the L-th electrical inspection (L is M), The switching unit is controlled to connect 2 ^(L-1) signal lines adjacent on one end side to any one of the potentials, and 2 ^(L-1) lines adjacent on the other end side. The inspection apparatus according to claim 1, wherein the signal lines are connected to the other potential.

A measurement process for measuring an electrical parameter by applying a DC voltage between conductor patterns to be inspected via a flat connection cable in which a plurality of signal lines are arranged in parallel along a predetermined direction; And the switching process for switching the connection between one of the high potential and the low potential and performing electrical inspection on N (N is an integer of 4 or more) conductor patterns, The switching process is performed M times satisfying the condition of ((M−1) <log ₂ N ≦ M (M is an integer)), and each conductor connected to the high potential as the measurement process in each switched state An inspection method for measuring the electrical parameters between a pattern and each conductor pattern connected to the low potential,
In each of the M electrical inspections, as the switching process, one of a pair of signal lines connected to the pair of conductor patterns to be inspected adjacent to each other in the predetermined direction among the signal lines. When there is another signal line that is connected to one of the high potential and the low potential and is adjacent to the one signal line in the direction opposite to the predetermined direction, the other signal line Is connected to one of the potentials, and the other of the pair of signal lines is connected to the other potential of the high potential and the low potential, and the predetermined direction side with respect to the other signal line In the inspection method, when there is another signal line adjacent to the other signal line, the other signal line is connected to the other potential.

When the N (N is an integer greater than or equal to 8 represented by 2 ^M ) pieces of the conductor patterns are inspected, 2 ^(ML ) in the Lth (L is 1 to M) electrical inspection. ^{) The} electrical inspections are performed in random order with the pair of conductor patterns as inspection targets. In the L-th electrical inspection (L is 1), the L signal lines at both ends are used as the switching process. Connect to any one of the potentials and connect the remaining (N−2 × L) signal lines to any one of the potentials so that the 2 ^(ML) pairs of conductor patterns can be inspected. In the L-th electrical inspection (where L is from 2 to (M−1)), the two ^(L−1) signal lines adjacent at both ends are connected to one of the potentials as the switching process. And the remaining adjacent (N−2 × 2 × (L−1)) signals. The wire is connected to any one of the potentials so that the 2 ^(ML) pairs of conductor patterns can be inspected, and adjacent to one end side as the switching process in the L-th (L is M) electrical inspection. 2 ^(L-1) signal lines connected to one of the potentials, and 2 ^(L-1) signal lines adjacent on the other end are connected to the other potential. The inspection method according to claim 3, wherein the inspection method is connected to.