JP4764036B2 - Method and circuit for performing correlated double subsampling of pixels in an active pixel sensor array - Google Patents

Description

  The present invention relates to an image sensor, and more particularly to a correlated double sub-sampling (CDSS) of pixels dynamically selected in an N × M pixel region of an active pixel sensor (APS) array (sub-sampling). And subsequent correlated double sampling).

  The most common image pickup device since the mid 1980's was a CCD (Charge-Coupled Device). With the development of the semiconductor industry, the CCD system developed rapidly and eventually came to be mounted on small high-performance cameras. The CCD is an important image pickup device, but the CCD sensor which is the core of the digital camera has a problem that it consumes a relatively large amount of energy and is not suitable for high-speed operation.

  From such a viewpoint, a large CIS (CMOS Image Sensor) capable of realizing a high resolution of several million pixels or more has been developed. Besides being highly integrated and capable of arranging a large number of pixels and allowing high-speed data scanning, CIS has a lower power consumption (about the power consumed by the CCD) compared to standard CCDs currently in use. 1/5) has a significant advantage.

  Another advantage of CIS is its low manufacturing cost. That is, relatively large CIS can be supplied at low cost. Since CIS can be manufactured on the same chip in a process such as MOSFET (Metal Oxide Field Effect Transistor) or CMOS (Complementary Metal Oxide Semiconductor) transistor, the signal processing circuit reduces the number of connecting lines. Can be formed. Furthermore, since the CIS is driven at a voltage lower than that of the CCD and the peripheral circuits can be arranged on the same chip, the size can be reduced. Therefore, CIS is expected as a core image sensing device (substitute for CCD solid-state imaging device) in the future digital image system with a wide range of application fields.

  There are many differences in the video data scanning method between the CCD and the CIS. For example, at 3 million pixel resolution, a CCD sensor continuously scans 3 million analog charges, and amplification that converts the charges into electrical signals typically occurs only after the last pixel is scanned To do. On the other hand, the CIS, that is, the APS as shown in FIG. 1, has one amplifying element (a transistor or other converter that converts electric charges into an electrical signal) per pixel. Therefore, since CIS performs signal amplification for each pixel, the transmission operation can be reduced, and further high-speed data scanning can be performed with lower energy consumption.

CDS (Correlated Double Sampling)
A CIS charge-voltage converter basically includes a voltage follower (amplification transistor) of one stage or more, a capacitor, and a switch for resetting the capacitor voltage. In the simplest video system, the switch closes at the beginning of each pixel reading to reset the capacitor voltage as well as the output level. After the pixel charge packet is transferred to the capacitor, it changes to a voltage and its output signal is represented as the corresponding pixel value. A component such as a switch has its own constant error conductivity, thus precharging the capacitor to an unspecified constant value, thus causing an error in the output signal. Such precharge uncertainty can be compensated by CDS. In such a manner, the output signal is sampled twice for each pixel. That is, once after the capacitor is precharged and once after the pixel charge packets are combined. Such a difference between the two values can eliminate the noise component caused by the switch.

  The CDS method is a method devised to improve the SNR (Signal to Noise Ratio) of an integrated image sensor. By subtracting the pixel black level, reference level, or reset level from the signal that is substantially induced by light, static FTP (Fixed Pattern Noise) and various forms of temporal noise Effectively removed from the APS array output.

  FIG. 2 illustrates a typical CDS circuit (eg, included in the CDS & ADC block of FIG. 1) that can be applied to average four identical color CDS sampled pixel values in a 4 × 4 pixel region of an APS array. FIG. Two rows containing 4 pixels that are CDS sampled and averaged are selected by the row driver of FIG.

  In the APS array, the photocharge is collected by a photodiode (PD) and stored for each pixel in a single capacitance C within it. The photocharge is read from the capacitor as a voltage (V = Q / C) by the capacitor. The signal voltage Vs = Qs / C photoelectrically changed by the CDS process is compared with the black level, the reference level, or the reset level voltage Vr = Qr / C. Vr is obtained when the channel is turned off and all charges of C are at a fixed potential, that is, before the generation of the photoelectrically changed signal voltage. Therefore, the final output voltage V = Vs−Vr = (Qs−Qr) / C is obtained for each pixel. The CDS process can be performed on-chip with circuitry fabricated on the same chip as the APS array as in FIG. 1, or can be by “off-chip CDS”. The CDS process typically requires one memory (eg, one capacitor for storing charge) and one subtractor for each pixel column that is CDS sampled.

  In the circuit of FIG. 2, four capacitors 50a, 51a, 50b, 51b are provided to store four values from four pixels, and switches 2, 21a, 21b are “imaged” by four stored charges. Provided to perform an “averaging process”. Each of the capacitors 50a, 51a, 50b, 51b stores one charge (Qs-Qr) for outputting a final output voltage V (V = Vs-Vr) indicating analog image data of one pixel. Provided. Each of the switches 21a, 21b is provided for averaging together two stored pixel values obtained sequentially from different rows of pixels in the same column. For example, when each of the same size capacitors 50a and 51a stores pixel values sampled from one first column, if the switch 21a is closed, the charges of the two capacitors are combined and equalized. The two capacitors 50a and 51a are equally distributed. In this way, sampled pixel values from different rows in the same column are averaged. A switch 2 is provided to average together pixel values sampled from two different columns (eg, first and third columns). For example, when capacitors 50a, 51a, 50b, 51b of the same size store sampled pixel values averaged from the pixels of the first and third columns, switches 2, 21a and 21b are closed. For example, the charges stored in the four capacitors 50a, 51a, 50b, 51b are combined and averaged, and distributed to the four capacitors. As such, pixel values sampled from 4 pixels having the same color from 2 rows and 2 columns are averaged. If the switches 21a, 21b are opened and the switch 2 is closed, the circuit of FIG. 2 averages only two pixel values from two different columns in the same row stored in the capacitors 50a, 50b. .

  Each final averaged CDS sampled pixel value is sequentially transmitted to an analog-to-digital converter (not shown) via amplifiers 54a, 54b, column select switch (transistor) 20, and common output line 30. Is done.

  FIG. 2 illustrates CDS sampling of pixels from one of two columns (eg, first and third columns) via sample hold switches 42a and 42b via respective vertical select lines CL1 and CL3. Two identical circuits (a, b) connected to each other. A sample and hold capacitor 44 for holding reset or signal charge output from one pixel of the APS array is connected to a vertical selection line by a sample and hold switch 42. Each of the reference voltage sources 46a, 46b is connected in series to each of the sample and hold capacitors 44a, 44b. The analog charge subtracter includes sample and hold capacitors 44a and 44b, an amplifier (for example, a non-inverting buffer) 48, and CDS capacitors 50a and 50b. The output node of the subtracter (the output terminal of the CDS capacitor 50) is connected to the input terminal of the output amplifier 54. The electric charge held in the sample hold capacitor 44 is copied to the CDS capacitor 50 when the clamp switch 52 is closed. This is because the same voltage (or charge) as the output voltage of the non-inverting amplifier 48 corresponding to the amount of charge stored by the sample and hold capacitor 44 can be induced to be stored in the CDS capacitor 50. The CDS capacitor 50 is then in a floating state by opening the clamp switch 52, at which time the voltage / charge copied from the sample and hold capacitor 44 is stored.

  As such, the first charge (signal charge) Qs from a certain pixel initially received and held by the sample and hold capacitor 44 is copied and stored in the CDS capacitor 50, and then the second charge from the same pixel. Two charges (reset charges) Qr are received and stored by the sample and hold capacitor 44.

  In this way, the signal voltage VS from one pixel is first applied to the input terminal of the subtracter (node of the sample hold capacitor 44) via the selection line CL1, and if the clamp switch 52 is closed, the pixel The signal voltage VS from 1 charges not only the sample and hold capacitor 44 but also the CDS capacitor 50. Next, when the clamp switch 52 is opened, the reset voltage VR is output from the same pixel, input to the input terminal of the analog subtractor, and held by the sample hold capacitor 44. As a result, a signal VS−VR corresponding to the difference between the signal voltage VS and the reset voltage VR is generated at the output terminal of the analog subtractor, that is, the output terminal of the CDS capacitor 50. As such, the fixed pattern noise reflecting both the signal voltage VS and the reset voltage VR is removed, and CDS sampled analog pixel data of one pixel is obtained. CDS sampled analog pixel data is output via switch 20, amplifier 54 and common output line 30 when switch 20 is closed.

  Each of the capacitors 50a, 51a, 50b, and 51b stores a charge Qs / Qr that outputs a final output voltage V = Vs−Vr indicating analog image data of one pixel.

  The difference signal VS-VR is held by the CDS capacitor 50 so that each of the CDS capacitors 50a, 51a, 50b, 51b stores four global difference signals VS-VR for four CDS sampled pixels. To do. However, while changing the electric charge held in the sample hold capacitor 44, that is, the output voltage of the non-inverting amplifier 48, the entire difference is applied to one CDS capacitor 50 (for example, one of 50a, 51a, 50b, 51b). It is difficult to hold a charge that accurately indicates the signal VS-VR. In practice, the CDS capacitor 50 does not store the total difference signal VS-VR due to Qs-Qr, but rather the charge from a certain pixel (for example, of the reset charge Qr or the signal charge Qs received from the pixel, Only the voltage associated with any one charge) is stored.

  As such, before the reset charge Qr of 4 pixels is received and stored by any one of the two sample and hold capacitors 44a and 44b, the image signal charge Qs of each of the 4 pixels is stored in the CDS capacitor. The four floating signal charges Qs first stored in one of 50a, 51a, 50b, 51b and stored in the CDS capacitors 50a, 51a, 50b, 51b are combined by the CDS capacitors and distributed separately. However, the resulting output by amplifiers 54a, 54b is based on the two reset charges stored in the two sample and hold capacitors 44a, 44b. As such, the resulting output of the subtractor (output by amplifier 54) is not a mathematical average of the four CDS sampled pixel values VS-VR output sequentially from the circuit of FIG. In this case, only the two received reset charges / voltages are averaged with the two stored signal charges / voltages.

  As described above, in the operation of the circuit shown in FIG. 2, the averaged pixel representing the four pixels includes an error caused by the fixed pattern noise component.

  The ability to subsample an image captured by a digital camera with an APS array is useful when trying to achieve a reduced resolution mode. For example, when trying to reduce the bit rate in the moving image capture mode, or when trying to display the video with a reduced resolution. Sub-sampling in the digital domain after analog-to-digital conversion requires a large amount of memory and processing time that consumes additional power.

  A circuit such as FIG. 2 and other similar circuits for performing pixel sub-sampling in an analog domain averaging operation are used for CDS sampled pixels of the buyer pattern, ie, for each color in the 4 × 4 pixel region. It is applied to average 4 pixels for subsampling.

  Accordingly, a technical problem to be achieved by the present invention is to provide an image sensor and a method for improving display quality by analogly averaging video signals output from pixels when driving in a sub-sampling mode. .

  An image sensor according to the present invention for achieving the above technical problem is composed of a plurality of pixels arranged in rows and columns, and each column pixel stores at least two reset charges. A switch is connected to the data capacitor and at least two image signal data capacitors for storing at least two image charges.

The image sensor is an APS array having N ² pixels arranged in N rows and N columns, in which each pixel outputs a reset voltage and an image signal voltage, and a first capacitor resets the reset voltage of the first pixel. Storing as a charge, storing a reset voltage of the second pixel as a second charge with a second capacitor, and combining the first and second charges into an averaged reset charge. A sub-sampling method is performed.

The sub-sampling method is a method of sub-sampling pixels in the APS array, in the APS array, the method comprising storing the L ² analog pixel reset data charges received from L ² pixels in the first set of N ² capacitor, wherein in the APS array, characterized in that it comprises the steps of storing the L ² analog pixel image signal data charges received from L ² pixels in the second set of N ² capacitor, a. L is an integer between 1 and N. The sub-sampling method is characterized by further comprising performing a first averaging operation with conserved L ² analog pixel reset data charges to said first set of N ² capacitor. The sub-sampling method is characterized by further comprising performing a second averaging operation with conserved L ² analog pixel image signal data charges to said second set of N ² capacitor.

  The image sensor may further include an averaging circuit that generates a reset charge averaged by performing a first averaging operation using the at least two reset charges. The averaging circuit may generate an averaged image charge by performing a second averaging operation using the at least two image charges. The first and second averaging operations are performed in the analog domain. The image sensor includes an analog subtractor that generates a differential voltage by subtracting the averaged reset charge from the averaged image charge, and an analog-digital converter that converts the differential voltage from analog to digital ( (Analog to Digital Converter: hereinafter referred to as ADC).

A sub-sampling method according to another embodiment of the present invention is a pixel array in which each pixel is arranged in a plurality of rows and a plurality of columns that output a reset voltage and an image signal voltage. output analog reset data charges from ^2), for example, the method of synthesizing a conserved L ² reset data charges to the first set of storage capacitor together analog image signal data output from the plurality of pixels (L ²⁾ Combining charges, eg, L ² image signal data charges stored in a second set of storage capacitors, with each other. Instead of reset and image signal charge from one pixel, the combined (averaged) reset data charge and the combined image signal data charge are used to perform a CDS operation, thereby A difference voltage (VS-VR) is generated that indicates accurate mathematical averaging for the L ² pixels being averaged of the same color.

  The accuracy of the averaging (sub-sampling) function performed in the embodiment of the present invention is the fact that four identically colored CDS sampled values (charge quantized as Qs-Qr) within the 4 × 4 pixel region of the buyer pattern array. ) Can be confirmed by whether or not the mathematical average satisfies the following formula. Assume that every capacitor in the subtracter has a capacitance C and is charged with respect to the same reference voltage Vref.

The exact average of the four CDS sampled pixel values that are averaged (subsampled) to each other by the above equation is from the combined value Q _S11 + Q _S13 + Q _S31 + Q _S33 of the four signal charges from the four pixels. It is obtained by subtracting the combined value Q _R11 + Q _R13 + Q _R31 + Q _R33 of four reset charges from four pixels. The combined value of the four signal charges is split at 4 before subtracting the combined reset charge, and the split value is equally distributed among the four capacitors with the same capacitance. Similarly, the combined value of the four reset charges is split at 4 before subtracting from the combined signal charge, and the split value is equally distributed among the four capacitors with the same capacitance. Thus, the method for obtaining the average value of the CDS sampled pixels is to combine and divide the four related reset charges to obtain the average reset charge Q _{RAVG and} to obtain the average signal charge Q _SAVG 4 _Combining and dividing two related signal charges, and subtracting the average reset charge Q _RAVG from the average signal charge Q _SAVG to perform one CDS sampling operation (subtraction operation). Such a general method is described herein as CDSS. This is because the result of such a method is an accurate average for the four CDS sampled pixels and is an accurately subsampled pixel value.

  In the embodiment of the present invention, a CDSS with a sub-sampling rate B of 4 consists of three stages as follows. First, two pairs of reset voltages (charges) are averaged in the column direction, and two pairs of signal voltages (charges) are averaged in the column direction. The two pairs of average reset voltages are then averaged in the row direction to obtain a final average reset voltage, and the two pairs of average signal voltages are averaged in the row direction to obtain a final average signal voltage. Finally, the final average reset signal voltage is subtracted from the final average image signal voltage using one analog subtractor. In the embodiment of the present invention, the averaging of the charge and the like is performed by combining the charge stored in the four capacitances C into a large capacitance 4C that is eventually one, and dividing the charge into four capacitances having the same capacitance C. Including doing.

  An image sensor according to another embodiment of the present invention includes a pixel array arranged in a plurality of rows and a plurality of columns, and an operation is performed in which each pixel of each column pixel is connected to an averaging unit. Each averaging unit stores first and second storage capacitors for storing analog reset data from the first pixel and the second pixel, and analog image signal data from the first pixel and the second pixel. 3 and a fourth storage capacitor.

  The image sensor and its sub-sampling method according to the present invention can directly and accurately sub-sample a plurality of pixels in the APS, thereby removing static fixed pattern noise.

For a full understanding of the invention and the operational advantages thereof and the objects achieved by the practice of the invention, reference should be made to the accompanying drawings illustrating preferred embodiments of the invention and the contents described in the accompanying drawings. There must be.
Hereinafter, the present invention will be described in detail by explaining preferred embodiments of the invention with reference to the accompanying drawings. The same reference numerals attached to the drawings indicate the same members.

  FIG. 3 is a block diagram illustrating a CIS including an APS array and an averaging and comparing unit (ACU) that performs CDSS according to an embodiment of the present invention. FIG. 4 is a circuit diagram showing each pixel structure in the CIS APS array of FIG.

  Referring to FIGS. 3 and 4, the APS array includes a plurality of well-known pixel circuits such as the pixel circuit of FIG. This pixel circuit sequentially outputs a VR (reset signal) voltage and a VS (image signal) voltage. Each pixel in the APS array typically includes a photoelectric converter, such as the photodiode PD of FIG. As is well known, the row driver circuit sequentially selects odd row pairs (1, 3,...) And then even row pairs (2, 4,...) During CDSS according to one embodiment of the present invention. , ...) is selected. In order to selectively activate one row among the plurality of lines, an active row selection signal SEL is transmitted to each row.

To read the charge or voltage stored in the capacitance present in the photodiode PD of each pixel, the switch T _TX controlled by the signal _TX is closed. The switch T _TX is generally opened during the reset operation. If the switch T _TX is closed together with the reset switch T _RX , the diffusion region of the photodiode PD of each pixel can also be reset. The reset signal RX is used to control the switch T _RX, and as is well known, the switch T _RX used with the switch T _TX controlled by the signal TX is stored in the capacitance present in the photodiode PD. Reset the charge or voltage to the reset level.

The transistor T _AMP is a voltage follower amplifier that changes the electric charge or voltage stored in the capacitance present in the photodiode PD to the corresponding voltage or current, and transmits it to the ACU of FIG. 3 for storage.

The switch T _RX controlled by the reset signal RX is closed at the initial reading of each pixel, and resets the charge and voltage stored in the capacitance present in the photodiode PD. When the switch _TSEL is closed by the reset charge or voltage of the capacitance present in the photodiode PD, the output node OUT is represented by the output voltage level VR. If the APS array is exposed to the actual image (light), the photodiode PD and the associated capacitor of each pixel cause an image or signal charge / voltage that corresponds to the intensity of light incident on the photodiode PD. When the switch T _TX is closed and the switch T _RX is opened, the image signal, which is a substantially photoelectrically converted signal, is amplified by the amplifier T _AMP and when the switch T _SEL is closed, the capacitor of the ACU of FIG. And transmitted as an image signal voltage VS.

  FIG. 5 is a block diagram showing a buyer pattern array of color sensing pixels in the APS array of FIG. 3 and its output. The buyer pattern is realized by a CFA (Color Filter Array) of the buyer pattern coupled onto the optical elements in the APS array. In the present invention, four pixels of the same color (for example, red pixels R11, R13, R31, R33) in the 4 × 4 pixel region are averaged and CDSSed as in the pixel region in the thick line in FIG. . As such, a set of four pixels that are CDSS is typically composed of pixels having the same color from the same two rows and the same two columns. For example, red pixels R11, R13, R31, and R33 are CDSS sampled, and green pixels G12, G14, G32, and G34 are CDSS sampled. Thereafter, the green pixels G12, G14, G32, G34 are CDSS sampled, and the blue pixels B22, B24, B42, B44 are CDSS sampled. As such, the CDSS result for four sets of pixels of the same color is four averaged pixel values corresponding to red, blue, and green, respectively. Therefore, performing CDSS for a certain pixel region of the APS array effectively sub-samples in the analog domain to compensate for static fixed pattern noise and various forms of temporal noise.

  Row selection signals SEL1 and SEL3 correspond to the first and third rows, which are activated sequentially. When each of the row selection signals is activated, every pixel in the activated row first reads the respective reset voltage VR and then reads the substantial image signal voltage VS (timing diagrams of FIGS. 8A and 8B). See). As shown in FIG. 5, in the pixel of the first column, the signals VR11 and VS11 are output from the red filtered pixel R11, and then the signals VR31 and VS31 are output from the red filtered pixel R31. On the other hand, in the pixel of the third column, the signals VR13 and VS13 are output from the red filtered pixel R13, and then the signals VR33 and VS33 are output from the red filtered pixel R33. Here, it is assumed that the first row is activated first, but the third row may be activated first. Although not shown in FIG. 5, as shown in FIG. 6, the signals VR12 and VS12 are output from the green-filtered pixel G12 and then the green-filtered pixel G32, as shown in FIG. Signals VR32 and VS32 can be output. In the fourth column, the signals VR14 and VS14 can be output from the green-filtered pixel G14, and then the signals VR34 and VS34 can be output from the green-filtered pixel G34. The pixel values of the second row and the fourth row are also output after the pixel values of the first row and the third row are both CDSS sampled.

FIG. 6 is a block diagram illustrating switching connections between a plurality of ACUs that perform CDSS in the CIS of FIG. Each pixel in the column of the APS array is connected to the vertical transmission line via a respective selection switch T _SEL, it is also connected to ACU via the vertical transmission line. Thereby, as shown in FIG. 6, four adjacent ACUs correspond to four adjacent 1, 2, 3, 4 columns of the APS array pixel. During a read operation, ACU-1 and ACU-3 receive analog pixel data received from the same color pixel. For example, first receive from red filtered pixels R11 and R13, then receive from R31 and R33. It also receives in the same way from green filtered pixels or blue filtered pixels. Thereby, ACU-1 and ACU-3 are coupled together via a first averaging switch Savg in order to effectively average the received analog pixel data associated with the same color pixel. Similarly, ACU-2 and ACU-4 are connected to each other via the second averaging switch Savg. The function of the averaging switch Savg will be described in more detail in the description of the circuit diagram of FIG. 7 which specifically shows ACU-1 and ACU-3.

Hereinafter, the structure and operation method of the ACU will be described in detail with reference to FIGS. 7 and 8A in the CIS of FIG.
FIG. 7 is a block diagram showing two ACUs connected by switches in the CIS of FIG. FIG. 8A is a timing diagram showing waveforms of switching signals and row selection signals used during CDSS in the CIS of FIG.

Each ACU included in ACU in FIG 3 (ACU-1, ACU- 2, ACU3 etc.) is selectively connected to every pixel in a predetermined row through the respective _{T SEL} switch of the pixel. Thereby, ACU-1 is coupled to each of the first column pixels including pixels R11 and R31, and similarly, ACU-3 is coupled to each of the third column pixels including pixels R13 and R33. In general, each column pixel of an APS array is connected to a vertical transmission line via a respective _TSEL switch and is also connected to an ACU via a vertical transmission line. During operation, each column pixel of the APS array is activated by a row selection signal input via a horizontal line connected to every pixel in each row of the APS array. If W is the number of pixels in one row of the APS array, W is the same as the number of ACUs. Thereby, as described above, during operation, any ACU, including ACU-1 and ACU-3, can simultaneously receive analog pixel data from pixels located in each row of the APS array.

  As shown in FIG. 8A, the first row is activated first by SEL1, and then the third row is activated by SEL3. Thereby, during operation, ACU-1 and ACU-3 obtain analog pixel data including a reset voltage and an image signal voltage from each of the four pixels of the same color (eg, R11, R31, R13, R33). Since ACU-1 and ACU-3 are connected by a switch Savg, ACU-1 and ACU-3 can share analog pixel data obtained from four pixels of the same color (for example, R11, R31, R13, R33). Specifically, ACU-1 and ACU-3 synthesize and divide pixel data of each type (reset and image signals) obtained from 4 pixels of the same color, and average the reset charge / voltage VR. And an averaged value of the image signal charge / voltage VS. Each ACU subtracts the averaged value of the reset charge / voltage VR from the averaged value of the image signal charge / voltage VS to obtain a final mathematical average such as the CDS sampled 4 pixels. Output analog pixel data. Thereby, static fixed pattern noise is removed.

Each ACU includes an analog subtractor (eg, subtractor-1 and subtractor-3) and an amplifier AMP1 that receives and transmits the output of the analog subtractor.
The amplifier AMP1 may be a non-inverting amplifier (where Vref = 0) or a differential amplifier connected to a reference voltage Vref used for parallel analog-to-digital conversion described below. With such an arrangement, the bias source Vramp is placed at the first voltage level during the averaging operation and at the second voltage level during the analog-to-digital conversion operation. The first voltage level is different from the second voltage level. The buffer capacitor CA and the second output amplifier AMP2 are optional items and they are used to increase the gain for analog-to-digital conversion resolution. The analog domain subtractor output in each ACU (eg, ACU-1 and ACU-3) is sensed by amplifier AMP1, buffered by optional capacitor CA, and further amplified for analog-to-digital conversion by optional amplifier AMP2. The As a result, voltage signals VCD1 and VCD3 indicating the averaged VS-VR are output.

  Each analog domain subtractor (eg, subtractor-1) according to the present invention is coupled to a column pixel processed by the ACU (eg, a pixel in the first column processed by ACU-1) via switch S1. Including a plurality of data storage capacitors (for example, CS11, CS31, CR11, CR31 in ACU-1) connected to one common node on a vertical transmission line, which are essential components. Each of the four data storage capacitors in each ACU is determined by being sequentially connected through a plurality of switches (eg, S1, S2, S3, S4, SS, SR) and an ACU (eg, ACU-1). Are stored with being filled with a certain analog pixel data charge (reset or signal data) received from one of the pixels (first row or third row pixels in the same column). The switch (S1, S2, S3, S4, SS, SR) in all ACUs and the switch Savg between the ACUs are opened or closed at the same time. Switches within each ACU (eg, S1, S2, S3, S4, SS, SR) are opened by the action of a row selection signal (eg, SEL), as shown in the timing diagram of FIG. 8A, or Blocked.

  By adjusting the switches S1, S2, S3, S4, SS, SR, the connection between the pixel, four storage capacitors (eg CS11, CS31, CR11, CR31) and other current paths can be controlled. The capacitors are filled with analog pixel data by the following order. First, the storage capacitor CR11 stores the reset charge from the pixel R11 in the first column of the first row. Next, the storage capacitor CS11 stores the signal charge from the pixel R11 in the first column of the first row. Next, the storage capacitor CR31 stores the reset charge from the pixel R31 in the first column of the third row. Next, the storage capacitor CS31 stores the signal charge from the pixel R31 in the first column of the third row.

  On the other hand, during a mode in which the ACU is not a CDSS, that is, in the standard CDS mode, a reset data storage capacitor CR (for example, CR11, CR31, or one) in each ACU (ACU-1 and ACU-3, respectively) One of CR11 and CR31 combined to operate like a capacitor, and a signal data storage capacitor CS (for example, CS11 and CS31, or CS11 and CS31 combined to operate like a single capacitor). One of which is loaded with analog pixel data received from that pixel. Thereby, multiple ACUs are loaded with complete reset and signal analog pixel data from only one row of pixels. By such a method of loading the data storage capacitors CR, CS in the ACU, a standard (non-subsampling mode) CDS is present in every pixel (eg, R11,) in one row (eg, the first row) of the APS array. G12, R13, G14,...). If the row select line is then activated, the next operation of the ACU in standard CDS mode is to make every pixel (eg, G21, B22, G23, B24) in one row (eg, the second row) of the APS array. ,... In the standard CDS mode, the switches SS, SR, and Savg are fixed in an open state without operating.

  In the CDSS mode (subsampling mode), 8 storage capacitors are connected to the ACU (eg, ACU-1, ACU-3) by switching, and analog (reset and reset) from the four pixels R11, R31, R13, R33. Signal) filled with pixel data, so that the switches SS, SR, Savg work together with the switches S1, S2, S3, S4 to block sequentially so that the four pixels R11, R31, R13, R33 Any charges of the same type (reset or signal) received are synthesized and divided and averaged.

  However, in the ACU CDSS method according to an embodiment of the present invention, when the averaging switch Savg is closed, the storage capacitors in the ACUs of other columns (for example, the first and third columns) connected to each other are connected. In between, each type (reset or signal type) of analog pixel data is averaged. Thereby, for example, the data storage capacitor CS11 is loaded with the signal data from the pixel R11, whereas the data storage capacitor CR11 does not store only the reset value of the pixel R11, but the reset data and the pixel of the pixel R11. Save the average of R13 reset data.

  In order to perform the averaging through the process of loading the four storage capacitors in each ACU, the operation of the switch, in particular the averaging switch Savg, is shown in the timing diagram of FIG. 8A. Here, the switch closes at a high level. When switch S1 is closed, the set of data storage capacitors, eg, CR11, CR12 (not shown), CR13, CR14 (not shown) are activated in the row selection line (eg, the first row is Loaded with a certain type of analog pixel data output from one pixel in a row determined by SEL1). Subsequently, the switch S1 is opened and the averaging switch Savg is closed. On the other hand, in any ACU, the switches S2, S3, S4, SS and SR are opened or closed, and one of the four data storage capacitors in each predetermined ACU is specified. Receive and store analog pixel data.

  For example, as shown in FIG. 8A, at (1) time, the averaging switch Savg is opened, the switch S1 is closed, and reset data is loaded into the capacitors CR11 and CR13. Next, after the reset pixel data is completely loaded into the capacitors CR11 and CR13, (2) the switch S1 is opened at time, the averaging switch Savg is closed, and the analog pixel data stored in the capacitors CR11 and CR13 (or Charge) is synthesized and divided. As such, after analog pixel data (reset data) is received by each selected data storage capacitor (eg, CR11, CR12, CR13, CR14) in every ACU, upon completion of loading of the data storage capacitor, By opening the switch S1 and closing the averaging switch Savg between the ACUs, corresponding charges of the same type from the same color pixels in the same row (for example, reset charges from the pixels R11 and R13) are averaged (combined and divided). ) As such, analog pixel data of the same type (eg, reset) received from two pixels of the same color in the same row is averaged with a fixed storage capacitor pair (eg, CR11 and CR13) and stored in each. For example, after the switch S1 is closed at time (3), (5), (7) and the switch Savg is opened, the switch S1 is opened at time (2), (4), (6), and the switch Savg is Such a general accompaniment averaging scheme that closes is equally applicable to the remaining three pairs of data storage capacitors (eg, CS11 and CS13, CR31 and CR33, and CS31 and CS33). That is, each of the four pairs of storage capacitors (CR11 and CR13, CS11 and CS13, CR31 and CR33, and CS31 and CS33) in the ACU (for example, ACU-1 and ACU-3) connected by switching is accompanied. Save the averaged values of reset and signal data received from two pixels of the same color.

  An averaging (compositing and splitting) is then performed on the same type of pixel data received from the same column pixel in another row. Data averaging from the same column pixel in other rows was stored in the data storage capacitor CS pair (eg, CS11 and CS31 in ACU-1) in each ACU, eg, closing switch SS at (9) time The signal data charges are equalized, the switch SR is closed, and the reset data charges stored in the data storage capacitor CR pair (eg, CR11 and CR31 in ACU-1) in each ACU are equalized to make it easier. Is called. With such a final identical column averaging process, each of the four CS data capacitors (eg, CS11, CS13, CS31, CS33) in the ACU (eg, ACU-1 and ACU-3) connected by switching is Hold the same average signal charge. The averaged signal charge represents an accurate mathematical average of the four signal charges received from four pixels of the same color (eg, R11, R13, R31, and R33). Similarly, in such a same column averaging process, each of the four CR data capacitors (eg, CR11, CR13, CR31, CR33) in the ACU (eg, ACU-1 and ACU-3) connected by switching, respectively. Hold the same average reset charge. The averaged reset charge represents an accurate mathematical average of the four reset charges received from four pixels of the same color (eg, R11, R13, R31, and R33).

For example, for performing CDSS on four pixels R11, R13, R31 and R33, eight data capacitors (eg, CR11, C) in two ACUs (eg, ACU-1 and ACU-3) connected by switching. The data loading and averaging process of CR13, CR31, CR33 and CS11, CS13, CS31, CS33) displays the charges at times (1)-(9) shown in the timing diagram of FIG. This will be described in more detail with reference to mathematical expressions. In the following equation, Q represents the charge of the storage capacitor with the subscript, and the “=” display assumes the same type, ie, the capacitance of all storage capacitors of CS or CR is the same. Indicates that the charges are the same. The voltage in the form indicated by the subscript, for example, V _RESET11 is the same as the voltage VR11. A capacitance in a form indicated by a subscript, for example, CCR11 / CR31 indicates one capacitance when the storage capacitor with the subscript, CR11 and CR31 are connected in parallel.

At time (1), reset voltages VR11 and VR13 of pixels R11 and R13, respectively, are sampled and loaded into data storage capacitors CR11 and CR13, respectively. At that time, the following formula is satisfied.
R11 _{Pixel: Q CR11 = Q CR31 = C} CR11 / CR31 (V RESET11 -V ref)
R13 pixel: _QCR13 = _QCR33 = _{CCR13 / CR33} ( _VRESET13 - _Vref )

At time (1), capacitors CS11, CS13, CS31, and CS33 are also charged, but such initial charge is changed to the image signal data received later from certain pixels.
By closing the averaging switch Savg at time (2), the respective reset voltages VR11 and VR13 of the pixels R11 and R13 are combined between the data storage capacitors CR11 and CR13 and divided and averaged. At that time, the following formula is satisfied.

At time (3), the image signal voltages VS11 and VS13 of the pixels R11 and R13, respectively, are sampled and loaded into the data storage capacitors CS11 and CS13, respectively. At that time, the following formula is satisfied.
R11 pixel: Q _CS11 = Q _CS31 = C _{CS11 / CS31} (V _SIGNAL11 V _ramp )
R13 pixel: Q _CS13 = Q _CS33 = C _{CS13 / CS33} (V _SIGNAL13 V _ramp )

At time (3), since the switches S3 and S4 are opened and the capacitors CR11, CR13, CR31, and CR33 that store the reset voltage are in a floating state, the capacitors CR11, CR13, CR31, and CR33 that store the reset voltage are in a floating state. each of the previous time (1) is charged by the charge amount _{Q CR11, Q CR31, Q CR13} , and holds the _{Q CR33.}

  At time (4), the averaging switch Savg is closed so that the respective image signal voltages VS11 and VS13 of the pixels R11 and R13 are synthesized between the data storage capacitors CS11 and CS13 and divided and averaged. . At that time, the following formula is satisfied.

At time (5), the respective reset voltages VR31 and VR33 of the pixels R31 and R33 are sampled and loaded into the data storage capacitors CR31 and CR33, respectively. At that time, the following formula is satisfied.
R31 pixel: _QCR31 = _CCR31 ( _VRESET31 - _Vref )
R33 pixel: _QCR33 = _CCR33 ( _VRESET33 - _Vref )

  At time (5), the switch SS is opened and the capacitors CS11 and CS13 that store the signal voltage are in a floating state, and the switch SR is opened and the capacitors CR11 and CR13 that store the reset voltage are in a floating state. Thereby, the capacitors CS11, CS13, CR11, and CR13 hold the amount of charge that has been previously charged.

  By closing the averaging switch Savg at time (6), the respective reset voltages VR31 and VR33 of the pixels R31 and R33 are synthesized between the data storage capacitors CR31 and CR33 and divided and averaged. At that time, the following formula is satisfied.

At time (7), the image signal voltages VS31 and VS33 of the pixels R31 and R33, respectively, are sampled and loaded into the data storage capacitors CS31 and CS33, respectively. At that time, the following formula is satisfied.
R31 pixel: Q _CS31 = C _CS31 (V _SIGNAL31 -V _ramp )
R33 pixel: Q _CS33 = C _CS33 (V _SIGNAL33 -V _ramp )

  At time (8), the averaging switch Savg is closed so that the respective image signal voltages VS31 and VS33 of the pixels R31 and R33 are synthesized between the data storage capacitors CS31 and CS33, and are divided and averaged. . At that time, the following formula is satisfied.

At time (9), a final averaging is performed on the four reset charges and the four signal charges. By closing the switch SR, two reset voltages in the same _row stored in each ACU are averaged, and the average reset charge Q _RAVG is held in the capacitor. Further, when the switch SS is closed, two image signal voltages in the same _row stored in each ACU are averaged, and the average signal charge Q _SAVG is held in the capacitor. That is, the following formula is satisfied.

  Thus, closing the switches SS and SR produces a final averaged and subsampled voltage difference (VS−VR) for four pixels of the same color. After final averaging, ie, time (9), the charge stored in the CS and CR data storage capacitors in ACU-1 and ACU-3 for the first and third columns is derived from four pixels. It is also held on average with the charge taken. Thus, either one of the outputs VCD1 or VCD3 is used to be read for analog-to-digital conversion as the final voltage difference (VS-VR) indicating four CDSS sampled pixels of the same color.

  FIG. 8B is a timing diagram showing waveforms of a ramp voltage and a counter latch control signal used to perform analog-to-digital conversion of a plurality of outputs from a plurality of ACUs in the CIS of FIG. After final averaging, ie, time (9) in FIG. 8A, the average reset and average signal charge stored in the CS and CR data storage capacitors in ACU-1 and ACU-3 for the first and third columns Are compared by an analog domain subtractor (eg, subtractor-1) within each ACU to obtain one subsample voltage for the four CDSS sampled pixels of the APS array. A subtractor (eg, subtractor-1) composed of CS and CR capacitors connected in series is connected between the input of Vramp and the amplifier AMP1. As such, the voltage at the input of AMP1 is represented by the sum of the voltages as Vramp + VS + (− VR). This is because the polarity of the VR charge stored in the CR capacitor is connected in series so that the polarity of the VS charge stored in the CS capacitor is reversed. Therefore, the input voltage of AMP1 is a voltage that Vramp is clamped by the averaged (VS-VR), and thus becomes higher. The counter enable signal CE in FIG. 3 is applied to start counting after final averaging, that is, after the switches SS and SR are closed. Therefore, by gradually increasing the Vramp voltage at a constant rate at the moment of initializing the counter in the digital signal output circuit of FIG. 3, the size of (VS-VR) is quantized from the analog value. Converted to a constant digital value. Digital conversion is obtained by latching the count value when the AMP1 input from the output of the subtracter passes a certain critical voltage level (Vref). As the size of (VS-VR) increases, the time for the input of AMP1 to reach the critical voltage (Vref) is further shortened.

  When the input of AMP1 reaches a critical voltage (Vref), the output signal VCD of the ACU (eg, VCD1 of ACU-1) transitions from a low to a high value. Therefore, VCD signals from each ACU, for example, VCD1, VCD2, VCD3,... Are output to the latch circuit of FIG.

  FIG. 9 is a block diagram showing a counter and a latch circuit used for performing analog-digital conversion of a plurality of outputs from a plurality of ACUs in the CIS of FIG. The counter outputs a digital count value when the counter enable signal CE starts to be activated. For example, the counter enable signal CE is activated after the final averaging of four pixels by an ACU operating in CDSS mode, or only one pixel data is loaded into each of the ACUs during standard CDS mode. Is done. The latch circuit includes a plurality of parallel count-latches corresponding to each ACU, and latches the count value output by the counter to every latch at a time determined by each VCD signal output by each ACU. . The VCD signal output by each ACU is used to control the respective count-latch provided to the latch circuit for each ACU. That is, when the VCD signal (eg, VCD1 of ACU-1) transitions from a low to a high value, each count-latch provided for that ACU stores the instantaneous count value. Thus, when the counter finishes counting, all independent signals output from the subtractors in the plurality of ACUs are converted in parallel from analog to digital. The stored values of the plurality of latches that store the count value for each ACU in the latch circuit are output to the digital signal processor for further reprocessing or subsampled or subsampling from each ACU. Pixel data that has not been processed is stored or transmitted as digital pixel data.

FIG. 10 is a diagram of the present invention showing multiple ACUs connected by switches for CDSS averaging / subsampling N ² pixels at a subsampling rate greater than 4 in the CIS APS array of FIG. It is a block diagram concerning other examples. The ACU of FIG. 10 is similar to FIG. 6, except that the switching connection between multiple ACUs (NACUs) is more flexible in that ACUs of two or more different columns can be connected simultaneously. . Such increased connectivity is achieved by combining and dividing pixel charges (eg, reset charge and image signal charge) from more than two columns, as in the case of the ACU pair linked in FIG. Allow averaging. Thus, instead of two ACUs each including two CR data storage capacitors and two CS storage capacitors, each includes N CR data storage capacitors and N CS storage capacitors. By connecting N ACUs to each other, the buyer pattern 2N × 2N pixel region is subsampled, and three colors R (Red), G (Green), B ( blue). Thus, the concatenated system as shown in FIG. 10 supports 2N × 2N pixel area CDSS in the CIS of FIG. 3, where N includes 1 (in the case of standard mode without sub-sampling). It is a positive integer (for example, it may be 2 as shown in FIGS. 6 and 7).

FIG. 11 is a detailed block diagram according to another embodiment of the present invention of an ACU that averages / subsamples N ² pixels in the CIS APS of FIG. The NACU of FIG. 11 is similar to the ACU shown in FIG. However, the analog domain subtractor in the NACU of FIG. 11 includes 2N analog pixel data storage capacitors instead of four analog pixel data storage capacitors. Added data storage capacitors and additional switches that control their loading and averaging were placed in N other columns and 2 other rows in the 2N × 2N pixel area of the APS array. Helps N ² pixels of the same color to be averaged and subsampled in CDSS mode. The CR data storage capacitors CR1 to CRN in one NACU subtractor (eg, N subtractor-1) are charged with a reset voltage from a column pixel connected to the NACU. The CS data storage capacitors CS1-CSN in one NACU subtractor (e.g., N subtractor-1) are charged with the image signal voltage from a column pixel connected to the NACU.

  Since one NACU for each column of pixels is required for CDSS averaging or sub-sampling, the NACU of FIG. 11 has at least N−1 other identical NACUs as shown in FIG. And connected by switching. In practice, the NACU of FIG. 11 can perform CDSS averaging or subsampling on only a few L pixels less than 1, 2, 3, or N for a column, so any other NACU in the CIS. Are connected by switching in the manner described in FIG. However, each averaging switch Savg is independently or dynamically controlled, and the averaging switch between a first block containing L NACUs and an adjacent second block containing other L NACUs. So that no connection is made. However, the same 2N × 2N (or 2L × 2L) pixel regions are averaged together by the CDSS mode operation of each block including NACUs concatenated by L or N switching.

By dynamically controlling the switches Savg, S1, S2, S3, S4, and (SS1... SSN) and (SR1... SRN), the ACU can be dynamically selected square (or not square) it is possible to perform sub-sampling with respect to the same color of L ² pixels placed in the pixel region of a).

  As described above, at least one embodiment of the present invention averages reset values received from a plurality of pixels in the analog domain, and averages image signal values received from the plurality of pixels in the analog domain. And subtracting the averaged reset value from the averaged signal value in the analog domain and CDSS sampled to show the exact mathematical average of the four common same color CDS sampled pixels A method and apparatus for performing CDSS that includes generating an analog data value is provided. Thus, at least one embodiment according to the present invention can directly and accurately sub-sample a plurality of pixels in the APS, thereby eliminating static fixed pattern noise.

  As described above, the best embodiment has been disclosed in the drawings and specification. Certain terminology has been used herein for the purpose of describing the invention only and is intended to limit the scope of the invention as defined by the meaning and claims. It was not used. Accordingly, those skilled in the art will appreciate that various modifications and equivalent other embodiments can be made therefrom. Therefore, the true technical protection scope of the present invention must be determined by the technical idea of the claims.

  The image sensor and its sub-sampling method according to the present invention can be used for an image pickup device such as a digital camera or a mobile phone.

1 is a block diagram illustrating a related art CIS including an APS array. FIG. FIG. 6 is a block diagram illustrating a related art CDS circuit that may be applied to roughly average four identically colored pixels. FIG. 3 is a block diagram illustrating a CIS including an ACU that performs an APS array and CDSS, according to one embodiment of the present invention. FIG. 4 is a circuit diagram showing each pixel structure in the CIS APS array of FIG. 3. FIG. 4 is a block diagram illustrating a buyer pattern array of color sensing pixels in the APS array of FIG. 3 and its output. FIG. 4 is a block diagram showing a switching connection between a plurality of ACUs performing CDSS in the CIS of FIG. 3. FIG. 4 is a block diagram showing two ACUs connected by a switch in the CIS of FIG. 3. FIG. 4 is a timing diagram illustrating waveforms of a switching signal and a row selection signal used during CDSS in the CIS of FIG. 3. FIG. 4 is a timing diagram showing waveforms of a ramp voltage and a counter latch control signal used to perform analog-digital conversion of a plurality of outputs from a plurality of ACUs in the CIS of FIG. 3. FIG. 4 is a block diagram illustrating a counter and a latch circuit used to perform analog-digital conversion of a plurality of outputs from a plurality of ACUs in the CIS of FIG. 3. 3 according to another embodiment of the present invention showing multiple ACUs connected by switches for performing CDSS, averaging / subsampling N ² pixels at a subsampling rate greater than 4 in the CIS APS array of FIG. It is a block diagram. FIG. 4 is a specific block diagram according to another embodiment of the present invention of an ACU that averages / subsamples N ² pixels in the CIS APS of FIG.

Claims (43)

An image sensor composed of a plurality of pixels arranged in rows and columns,
Each column pixel is
A switch coupled to at least two reset data capacitors for storing at least two reset charges and at least two image signal data capacitors for storing at least two image charges;
At least one of the at least two reset data capacitors of each column is coupled in series at a node to at least one of the at least two image signal data capacitors in the same column;
The at least two reset data capacitors are connected to each other through a switch;
The image sensor is
An averaging circuit that performs a first averaging operation using the at least two reset charges to generate an averaged reset charge for at least two pixels in the same column;
The first averaging operation is:
An image sensor comprising: a first step of averaging reset values of pixels arranged in the same row; and a second step of averaging reset values of pixels arranged in the same column. The averaging circuit is
The method of claim 1, wherein the at least two image charges are used to perform a second averaging operation to generate an averaged image charge for at least two pixels in the same column. Image sensor.   The image sensor according to claim 2, wherein the first and second averaging operations are performed in an analog domain. The image sensor is
The image sensor according to claim 2, further comprising an analog subtractor that subtracts the averaged reset charge from the averaged image charge to generate a differential voltage. The image sensor is
The image sensor according to claim 4, further comprising an analog-to-digital converter that performs analog-to-digital conversion on the differential voltage. The averaging circuit and the analog-to-digital converter are:
The image sensor according to claim 5, wherein the image sensor is commonly biased by the same bias source. The bias source is
A first voltage level during the first and second averaging operations; a second voltage level during the analog-to-digital conversion operation; and the first voltage level is different from the second voltage level. The image sensor according to claim 6. The first step of the averaging is
The image sensor according to claim 1, wherein the image sensor is performed before the second step of averaging is performed. The averaging circuit is
The image sensor of claim 1, further comprising a switch positioned between the at least two reset data capacitors. The averaging circuit is
3. The image sensor of claim 2, further comprising a switch positioned between the at least two image signal data capacitors.   The image sensor according to claim 1, wherein the image sensor is of a CMOS type. In a method of subsampling N ² pixels in an APS array,
N first reset charges are received from N pixels in the first column of the APS array and connected in parallel to each other via a switch between the first node and the second node. Continuously storing in a reset charge storage capacitor of the set;
Closing (N-1) reset charge retention switches coupled to the N first set of reset charge storage capacitors between the first node and the second node;
Closing a row direction averaging switch disposed between the first node and N reset charge storage capacitors corresponding to a second column of the APS array;
When the N-1 reset charge holding switches are closed, the N first set of reset charge storage capacitors are connected in parallel to each other;
A sub-sampling method comprising performing a first averaging operation in which an averaged reset charge for N pixels in the first column is generated. The sub-sampling method includes:
13. The sub of claim 12, further comprising storing N image charges from N pixels in the first column of the APS array in N second sets of image charge storage capacitors. Sampling method. The first averaging operation is:
The sub-sampling method according to claim 12, wherein the sub-sampling method is performed in an analog domain. The sub-sampling method includes:
The sub-sampling method of claim 13 , further comprising performing a second averaging operation on the image charges stored in the N second image charge storage capacitors. The second averaging operation is as follows:
Synthesizing the image charge;
The sub-sampling method of claim 15, further comprising connecting at least two capacitors of the second set of image charge storage capacitors in parallel with each other. The sub-sampling method includes:
In the analog domain, further includes a subtraction operation,
In the subtraction operation, at least one of the second set of image charge storage capacitors and at least one of the first set of image charge storage capacitors are connected in series to generate a differential voltage. The sub-sampling method according to claim 16, wherein the sub-sampling method is performed. The sub-sampling method includes:
The sub-sampling method according to claim 17, further comprising analog-to-digital conversion of the differential voltage from the subtraction operation. The averaging operation and the analog-to-digital conversion of the differential voltage are:
19. The sub-sampling method according to claim 18, wherein the sub-sampling method is performed by a circuit biased by one source bias. The one source bias is:
The sub-sampling method according to claim 19 , wherein the voltage level is low during the averaging operation and the voltage is high during the analog-to-digital conversion.   The subsampling method according to claim 16, wherein N is four. The four pixels are arranged in 2 rows and 2 columns,
The first averaging operation is:
From the first row and the first pixel pair of the steps of generating a first same row average for the two reset charge,
Generating a second identical row average for two reset charges from a second pixel pair in the second row;
The subsampling method according to claim 21, further comprising: averaging the first same row average and the second same row average. It consists of a pixel array arranged in a plurality of rows and a plurality of columns,
An operation is performed in which each pixel of each column pixel is connected to the averaging unit,
Each averaging unit
First and second storage capacitors for storing analog reset data from the first pixel and the second pixel;
Third and fourth storage capacitors for storing analog image signal data from the first pixel and the second pixel;
At least one of the first and second storage capacitors is connected in series at a node to at least one of the third and fourth storage capacitors of the same column;
The image sensor, wherein the first and second storage capacitors are connected to each other by a switch to generate an average reset charge for the first and second pixels of the same column.   24. The image sensor of claim 23, wherein the analog reset data from the first pixel and the second pixel is stored as a charge. The image sensor is
24. The image sensor of claim 23, further comprising a first averaging switch that performs a first averaging operation including averaging analog reset data stored in at least two averaging units. The first averaging switch includes:
26. The image sensor of claim 25, wherein a second averaging operation including averaging analog image signals stored in at least two averaging units is performed. The first and second averaging operations are:
27. The image sensor according to claim 26, which is performed in an analog domain. Each of the averaging units is
The image sensor of claim 23, further comprising an Nth storage capacitor for storing analog image signal data from the Nth pixel. Each of the averaging units is
The image sensor of claim 23, further comprising a 2Nth storage capacitor for storing analog reset data from the Nth pixel. The image sensor is
24. The image sensor of claim 23, further comprising an analog-to-digital converter for each column for analog-to-digital conversion of a plurality of outputs from the averaging unit. Each of the analog-to-digital converters is
The image sensor according to claim 30, wherein the plurality of outputs from the averaging unit are analog-to-digital converted in parallel. The averaging unit and the analog - digital converter,
The image sensor according to claim 30 , wherein the image sensor is commonly biased by the same bias voltage. The bias voltage is
The first voltage level during the averaging operation is a first voltage level, and the second voltage level during the analog-to-digital conversion. The first voltage level is different from the second voltage level. The image sensor according to 32. The first averaging operation is:
27. The image sensor of claim 26 including averaging analog reset data for pixels arranged in the same row. The second averaging operation is as follows:
28. The image sensor of claim 27, comprising averaging analog image signal data for pixels arranged in the same row. Each of the averaging units is
24. The image sensor of claim 23, further comprising a reset averaging switch positioned between first and second storage capacitors that averages analog reset data for pixels in the same column. Each of the averaging units is
24. The image sensor of claim 23, further comprising an image signal averaging switch positioned between third and fourth storage capacitors that averages analog image signal data for pixels in the same column. The image sensor is
The image sensor according to claim 23, wherein the image sensor is a CMOS type. The image sensor is
The image sensor according to claim 23, further comprising a digital signal processor. In a method of subsampling N ² pixels in an array having pixels arranged in a plurality of rows and a plurality of columns, each pixel outputting a reset voltage and an image signal voltage,
Storing and combining a plurality of reset voltages output from the N ² pixels in a first set of storage capacitors;
Storing and synthesizing a plurality of image signal voltages output from the N ² pixels in a second set of storage capacitors;
Serially connecting at least one storage capacitor in the first set of storage capacitors and at least one storage capacitor in the second set of storage capacitors;
A sub-sampling method, wherein the first set of storage capacitors are connected to each other by a switch to generate an averaged reset charge for a plurality of pixels in the same column.   The method of claim 40, further comprising detecting a voltage between the first set of storage capacitors and the second set of storage capacitors connected in series.   41. The sub-sampling method of claim 40, further comprising digitally quantizing a voltage between the first set of storage capacitors and the second set of storage capacitors connected in series. . In the method each pixel outputs a reset voltage and the image signal voltage, subsampling N ² pixels in the APS array having N ² pixels arranged in the N rows and N columns,
The reset voltage of the first pixel in the first row is stored in the first capacitor as a first charge, the reset voltage of the second pixel in the first row is stored in the second capacitor as a second charge, and the first capacitor Immediately combining the charge and the second charge to produce an averaged reset charge for the first row;
The reset voltage of the first pixel in the second row is stored as a third charge in a third capacitor, the reset voltage of the second pixel in the second row is stored as a fourth charge in a fourth capacitor, and the third capacitor is stored. Combining the charge and the fourth charge immediately to produce an averaged reset charge of the second row;
Combining the reset reset charge for subsampling by combining the averaged reset charge of the first row and the averaged reset charge of the second row,
The sub-sampling characterized in that the first capacitor and the third capacitor are connected to each other by a switch to generate an averaged reset charge for pixels in the first and second rows of the same column. Method.

Images