JP2001036816A - Automatic calibration of a/d converter in cmos-type image sensor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To minimize the parasitic effect of an A/D converter and a CDS circuit by initializing the counters of respective n-A/D converters by a compensation value to compensate the digital output of the corresponding A/D converters to balance the nonuniformity of elements in a signal processing means. SOLUTION: Each A/D converter 16 is connected so as to receive an analog signal from a corresponding column line 14 through a known correlated double sampling(CDS) circuit 18 to convert each analog signal to a digital signal. The digital signal expresses the gray level of optical luminance detected by a corresponding pixel element. Then, in an initializing period before generation of N-pieces of digital signals, a compensation value where prescribed reference voltage corresponds to each of the N A/D converters 16 is obtained. As the result of it, the counters of the respective N A/D converters are initialized by the compensation value to compensate the digital output of the corresponding A/D converters 16 to balance the nonuniformity of elements in a signal processing means.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a CMOS image sensor, and more particularly, to an initialization procedure of an A / D converter in a CMOS image sensor.

[0002]

2. Description of the Related Art An image sensor is used to convert a light image focused on a sensor into an electric signal. Typically, an image sensor includes an array of photodetectors. In this array, when an image is focused on the array, each element generates a signal corresponding to the light intensity received by the element. These signals can then be used to display a corresponding image on a monitor.

One typical well-known type of image sensor is a charge-coupled device (CCD). Integrated circuit chips including CCD image sensors are expensive due to the need for special processes. CCDs also dissipate relatively large amounts of power due to the required clock signals and the normally required high voltages. In contrast to a CCD image sensor, a CMOS active pixel sensor (APS) has one
Control, drive and signal processing circuits can be monolithically integrated on a single sensor chip, which has recently attracted much attention. The advantage of CMOS APS image is
(1) low voltage operation and low power consumption, (2) process compatibility in on-chip electronics, and (3)
Potentially lower cost compared to conventional CCDs. These advantages result from the widespread availability of standard CMOS manufacturing processes.

[0004]

However, the present inventor has
In a wide-area and high-density pixel array, an analog signal generated by each photodetector has a parasitic capacitance, a resistance,
It is subject to varying degrees of parasitic effects such as dark current leakage or effects due to non-uniform device characteristics. These parasitic effects are inherent in semiconductor devices and reduce the signal-to-noise ratio of image information. Therefore, the noise problem is C
The main technical challenges that can limit the performance of MOS APS are presented. These noises include kTC noise associated with sampling the image data, 1 / f noise associated with the circuitry used to amplify the image signal, and fixed pattern noise associated with non-uniformity between columns in the array. No.

[0005] For the same internal signal on the column line, device variations, leakage current and / or mismatch between correlated double sampling (CDS) circuits and 1
A comparator in the A / D converter in one of the integrated circuit CMOS sensor chips generates a different digital signal value at the output of each A / D converter. Variations in performance between the ADC comparator and the CDS circuit corresponding to cells in a different column become worse when the line pitch between column lines is reduced. It is an object of the present invention to minimize these parasitic effects of A / D converters and CDS circuits.

[0006]

SUMMARY OF THE INVENTION An image sensor device according to the present invention includes N analog signals each outputting N analog signals.
An image sensing array having a row of output lines,
N is an integer greater than 1, an image sensing array;
Signal processing means having N input lines each for generating N digital signals corresponding to one of the N analog signals; and one signal for each of the N digital signals Are provided, and during an initialization period before the N digital signals are generated, a predetermined reference voltage is applied to the N A / D converters.
Connected to the input of the A / D converter to obtain a compensation value corresponding to each of the N A / D converters, so that the counter of each of the N A / D converters is calculated by the compensation value. Initialized to compensate for the digital output of the corresponding A / D converter, thereby balancing the non-uniformity of the elements in the signal processing means, achieving the above objective.

[0007] The image sensor device further comprises N initialization circuits, each of the signal processing means loading the compensation value into the corresponding counter and compensating the digital output of the corresponding counter. You may.

In the image sensor device, the signal processing means may each latch and add the compensation value to the output of the corresponding counter to compensate for the digital output of the corresponding counter. A conversion circuit may be further provided.

In the image sensor device, the signal processing means may generate a sampled analog signal in response to a corresponding one of the N analog signals. It may further include N sampling circuits connected to the input line.

[0010] The image sensor device includes the N A / Ds.
Each of the converters may have a first input terminal for receiving a reference ramp signal and a second input terminal for receiving the sampled analog signal.

In the image sensor device, each of the sampling circuits has a first input terminal and a second input terminal, and during the initialization period, the sampling circuit corresponds to each of the N A / D converters. The predetermined reference voltage may be applied through the first and second input terminals such that a compensation value is obtained at the output of the A / D converter.

[0012] The image sensor device may be configured so that during the initialization period, the compensation value corresponding to each set of the A / D converter is obtained at the output of the A / D converter. A voltage may be applied to each output of the sampling circuit.

[0013] In the image sensor device, the signal sensing array may be an image sensing array.

In the image sensor device, the reference voltage is equal to (Vramp +)-(Vramp-)-Vsh,
Where Vsh is greater than or at least equal to the offset voltage produced by the A / D converter, Vramp + is the highest value of the reference ramp signal, and Vramp- is the lowest value of the reference ramp signal. There may be.

In the image sensor device, the compensation value may be a binary complement of the digital signal from a corresponding A / D converter when the reference voltage is applied during the initialization period.

In the image sensor device, the image sensor may be a CMOS type image sensor.

In the image sensor device, the CMOS type image sensor may be a monolithic CMOS type image sensor.

An image sensing array having N columns of output lines for outputting N analog signals, respectively, according to the present invention, and N input lines and N input lines each corresponding to one of the N analog signals. A signal processing device having N A / D converters for generating a digital signal of
During an initialization period before generating the analog signals, a predetermined reference voltage is coupled to the outputs of the N A / D converters of the signal processing means, corresponding to each set of A / D converters. Obtaining a compensation value at the output of each of the N A / D converters; and (b) a counter in each of the N A / D converters before generating the N analog signals. And compensating the digital output of the corresponding A / D converter, thereby balancing the non-uniformity of the elements in the signal processing means. This achieves the above object.

In the step (b), the compensation value is set to 1
The method may further include loading the corresponding counters and compensating the digital signal output from the counters with N sampling circuits.

The step (b) may further comprise the step of latching the compensation value and adding the compensation value to the output of the corresponding counter by N sets of sampling circuits.

Before the step (a), the method further includes a step of sampling each of the N analog signals by the N sampling circuits and generating a sampled analog signal corresponding to the analog signal. May be.

Each of the N A / D converters has a first input terminal for receiving a reference ramp signal and a second input terminal for receiving the sampled analog signal.
May be provided.

The step (b) includes applying the predetermined reference voltage during the initialization period across the first input terminal and the second input terminal of each of the sampling circuits. The method may further include obtaining the compensation value corresponding to the A / D converter at an output of the A / D converter.

In the step (b), the predetermined reference voltage is applied across respective outputs of the sampling circuit during the initialization period, and corresponds to each of the N A / D converters. The method may further include the step of obtaining the compensation value at an output of the A / D converter.

[0025] The signal sensing array may be an image sensing array.

The reference voltage is (Vramp +)-(Vr
amp-)-Vsh, where Vsh is greater than or at least equal to the offset voltage created by the A / D converter, Vramp + is the highest value of the reference ramp signal, and Vramp- is the reference ramp. It may be the lowest value of the signal.

[0027] The compensation value may be a binary complement of the digital signal from the corresponding A / D converter when the reference voltage is applied.

[0028] The image sensor device may be a CMOS image sensor.

The image sensor according to the present invention is described in claim 2
3. The image sensor according to 3, wherein the CMOS image sensor is a monolithic CMOS image sensor, thereby achieving the above object.

The signal processing means used in the signal sensor device having signal sensing means having N columns of output lines for outputting N analog signals, respectively, according to the present invention comprises: N A / Ds having N input lines for generating N digital signals corresponding to one, each having a counter for generating one of the N digital signals
A converter, wherein a predetermined reference voltage is coupled to an input of the N A / D converters during an initialization period before the N digital signals are generated, and A compensation value corresponding to each of the D converters is obtained, and the N A / D
The counter in each of the converters is initialized with the compensation value to compensate for the digital output of the corresponding A / D converter, thereby balancing non-uniformity of elements in the signal processing means. Thereby, the above object is achieved.

[0031] The apparatus may further comprise N initialization circuits each of which loads the compensation value into the corresponding counter and compensates the digital output of the corresponding counter.

Each of the latches may further include N initialization circuits for latching the compensation value, adding the compensation value to the output of the corresponding counter, and compensating for the digital output of the corresponding counter. .

Each may further include N sampling circuits for generating a sampled analog signal in response to a corresponding one of said N analog signals.

Each of the N A / D converters has a first input terminal for receiving a reference ramp signal and a second input terminal for receiving the sampled analog signal.
May be provided.

Each of the sampling circuits has a first
And the predetermined reference voltage is applied across the first input terminal and the second input terminal during the initialization period, and the N number of A /
The compensation value corresponding to each of the D converters may be obtained at the output of the A / D converter.

[0036] The signal sensing means may be an image sensing array.

The reference voltage is (Vramp +)-(Vr
amp-)-Vsh, where Vsh is greater than or at least equal to the offset voltage generated by the A / D converter, Vramp + is the highest value of the reference ramp signal, and Vramp- is the reference ramp. It may be the lowest value of the signal.

[0038] The compensation value may be a binary complement of the digital signal from the corresponding A / D converter when the reference voltage is applied during the initialization period.

Signal sensor means having N columns of output lines for respectively outputting N analog signals according to the present invention, and having N input lines, each having one of the N analog signals. Signal processing means having N A / D converters for generating corresponding N digital signals, respectively, in order to minimize non-uniformity of elements in the signal processing means. The method of initializing a counter in a corresponding one of the N A / D converters in the signal processing means includes the steps of (i) during an initialization period before generating the N analog signals. , A predetermined reference voltage is coupled to the outputs of the N A / D converters of the signal processing means, and a compensation value corresponding to each of the N A / D converters is set to the A / D conversion of each set. Obtaining at the output of the vessel;
(Ii) initializing the counter in each of the N A / D converters with the corresponding compensation value before generating the N analog signals, and Compensating the output, thereby balancing the non-uniformity of the elements in the signal processing means, thereby achieving the above objective.

[0040] Said step (ii) may further comprise the step of loading said compensation value into one corresponding counter by means of N initialization circuits and compensating said digital signal output from said counter.

The step (ii) may further include the step of latching the compensation value by N initialization circuits and adding the compensation value to the output of the corresponding counter.

Before the step (i), the method further includes the step of sampling each of the N analog signals by the N sampling circuits and generating a sampled analog signal corresponding to the analog signal. Is fine.

Each of the N A / D converters has a first input terminal for receiving a reference ramp signal and a second input terminal for receiving the sampled analog signal. Is also good.

In the step (ii), the predetermined reference voltage is applied across the first input terminal and the second input terminal of each of the sampling circuits during the initialization period. And obtaining the compensation value corresponding to each of the A / D converters at the output of the A / D converter.

In the step (ii), the predetermined reference voltage is applied across the respective outputs of the sampling circuit during the initialization period, and the N A / Ds are applied.
The compensation value corresponding to each of the converters is calculated by the A / D
The method may further include the step of obtaining at the output of the converter.

[0046] The signal sensing array may be an image sensing array.

The reference voltage is (Vramp +)-(Vr
amp-)-Vsh, where Vsh is greater than or at least equal to the offset voltage generated by the A / D converter, Vramp + is the highest value of the reference ramp signal, and Vramp- is the reference ramp. It may be the lowest value of the signal.

[0048] The compensation value may be a binary complement of the digital signal from the corresponding A / D converter when the reference voltage is applied.

An active pixel image sensor manufactured by a CMOS process is described herein. The active pixel image sensor of the present invention includes a two-dimensional pixel array core of a photosensitive diode. The conductivity of a photosensitive diode is related to the amount of light received by the photodiode. The analog signal generated by the photodiode is buffered by a source-hollow amplifier, accessed by row transistors, and coupled to each column in the array. The analog signal on each column line is converted to a digital signal by an A / D converter (ADC) coupled to each column line. Among other methods, the A / D converter may be formed by a high gain comparator, an 8-bit binary counter tuned with a reference ramp signal tuned to a particular timing sequence. To perform A / D conversion within the time frame for the A / D conversion circuit, all sensing elements in the row convert each light level to a digital value during this interval using a specific timing sequence. Depending on the timing, the resulting digital signal value is delivered to another functional block of the chip, or the chip is turned off for processing during this or another period.
However, in a preferred embodiment, prior to the read operation of the first row line, the potential of the input node of the CDS on each column line is set to the "reference" voltage, followed by the value on each column being A It is converted to a digital value by a / D converter. The obtained output digital data includes information on non-uniformity and variation due to variation in device characteristics between the A / D converter and the CDS circuit. Next, the digital data value corresponding to each output line thus obtained is used as an initial value of each ADC counter before executing an operation following an actual A / D operation on a row of the pixel array. Used.
Therefore, the main parasitic effects and distortions of the A / D converter and the CDS circuit are minimized during the subsequent A / D conversion of the actual image.

[0050]

BRIEF DESCRIPTION OF THE DRAWINGS FIG.
Hereinafter, the present invention will be described in more detail. The drawings illustrate embodiments of the invention. One of the embodiments shown is a CMO
Although related to S image sensor applications, those skilled in the art should not be construed as limiting the invention to the embodiments and applications presented herein, as the invention may be illustrated in many different forms. That
Understood. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the spirit of the invention to those skilled in the art. In the drawings, the same numbers indicate the same elements.

FIG. 1 shows the architecture of a 640 × 480 CMOS active pixel image sensor formed on one integrated circuit chip. The image sensor core array 19 includes a two-dimensional pixel array of photodetectors indicated by reference numeral 10. The light detecting element includes the same circuit as the circuit shown in FIG. Row address shift register 1 with control signal 152 from timing / control theory 15
2 are connected to the core array 19 for addressing row by row. The output of the shift register 12 addresses the core array 19 line by line on an address line 21, thereby reading analog signals on column lines 14 according to predetermined frame rate timing requirements.

In one embodiment, each A / D converter 16 includes a well-known correlation double sampling (CDS) circuit 1.
8 are connected to receive analog signals from the corresponding column lines 14 and convert each analog signal to a digital signal. The digital signal is transmitted to the corresponding pixel element 10
Represents the gray level of the light intensity detected by. For example, if 8-bit A / D conversion is performed, the analog signal has 256 values, each representing a degree of optical brightness. The function of the CDS circuit 18 will be described below when FIG. 4 is described. The timing / control theory 15 outputs timing signals such as a switching signal for operating the CDS circuit 18, a control signal for operating the row address shift register 12, and a signal for operating the shift register 13 for controlling the operation of the system. I do.

When a sensing operation is performed, the image is focused on image sensor core 19 such that different portions of the image strike each pixel element 10. As shown in FIG. 2, each photodetector 10 is a photodiode 2
0 or its equivalent. The light-sensing device is one in which the conduction current is related to the light intensity hitting the junction of the light-sensing device, such as a photogate, bipolar phototransistor.

As shown in FIG. 2, the internal column line 24 is isolated at the beginning of the exposure cycle because the access transistor M3 is turned off due to the inactive state of the read signal RD. is there. First, the photodiode 20 is connected to the reset transistor M1.
Is reset to a value close to the VDD level. The reset transistor M1 is turned on when the reset signal RST output from the row address shift register 12 in FIG. 1 is active.

Exposure starts as the reset transistor M1 is turned off because the signal RST is inactive. This allows the photodiode current to discharge its own capacitance and reduce the charge at node P due to the light falling on it. The time interval, t _exp , shown in FIG. 5, is the time of image exposure. The time interval starts at the falling transition of the RST signal and ends at the rising transition of the RST signal. After a sufficient time from the start of exposure, the access transistor M in that row
3 is turned on by the active RD signal. The sufficient time above can be varied to provide different image sensitivities or exposure controls. When the access transistor M3 is turned on, the photodiode voltage at the node P, which is converted via the source hollow transistor M2 and the access transistor M3, is connected to the internal column line 24. The voltage is offset by the effect of the source hollow transistor M2 and, of course, the transistor M2
2 depending on the characteristics of This voltage is stored in a circuit at the end of the column line 24. Then, at the end of the exposure interval, the reset transistors M in the row
1 is turned on again, and the input of the source hollow M2 connected to the cathode node P of the photodiode 20 is connected to VDD.
Reset to a value close to. The actual signal sensed by the subsequent correlation doubling sampling (CDS) circuit 18 is:
The difference between the signals at the node C before and after the reset signal RST is activated, and is represented by ΔV _c . Elimination of the signal at node C at different instants is achieved by well-known CDS circuits, the details of which are not covered by the present invention. Both signals on internal column line 24 at different times are source hollow M2 and access transistor M2.
3 offset so that the internal column line 24
Errors related to are automatically disabled. The signal difference is then converted by the A / D circuit 16 into a digital value.
Provided to That is, the actual image acquisition operation is performed by acquiring the signal difference at the column node C at the end of the exposure time and after the reset signal RST is activated.

FIG. 3 is a functional block diagram of the exemplary A / D converter 16. The A / D converter 16 shown includes a high gain comparator 32, a clock gating theory 34, and an 8-bit binary counter 36, and two inverters 33,35. However, other settings that allow the conversion of the signal to a digital value are also possible. In the embodiment of FIG. 3, the reference ramp signal 38 is input to the non-inverting input node of the comparator 32 and the analog signal 31 from the CDS circuit is input to the inverting input node of the comparator 32. The clock signal 39 is gated by the output signal of the inverter 33. When performing A / D conversion, the reference ramp signal 38 starts rising, and the counter 36 starts counting as the clock signal 39 starts operating. If the reference ramp signal 38 is equal to the analog signal 31, the output of the comparator 32 flips and, via the clock gating logic 34, de-gates the clock signal 39. Thus, the output of counter 36 represents a digital value corresponding to analog signal 31 when the counter stops counting. The Vramp- value is the lowest level of the ramp signal 38, and Vramp + is the highest level of the ramp signal 38.

As shown in FIG. 4, the important path of the analog signal 31 from the input to the output depends on the source hollow M2, the access transistor M3, the internal column line 24, the CDS circuit 18, and the A / D converter 16. A comparator circuit 32 is included. Even for the same analog signal on node P in different photocells 10, device variations between source hollows M2 and device variations between access transistors M3 may be caused by a corresponding internal column line of each photocell 10. 24 to generate different signal values.
These variations can be minimized by the well-known CDS circuit 18 described above.

The read timing for pixels in two consecutive row lines is illustratively shown in FIG. The S1 and S2 signals actuate switches S1 and S2, respectively, in FIG. As an example, in FIG.
A line time interval of 69.4 μs, corresponding to a 30 Hz frame rate for 480 line lines, is disclosed and will be used later where applicable.

However, even for the same internal signal on each column line, device variation, leakage current, and / or
Or CDS circuit 18 and one integrated circuit CMOS
Comparator 32 in A / D converter 16 in sensor chip
The mismatch between produces different digital signal values at the output of each A / D converter 16. The variation in operation between the ADC comparator and the comparator of the CDS circuit corresponding to cells in different columns becomes worse as the line pitch between the column lines 24 is reduced. A / D converter 16 and CDS
To minimize these parasitic effects in circuit 18, the following preferred embodiments are used.

As shown in the circuit of FIG. 6a and the timing of FIG. 6b, the present invention provides a series of operations for each column at the beginning of a frame time slot and before the read operation for the first line in each frame. give. In 6b, the generation of the pulse at time t ₂ and t ₃ on the signal S1 and S2 are involved in the sampling of the actual image signal. The present invention provides two conventional switches S
In addition to 1 and S2, the corresponding signals S3 and S4 shown in FIG.
There are two additional switches S3 and S4 operated by.

At time t _1a , each internal column line 24
Is pulled down to VL by the switch S3. Next, this VL voltage is stored at the inverting input node (SIG) of the differential amplifier 60 of the CDS circuit 18 by turning on the switch S1 at time _t1b . Time t
_{At 1c} , switch S4 is turned on, causing all of the internal column lines 24 to be preset to VH. Note that the switch S4 cannot be turned ON when the switch S1 is ON. In a preferred embodiment, VH and VL are generally such that the difference between VH and VL, denoted Vref, is (Vram
p +)-(Vramp-)-Vsh or less. Here, Vramp + and Vramp- are the highest and lowest level ramp signals (used in FIG. 3), respectively, and Vsh is the maximum effective voltage offset. The maximum effective voltage offset can be created by combining the ADC and CDS circuits for any given column and is tolerated in the positive direction for any given manufacturing process. At time t _1d , the voltage V
H turns on the switch S2 to turn on the non-inverting input node (PRE) of the differential amplifier 60 of the CDS circuit 18.
Is transferred to and stored. As a result, shortly after time t _1d , the output of CDS circuit 18 for each column of the array will be from VH on node (PRE) to node (SIG), assuming that the offset voltage for each CDS is very small.
This is Vref obtained by subtracting the above VL.
Note that the switch S2 is turned off before M3 is turned on for sampling of the actual image signal.

FIG. 7A shows a comparison between the case of FIG.
Vref (= VH-VL) at the time of output from S circuit 18
5 shows another example of voltage generation. As shown in FIG. 7b, the switch S3 at time t ₁ and S
The purpose is achieved by presetting the input nodes (SIG) and (PRE) of the differential amplifier 60 to the VL and VH levels by turning ON 4 respectively. As expected, assuming that the offset voltage for each CDS is very small, the output of CDS circuit 18 will be Vref (= VH-VL). In Figure 7b, the occurrence of the pulse at time t ₂ and t ₃ on the signal S1 and S2 are involved in the sampling of the actual image signal.

Further, between columns caused by the CDS circuit
Is very small and negligible, the AD
No compensation is made only for the part caused by the C circuit
Can be In this case, a false image signal to the ADC input on each column
The generation of the Vref (= VH−VL) voltage as the signal
Time t shown in FIG. 8b₁In FIG.
When the switch S3 is turned on, the ADC to Vref is
This can be done by presetting the input nodes.
Time t on signals S1 and S2 in FIG. 8b _Twoand
t_ThreeThe generation of a pulse at
Involve in the ring.

By employing any one of the three methods described above, the voltage at the output of the CDS circuit 18 will be the time period from t _1d to t ₂ shown in FIG. 6b or shown in FIGS. 7b and 8b. During the period from t ₁ to t _2, it is converted into a digital value by the ADC circuit 16. If the offset voltage for each comparator in the ADC and CDS circuits for each column in the array deviates from each other, the digital value output from the ADC circuit will be the same Vref
It varies between columns under the signal.

According to the present invention, one A is set during the initialization period.
The binary complement of the digital value obtained for the DC circuit is used to initialize a counter in the corresponding ADC 16 before the actual image value conversion is performed for each row line in the frame time slot. That is, each initial value of the ADC's counter for each column is used to minimize the offset caused by the ADC and CDS circuits between columns. The invention may be further realized by the following detailed description of the results of an example operation.

In the following, by way of example, the maximum allowable output voltage shift Vsh in any direction may be selected to be 0.5 volt. However, under actual conditions, the forward V
There is a high possibility that the sh value is different from the Vsh value in the negative direction. Further, the input of the analog signal 31 to the comparator 32 is Vra
The voltage difference between the ramp signals Vramp + and Vramp- can be selected to be 3.5 volts while in the range of the mp + and Vramp- values. According to a statistical approach, all image sensor chips with device characteristics that deviate from the above range (± 0.5 volts) are deselected. By properly selecting the manufacturing process and the exposure time interval, moving from 0.5 volts with Vsh = 0.5 volts in any direction to 3 volts {Vc
Can be designed. Therefore, the final output value does not exceed 3.5 volts and does not fall below 0 volts.
ΔVc = 3 volts corresponds to the full open value of light brightness, ΔVc
= 0.5 volts corresponds to darkness. For example, during the image sensing period, after each operation of the corresponding switch at times t ₂ and t ₃ , the maximum difference of the input signal to the CDS circuit may be 3 volts, and thus substantially 3.5. Output volt analog signal. On the other hand,
The minimum difference between the signals input to the CDS circuit can be 0.5 volts, thus outputting a substantially 0 volt analog signal. Therefore, the dynamic range of the output of the A / D converter 16 is from 0 volts to 3.5 volts considering Vsh.

Without using the present invention, for .DELTA.Vc = 3 volts where Vsh is. +-. 0.5 volts, 8-bit A / D converter 16 has correspondingly the following values: Voc _n , Voc ₊ , and Voc _- are output. This phenomenon is
This is the inhomogeneity between columns that we intend to solve.

[0068]

(Equation 1)

Prior to the actual analog signal conversion of the image signal, the present invention provides that the auto-calibration of the counter in the A / D converter offsets any non-uniformity between different pixel columns in the array. Give an initialization period. Initialization of the counter by presetting the input of the CDS 18 or A / D converter 16 of each column line to the reference voltage Vref once before the read operation of the first row of the frame during each image frame time Is performed.

For example, during the initialization period, Vref = (Vr
amp +)-(Vramp-)-Vsh = 3.5 volts-0.5 volts = 3 volts may be used. Next, A / D
A conversion operation is performed to generate corresponding digital output data for each column. Assume that the results of the A / D conversion operation on three column lines X, Y, and Z are shown in items (4), (5), and (6), respectively. The present invention relies on inverting the binary data of items (4), (5), and (6) to binary complement, as listed below in items (7), (8), and (9). Use the data in items (4), (5) and (6) to get the required offset value.

[0071]

(Equation 2)

The above binary complement data is used to initialize each counter in each ADC circuit 16 corresponding to the column lines X, Y and Z, respectively. That is, according to the present invention, after the initialization period and before the A / D conversion for the actual image signal is performed for each row, each ADC corresponding to the column line X, the line Y, and the line Z is used. Circuit 1
The initial values of the counters in 6 are 0, 37 and 73, respectively.
It is. In a preferred embodiment, the initialization circuit shown in FIG. 10 is connected to a counter in the A / D converter, and the output of the initialization circuit is used during the initialization period in the A / D converter according to the present invention. Used to initialize the counter. FIG.
In the above, a latch enable signal is used to latch an output signal from a counter in a latch of an initialization circuit. The SCTR signal is output from the latch (IS0, IS0
1,. . . IS7) and preload the counter as described above.

The non-uniformity caused by the parasitic effects of each A / D converter is minimized by the value of the counter in the ADC circuit 16 for each column line before the actual image acquisition is each initialized by the method described above. Is limited.

For example, during sampling of the actual image signal, if the .DELTA.Vc signals for the column lines X, Y, and Z described above are each equal to 3 volts, the present invention will A / D output is 0+
255, that is, 255. Similarly, according to the present invention, the resulting A / D output for column line Y is 37
+218, or 255. Similarly, according to the present invention, the resulting A / D output for column line Z is 7
3 + 182, or 255. In other words, if the present invention is not the present invention, during sampling of the actual image signal, for ΔVc = 3 volts, each A / D output for column line X, line Y and line Z will be listed in list item (1), It can be the output shown in (2) and (3). In contrast, in the embodiment of the present invention, each A / D output for column line X, line Y, and line Z is 255
And all column uniformity is achieved as expected.

Similarly, when the present invention is not provided, and when ΔVc = 0.5 volts and Vsh is ± 0.5 volts, the 8-bit A / D converter will correspond as follows: It is assumed that Voc _n , Voc +, and Voc_ having the following values are output.

[0076]

(Equation 3)

In the present invention, during sampling of the actual image signal, when the .DELTA.Vc signals for column lines X, Y, and Z described above are each equal to 0.5 volts, the resulting value for column line X is obtained. A / D output is 0 + 7
3, ie 73. Similarly, according to the present invention, the resulting A / D output for column line Y is 37 + 3
6, ie 73. Similarly, according to the present invention, the resulting A / D output for column line Z is 73+
0, that is, 73. In other words, when the present invention is not the present invention, ΔVc =
For 0.5 volt, each A / D output may be the output shown in list items (10), (11), and (12). In contrast, in the practice of the invention, the respective A / D outputs are all equal to 73, and uniformity of all columns can be achieved as expected.

If higher resolution is required in a practical implementation, the number of bits of the ADC counter can be increased beyond eight bits to meet the requirements. FIG.
Other types of ADCs are available other than those shown, and their use can still achieve the objects of the invention without departing from the spirit of the invention.

Although the present invention has been described by way of example for application to a CMOS type image sensor chip, the present invention uses an A / D converter array and requires any output uniformity across the converters in the array. It is important to note that it is also applicable to circuits.

While the preferred embodiment of the invention has been described and illustrated, it will be appreciated by those skilled in the art that various equivalent modifications may be made without departing from the spirit and scope of the invention as defined by the appended claims. Can be obvious.

For example, instead of using the circuit illustrated in FIG. 10 to initialize the ADC counter as described above, the initialization value is obtained by complementing the output of each ADC during the initialization period of each frame. You may. Next, the obtained initialization value is stored in the data latch circuit. During the actual image acquisition operation, these values are then each added to the output of the ADC by an additional adder circuit to offset the non-uniformity between columns. The present invention is not limited to application to CMOS sensors, but includes physical or chemical changes by using various types of sensors 10.
It is applicable to a wide range of other signal sensing, such as temperature sensing, pressure sensing, etc.

In order to minimize non-uniformity across the N A / D converters, a corresponding set of N A / D converters of a single chip CMOS image sensor (where N is 1
A method for initializing a counter in an A / D converter (with a larger integer) is provided.

The single-chip CMOS image sensor is
An image sensing array having N columns of output lines for respectively outputting N analog signals;
A signal processing device for generating N digital signals respectively corresponding to one of the analog signals. The signal processing device has N input lines and N A / D converters each having a respective counter for generating one of the N digital signals. The method includes applying a predetermined reference voltage to each of the N input lines of the signal processing device to obtain a compensation value corresponding to each set of A / D converters. The method further includes loading counters of each corresponding set of A / D converters with a compensation value corresponding to each set of A / D converters before generating the N digital signals.

[0084]

In order to minimize non-uniformity across the N A / D converters, a corresponding set of N A / D converters of a single chip CMOS image sensor (where N is
Initialize a counter in the A / D converter (an integer greater than 1).

[Brief description of the drawings]

FIG. 1 is a block diagram of a conventional 640 × 480 CMOS active pixel image sensor.

FIG. 2 is a schematic view of a conventional active pixel cell and its basic operation timing.

FIG. 3 is a functional block diagram of an 8-bit A / D converter according to the related art and a reference ramp timing diagram thereof.

FIG. 4 is a simplified schematic diagram showing an analog signal critical path according to the prior art.

FIG. 5 is a timing chart of read operation for pixels in two consecutive row lines according to the related art.

FIG. 6a is a simplified schematic diagram of a preferred embodiment of the present application for reducing distortion of parasitic effects.

FIG. 6b is an operation timing diagram of FIG. 6a.

FIG. 7a is a simplified schematic block diagram of another preferred embodiment of the present application for reducing distortion of parasitic effects.

FIG. 7b is an operation timing diagram of FIG. 7a.

FIG. 8a is a schematic block diagram of another preferred embodiment of the present application for reducing distortion of parasitic effects.

FIG. 8B is a timing chart of a read operation corresponding to FIG. 8A.

FIG. 9 is an 8-bit ADC reference ramp timing diagram.

FIG. 10 illustrates how the initialization circuit performs, for example, initialization of a counter, according to a preferred embodiment.

[Explanation of symbols]

 13 shift register 14 column line 16 A / D circuit 18 CDS circuit 24 internal column line 60 differential amplifier

 ──────────────────────────────────────────────────続 き Continued on the front page (71) Applicant 599121942 12th Fl. , No. 214, Sec. 1, Hopin East R d. , Taipei, Taiwan (72) Inventor Li Xian No Taiwan, Taipei, Hopin East Road, Section 1, Number 214, 12 T F Floor F Term (Reference) 5C024 AA01 CA05 CA14 FA01 GA01 GA31 HA06 HA07 HA14 HA17 HA23 JA04

Claims (43)

[Claims] 1. An image sensor array, comprising: an image sensing array having N columns of output lines each outputting N analog signals, wherein N is an integer greater than 1. Signal processing means having N input lines for generating N digital signals corresponding to one of the N analog signals, each for processing one of the N digital signals. N A / D converters including a generating counter are provided, and during an initialization period before the N digital signals are generated,
A predetermined reference voltage is connected to the inputs of the N A / D converters to obtain a compensation value corresponding to each of the N A / D converters, resulting in the N A / D converters. The counter of each device is initialized with the compensation value and the corresponding A
An image sensor device that compensates for the digital output of a / D converter, thereby balancing non-uniformity of elements in the signal processing means. 2. The signal processing means further comprises N initialization circuits, each of which loads the compensation value into the corresponding counter and compensates for the digital output of the corresponding counter. The image sensor device according to claim 1. 3. The signal processing means includes N initialization circuits, each latching and adding the compensation value to the output of the corresponding counter to compensate for the digital output of the corresponding counter. The image sensor device according to claim 1, further comprising: 4. The signal processing means, wherein each of the N input lines of the signal processing means generates a sampled analog signal in response to a corresponding one of the N analog signals. 2. The image sensor device according to claim 1, further comprising N connected sampling circuits. 5. The method according to claim 4, wherein each of said N A / D converters has a first input terminal for receiving a reference ramp signal and a second input terminal for receiving said sampled analog signal. An image sensor device according to claim 1. 6. Each of said sampling circuits is a first
And a second input terminal, wherein the compensation value corresponding to each of the N A / D converters is obtained at the output of the A / D converter during the initialization period. 5. The image sensor device according to claim 4, wherein the predetermined reference voltage is applied through the first and second input terminals. 7. The method of claim 6, wherein during the initialization period, the predetermined reference voltage is such that the compensation value corresponding to each set of the A / D converter is obtained at the output of the A / D converter. The image sensor device according to claim 4, wherein the image sensor device is applied to each output of the sampling circuit. 8. The image sensor device according to claim 1, wherein the signal sensing array is an image sensing array. 9. The reference voltage is (Vramp +) − (V
ramp-)-Vsh, where Vsh is greater than or at least equal to the offset voltage produced by the A / D converter;
amp + is the highest value of the reference ramp signal;
The amp- is the lowest value of said reference ramp signal.
An image sensor device according to claim 1. 10. The image of claim 1, wherein said compensation value is a binary complement to said digital signal from a corresponding A / D converter when said reference voltage is applied during said initialization period. Sensor device. 11. The image sensor device according to claim 8, wherein the image sensor is a CMOS type image sensor. 12. The image sensor device according to claim 11, wherein said CMOS type image sensor is a monolithic CMOS type image sensor. 13. An image sensing array having N columns of output lines for respectively outputting N analog signals;
A signal processing device having N input lines and signal processing means having N A / D converters for generating N digital signals each corresponding to one of the N analog signals. (A) applying a predetermined reference voltage to the N A / Ds of the signal processing means during an initialization period before generating the N analog signals;
Coupling to the output of the converter to obtain at the output of each of the N A / D converters a compensation value corresponding to each set of A / D converters; and (b) the N analog signals. , The counter in each of the N A / D converters is initialized with the corresponding compensation value to compensate for the digital output of the corresponding A / D converter, and thereby the signal processing Balancing the non-uniformity of the elements in the means. 14. The method according to claim 13, wherein said step (b) further comprises the step of loading said compensation value into one corresponding counter and compensating a digital signal output from said counter with N sampling circuits. The method described in. 15. The method of claim 13, wherein step (b) further comprises the step of latching the compensation value and adding the compensation value to the output of the corresponding counter by N sets of sampling circuits. . 16. The method according to claim 16, further comprising: before the step (a), sampling each of the N analog signals by the N sampling circuits and generating a sampled analog signal corresponding to the analog signal. 14. The method of claim 13, further comprising: 17. Each of the N A / D converters has a first input terminal for receiving a reference ramp signal and a second input terminal for receiving the sampled analog signal. 17. The method of claim 16, wherein: 18. The method according to claim 18, wherein the step (b) comprises applying the predetermined reference voltage during the initialization period across the first input terminal and the second input terminal of each of the sampling circuits. 17. The method of claim 16, further comprising obtaining at the output of the A / D converter the compensation value corresponding to a set of A / D converters. 19. The method according to claim 19, wherein the step (b) includes applying the predetermined reference voltage across respective outputs of the sampling circuit during the initialization period, and
The compensation value corresponding to each of the D / D converters is calculated by the A / D
17. The method of claim 16, further comprising obtaining at an output of the converter.
The method described in. 20. The method of claim 13, wherein said signal sensing array is an image sensing array. 21. The reference voltage is (Vramp +) −
(Vramp-)-Vsh, where Vsh is the A /
18. The ramp of claim 17, wherein Vramp + is the highest value of the reference ramp signal and Vramp- is the lowest value of the reference ramp signal, greater than or at least equal to the offset voltage produced by the D-converter. Method. 22. The method of claim 13, wherein the compensation value is a binary complement of the digital signal from the corresponding A / D converter when the reference voltage is applied. 23. The image sensor device, wherein the image sensor device is a CMOS.
21. The method according to claim 20, which is a type image sensor. 24. The image sensor according to claim 23, wherein the CMOS image sensor is a monolithic CMOS image sensor. 25. Signal processing means for use in a signal sensor device having signal sensing means having N columns of output lines for respectively outputting N analog signals, each of said N analog signals. N input / output lines for generating N digital signals corresponding to one of the N digital signals, each having a counter for generating one of the N digital signals. A D-converter, wherein a predetermined reference voltage is coupled to an input of the N A / D converters during an initialization period before the N digital signals are generated; A compensation value corresponding to each of the A / D converters is obtained, the counter in each of the N A / D converters is initialized with the compensation value, and the digital value of the corresponding A / D converter is obtained. Compensates for the output, thereby , Balancing the non-uniformity of elements within the signal processing means, signal processing means. 26. The signal processing means according to claim 25, further comprising N initialization circuits each loading said compensation value into said corresponding counter and compensating said digital output of said corresponding counter. 27. N initialization circuits each latching the compensation value, adding the compensation value to the output of the corresponding counter, and compensating the digital output of the corresponding counter. Item 29. The signal processing means according to Item 25. 28. The signal processing means of claim 25, further comprising N sampling circuits each generating a sampled analog signal in response to a corresponding one of said N analog signals. . 29. Each of the N A / D converters has a first input terminal for receiving a reference ramp signal and a second input terminal for receiving the sampled analog signal. The signal processing means according to claim 28. 30. Each of said sampling circuits:
A first input terminal and a second input terminal, wherein the predetermined reference voltage is applied across the first input terminal and the second input terminal during the initialization period; The compensation value corresponding to each of the A / D converters is A / D converter.
29. The signal processing means according to claim 28, obtained at the output of the D converter. 31. The signal processing means according to claim 25, wherein said signal sensing means is an image sensing array. 32. The reference voltage is (Vramp +) −
(Vramp-)-Vsh, where Vsh is the A /
32. The ramp of claim 31, wherein Vramp + is the highest value of the reference ramp signal and Vramp- is the lowest value of the reference ramp signal, greater than or at least equal to the offset voltage created by the D-converter. Signal processing means. 33. The compensation value is a binary complement of the digital signal from the corresponding A / D converter when the reference voltage is applied during the initialization period.
An apparatus according to claim 25. 34. Signal sensor means having N columns of output lines for respectively outputting N analog signals;
Signal processing means having N input lines, each having N A / D converters for generating N digital signals each corresponding to one of the N analog signals. In the sensing device, initialize a counter in a corresponding one of the N A / D converters in the signal processing means to minimize non-uniformity of elements in the signal processing means. (I) applying a predetermined reference voltage to the N A / Ds of the signal processing means during an initialization period before generating the N analog signals;
Coupling to the output of the converter to obtain at the output of each set of A / D converters a compensation value corresponding to each of the N A / D converters; Prior to generating, the counter in each of the N A / D converters is initialized with the corresponding compensation value to compensate for the digital output of the corresponding A / D converter, thereby producing the signal Balancing the non-uniformity of the elements in the processing means. 35. The step (ii) further comprising loading the compensation value into one corresponding counter by N initialization circuits and compensating the digital signal output from the counter. Item 34. The method according to Item 34. 36. The method of claim 34, wherein step (ii) further comprises the step of latching the compensation value by N initialization circuits and adding the compensation value to the output of the corresponding counter. Method. 37. Before the step (i), a step of sampling each of the N analog signals by the N sampling circuits and generating a sampled analog signal corresponding to the analog signal, respectively. 35. The method of claim 34, further comprising: 38. Each of the N A / D converters has a first input terminal for receiving a reference ramp signal and a second input terminal for receiving the sampled analog signal. 38. The method of claim 37. 39. The method according to claim 39, wherein the step (ii) comprises applying the predetermined reference voltage over the first input terminal and the second input terminal of each of the sampling circuits during the initialization period. 38. The method of claim 37, further comprising obtaining at the output of the A / D converter the compensation value corresponding to each of the N A / D converters. 40. The step (ii) of applying the predetermined reference voltage across respective outputs of the sampling circuit during the initialization period,
The compensation value corresponding to each of the
38. The method of claim 37, further comprising obtaining at an output of the / D converter. 41. The method of claim 34, wherein said signal sensing array is an image sensing array. 42. The reference voltage is (Vramp +) −
(Vramp-)-Vsh, where Vsh is the A /
39. The ramp of claim 38, wherein Vramp + is the highest value of the reference ramp signal and Vramp- is the lowest value of the reference ramp signal, greater than or at least equal to the offset voltage created by the D-converter. Method. 43. The method of claim 33, wherein said compensation value is a binary complement of said digital signal from said corresponding A / D converter when said reference voltage is applied.