CN113612948B - Readout circuit and image sensor - Google Patents
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- CN113612948B CN113612948B CN202111000521.3A CN202111000521A CN113612948B CN 113612948 B CN113612948 B CN 113612948B CN 202111000521 A CN202111000521 A CN 202111000521A CN 113612948 B CN113612948 B CN 113612948B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/71—Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
- H04N25/75—Circuitry for providing, modifying or processing image signals from the pixel array
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
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Abstract
Embodiments of the present disclosure provide a readout circuit and an image sensor, the readout circuit including: a pixel array including a plurality of rows and columns of pixel units; a column counter adapted to obtain corresponding pixel signals of a plurality of rows of pixel units on a specific column in the pixel array; the column counter is reset after acquiring row-combined pixel signals of corresponding pixel signals of a plurality of row pixel units on a specific column. In the process of merging and reading the pixel signals of the acquired image information, the reading circuit does not need to buffer at least one row of pixel signals in advance, so that the chip area for storing the pixel signals in the image sensor can be effectively reduced.
Description
Technical Field
The present disclosure relates to the field of integrated circuits, and in particular, to a readout circuit and an image sensor.
Background
The complementary metal oxide semiconductor (Complementary Metal Oxide Semiconductor, abbreviated as CMOS) image sensor has the advantages of simple process, easy integration with other devices, small volume, light weight, low power consumption, low cost and the like, and therefore, with the development of image sensing technology, the CMOS image sensor is widely applied to various electronic products.
In some specific cases, CMOS image sensors require pixel signals to be read out in combination; however, the current CMOS image sensor needs to buffer at least one line of pixel signals when performing pixel signal merge readout, increasing the chip area. Therefore, a new readout circuit and image sensor are needed.
Disclosure of Invention
In order to solve the problems in the prior art, embodiments of the present disclosure provide a readout circuit and an image sensor, which can reduce a chip area.
To solve the above technical problem, an embodiment of the present disclosure provides a readout circuit, including: a pixel array including a plurality of rows and columns of pixel units; a column counter adapted to obtain corresponding pixel signals of a plurality of rows of pixel units on a specific column in the pixel array; the column counter is reset after acquiring row-combined pixel signals of corresponding pixel signals of a plurality of row pixel units on a specific column.
In some embodiments, the plurality of rows of pixel cells on a particular column are two rows of pixel cells adjacent to the particular column.
In some embodiments, the plurality of rows of pixel cells on a particular column are two rows of pixel cells spaced apart on a particular column.
In some embodiments, the readout circuitry further comprises: and the column latch is suitable for latching the row merging pixel signals obtained by the column counter on the corresponding column, and latches after the column counter obtains the row merging pixel signals and before the column counter resets.
In some embodiments, the readout circuitry further comprises: a timing control module adapted to generate a reset signal to control the reset of the column counter, the timing control module further adapted to generate a latch signal to control the opening of the column latch.
In some embodiments, the readout circuitry further comprises: an address decoder adapted to read out the row-combined pixel signals in the column latches.
The embodiment of the disclosure also provides an image sensor, including: a pixel array including a plurality of rows and columns of pixel units; a column counter adapted to obtain a row-combined pixel signal of a corresponding pixel signal of a plurality of rows of pixel units on a specific column in the pixel array; an address decoder adapted to read out the row-combined pixel signals; and a digital circuit adapted to receive the row-combined pixel signals read out by the address decoder and combine a plurality of columns of the row-combined pixel signals by the digital circuit.
In some embodiments, the order in which the address decoder reads out the row-combined pixel signals is related to receiving a column address provided by the digital circuit.
In some embodiments, the plurality of rows of pixel cells on the particular column are two rows of pixel cells adjacent to the particular column; the columns of the row-combined pixel signals are two adjacent columns of pixel signals in the row-combined pixel signals.
In some embodiments, the plurality of rows of pixel cells on a particular column are two rows of pixel cells spaced apart on a particular column; the columns of the row-combined pixel signals are two columns of pixel signals spaced in the row-combined pixel signal.
In some embodiments, the column counter is reset after acquiring row-combined pixel signals for rows of pixel cells on the particular column.
In some embodiments, the image sensor further comprises: and the column latch is suitable for latching the row merging pixel signals obtained by the column counter on the corresponding column, and latches after the column counter obtains the row merging pixel signals and before the column counter resets.
In some embodiments, the image sensor further comprises: a timing control module adapted to generate a reset signal to control the reset of the column counter, the timing control module further adapted to generate a latch signal to control the opening of the column latch.
The embodiment of the disclosure also provides an image sensor, including: the readout circuitry of any preceding embodiment, comprising an address decoder; and a digital circuit adapted to receive the row-combined pixel signals read out by the address decoder and to column-combine a plurality of columns of the row-combined pixel signals by the digital circuit.
In some embodiments, the order in which the address decoder reads out the row-combined pixel signals is related to receiving a column address provided by the digital circuit.
In some embodiments, the multiple columns of row-wise combined pixel signals are two adjacent columns of pixel signals in the row-wise combined pixel signal.
In some embodiments, the plurality of columns of row-wise combined pixel signals are two columns of pixel signals spaced apart in the row-wise combined pixel signal.
The embodiment of the disclosure also provides an image sensor, including: a mode selection module adapted to select a readout mode, the readout mode comprising a merge mode in which the image sensor comprises a readout circuit according to any one of the embodiments described above, the readout circuit comprising an address decoder.
In some embodiments, the image sensor further comprises: and the digital circuit is suitable for receiving the row merging pixel signals read out by the address decoder in the merging mode and carrying out column merging on a plurality of columns of the row merging pixel signals through the digital circuit.
In some embodiments, the order in which the address decoder reads out the row-combined pixel signals is related to receiving a column address provided by the digital circuit.
In some embodiments, the multiple columns of row-wise combined pixel signals are two adjacent columns of pixel signals in the row-wise combined pixel signal.
In some embodiments, the plurality of columns of row-wise combined pixel signals are two columns of pixel signals spaced apart in the row-wise combined pixel signal.
Compared with the prior art, the technical scheme of the embodiment of the disclosure has the following beneficial effects:
according to the readout circuit provided by the embodiment of the disclosure, the column counter is reset after the row merging pixel signals of the corresponding pixel signals of the pixel units in the plurality of rows on the specific column are acquired, the pixel signals of the pixel units in different rows to be merged are directly merged in the column counter, the pixel signals of the pixel units in the previous row are not required to be stored in the digital circuit, the data amount stored in the digital circuit can be greatly reduced, and the chip area is further reduced.
According to the image sensor provided by the embodiment of the disclosure, since each column of the pixel array in the readout circuit is provided with the column counter, when pixel signals need to be combined and read out, the pixel signals of pixel units in different rows can be combined in the readout circuit of the image sensor; and then, different columns in the row merging pixel signals can be merged in a digital circuit of the image sensor, so that the pixel signals of pixel units in a plurality of rows and columns can be merged, and the chip area for storing the pixel signals in the digital circuit can be effectively reduced.
The image sensor provided by the embodiment of the disclosure selects among different modes, can realize direct reading of pixel signals or combination output of the pixel signals, and can adapt to the needs of different application scenes.
Drawings
FIG. 1 is a block diagram of a sensing circuit according to an embodiment of the present disclosure;
FIG. 2 is a timing diagram of a black and white pixel array row merge read out in accordance with an embodiment of the present disclosure;
FIG. 3 is a schematic block diagram of a readout circuit and a digital circuit in an image sensor according to an embodiment of the disclosure;
FIG. 4 is a schematic diagram of a 4 row 6 column black and white pixel array in accordance with an embodiment of the present disclosure;
fig. 5 is a schematic diagram of a column-by-column readout sequence of row-combined pixel signals of a 4-row 6-column black-and-white pixel array according to an embodiment of the present disclosure;
FIG. 6 is a schematic diagram of a combined readout sequence for a 4 row 6 column black and white pixel array 2x2 in accordance with an embodiment of the present disclosure;
FIG. 7 is a timing diagram of a color pixel array row merge readout according to an embodiment of the disclosure;
FIG. 8 is a schematic diagram of a 4 row 8 column Bayer pixel array according to an embodiment of the disclosure;
fig. 9 is a schematic diagram of a row-merging pixel signal interval column readout sequence of a 4-row 8-column Bayer pixel array according to an embodiment of the present disclosure;
fig. 10 is a schematic diagram of a 4 row 8 column Bayer pixel array 2x2 merge readout sequence according to an embodiment of the present disclosure.
Detailed Description
As described in the background art, under the specific application requirement, the pixel signals need to be read out in a merging way, but the current pixel merging read-out scheme needs to buffer the pixel signals of at least one row of pixel units in advance when merging, which increases the chip area.
The embodiment of the disclosure provides a readout circuit and an image sensor, which can realize the non-buffer combination of pixel signals of pixel units in different rows and columns, thereby saving the chip area.
In order to make the objects, technical solutions and effects of the present disclosure clearer and more apparent, the present disclosure will be further described in detail below with reference to the accompanying drawings in combination with preferred embodiments. It should be understood that the description of the specific embodiments is intended for purposes of illustration only and is not intended to limit the scope of the present disclosure.
Embodiments of the present disclosure provide a sensing circuit including: a pixel array including a plurality of rows and columns of pixel units; a column counter adapted to obtain corresponding pixel signals of a plurality of rows of pixel units on a specific column in the pixel array; the column counter is reset after acquiring row-combined pixel signals of corresponding pixel signals of a plurality of row pixel units on a specific column.
The following describes a readout circuit provided in an embodiment of the present disclosure in detail with reference to fig. 1 as a specific embodiment.
Referring specifically to fig. 1, the readout circuit includes: the pixel array 101, the column comparator 102, the column counter 103, the column latch 104 and the address decoder 105, wherein the number of the column comparator 102, the column counter 103 and the column latch 104 is the same as the number of columns of the pixel array 101. The pixel array 101 includes a plurality of rows and columns of pixel units; the column comparator 102 is adapted to compare the analog pixel signal of the pixel unit on the specific column of the strobed row in the pixel array 101 with the reference signal, and convert the analog pixel signal into a digital pixel signal to be output to the column counter 103, and in the following detailed description, "pixel signal" is used to denote the digital pixel signal of the pixel unit output from the column comparator 102 to the column counter 103; the column counter 103 is adapted to obtain corresponding pixel signals of a plurality of rows of pixel units on a specific column in the pixel array 101, and combine the pixel signals of the plurality of rows of pixel units on the specific column; the column latch 104 is adapted to latch the row-combined pixel signal obtained by the column counter 103 on the corresponding column after receiving the latch signal; the address decoder 105 is adapted to serially read out the row-combined pixel signals in each of the column latches 104 between the latch signals to subsequent circuits for processing.
In some embodiments, the positive input of the column comparator is adapted to access a reference signal and the negative input is adapted to access an analog pixel signal of a particular strobe line of the pixel array.
In the embodiment shown in fig. 1, the reference signal is a ramp signal having a fixed slope and generated by a ramp signal generator 107.
In the embodiment shown in fig. 1, the readout circuit further includes a timing control module 108: the timing control module 108 is adapted to generate a reset signal to control the reset of the column counter 103, the timing control module 108 is further adapted to generate the latch signal to control the opening of the column latches 104.
As described above, the column counter acquires row-combined pixel signals of the corresponding pixel signals of the plurality of rows of pixel units on a specific column; next, as shown in fig. 2, after the row merging pixel signals of the specific rows are stored in each column counter, the timing control module generates the latch signals and controls each column latch to store the row merging pixel signals in the corresponding column counter; and then, the timing control module generates the reset signals, resets each column counter and prepares for the next row combination.
In the embodiment shown in fig. 1, the timing control module 108 may also control the row selection module 109 to gate a particular row. In some other embodiments, the timing control module may further control the ramp signal generator to generate a reference signal.
In some embodiments, the different rows of pixel units implementing the merging may be two adjacent rows of pixel units, i.e. the specific columns of pixel units are two adjacent rows of pixel units. In some other embodiments, the different rows of pixel cells implementing the merge may also be two rows of pixel cells spaced apart.
In some embodiments, when the row-combined pixel signals stored in the column latches are read out by the address decoder, row combination and storage of pixel signals of other rows may be performed simultaneously in each column comparator, column counter, and column latch of the readout circuit; in other words, in the process of reading out the row-combined pixel signals of the first two rows of pixel units, the row combination and storage of the pixel signals of the next two rows of pixel units are performed at the same time. The specific processes of performing the analog-to-digital conversion and storing are described in detail above, and are not described herein.
The embodiment of the present disclosure further provides an image sensor, and fig. 3 is taken as a specific embodiment to describe the image sensor provided in the embodiment of the present disclosure in detail.
Referring specifically to fig. 3, the image sensor includes: the pixel array 101, the column comparator 102, the column counter 103, the column latch 104, the address decoder 105 and the digital circuit 106, wherein the digital circuit 106 is configured to receive the row-combined pixel signal read out by the address decoder 105, and perform column combination on a plurality of columns of the row-combined pixel signal through the digital circuit 106. The readout circuit formed by the pixel array 101, the column comparator 102, the column counter 103, the column latch 104, and the address decoder 105 is described in detail above, and will not be described herein.
After the row-combined pixel signals are stored in the column latches 104 of the corresponding columns, the address decoder 105 serially reads out the row-combined pixel signals in each column latch 104 to the digital circuit 106 according to the acquired column address. Each time the digital circuit 106 reads two of the row-combined pixel signals, the two row-combined pixel signals are combined; specifically, after the row merging is completed, the latches 104 store row merging pixel signals of corresponding columns, the digital circuit 106 reads out one column of the row merging pixel signals from each latch 104 through the address decoder 105, and stores the column in the digital circuit 106, and after the digital circuit 106 reads out another column of the row merging pixel signals, the two row merging pixel signals are column-merged in the digital circuit, for example, two column row merging pixel signals can be merged by an adder, so as to realize 2x2 merging of pixel signals.
In some embodiments, the different column-row combined pixel signals implementing column combining may be two adjacent columns of pixel signals, i.e. the columns of the row combined pixel signals are two adjacent columns of pixel signals in the row combined pixel signals. In some other embodiments, the different column-row combined pixel signals that implement column combining may also be two columns of pixel signals that are spaced apart.
In some embodiments, the order in which the address decoder reads out the row-combined pixel signals is related to receiving a column address provided by the digital circuit.
As an embodiment, a schematic diagram of a readout sequence of 2×2 combined readout of pixel signals for a pixel array is shown in fig. 4-6. Fig. 4 shows a schematic diagram of a 4 row 6 column black and white pixel array. When the row combination of the pixel signals is performed, the timing control module sends a row selection signal to control the row selection module to gate the first row. In other embodiments, other rows of pixel cells may be gated as well.
Then, converting the analog pixel signals of the first row of pixel units into digital pixel signals of the selected row through each column comparator and column counter, and storing the digital pixel signals in the column counter of the corresponding column; hereinafter, a digital pixel signal is denoted as "pixel signal". Then, the timing control module controls the row selection module to gate a second row, and pixel signals of the pixel units of the second row are stored in the column counters of the corresponding columns by the same method; in other words, the second row pixel signal is counted in each of the column counters based on the pixel signal of the first row pixel unit, so that the row combined pixel signal is stored in each of the column counters; after the pixel signals of the two rows of pixel units are combined, the time sequence control module sends latch signals to enable each latch to store the row combined pixel signals of the corresponding column; and then, the timing control module generates a reset signal to reset each column counter, so as to prepare for storing the pixel signals of the corresponding columns of the pixel units of the next row in each column counter.
The address decoder reads the row-merging pixel signals column by column into a digital circuit according to the received column address, and the sequence of reading the row-merging pixel signals of the 4-row 6-column black-and-white pixel array after the row merging is completed is shown in fig. 5; in the column-by-column readout process, column-merging can also be performed on the row-merged pixel signals; when the column combination is performed, the digital circuit performs column combination of the two row combination pixel signals in the digital circuit every time the digital circuit reads out the two row combination pixel signals, and the pixel signal reading sequence after the column combination is completed is shown in fig. 6. In the above disclosed embodiment, the row-combined pixel signals for performing column-combination are two adjacent columns-row-combined pixel signals, so as to implement 2x2 combination of pixel signals of the black-and-white pixel array.
In the above embodiment, the readout circuit performs the combination of the pixel signals of the two rows and two columns of pixel units, so as to realize 2x2 combination of the pixel signals. In some other embodiments, the pixel signals of the pixel units of the rows and the columns can be combined, so that the pixel signals of the pixel units of the n rows and the n columns are combined. The manner of merging the pixel signal lines of the multi-line pixel units is the same as that of merging the pixel signal lines of the two-line pixel units, and the manner of merging the columns of the multi-column line merged pixel signals is the same as that of merging the columns of the two-column line merged pixel units, which are not repeated here.
In some embodiments, when the image to be subjected to pixel merging is a color image, since the color filter array in the image sensor is more than two rows and is one period, the timing control module may control the two rows of pixel units of the row selection module gating interval to perform merging of the pixel signals of the corresponding columns during the color merging.
In some embodiments, when 2x2 merging of pixel signals is performed on a color image, the merged readout timing of the color pixel array is as shown in fig. 7, and after two rows of co-channel pixel signals are stored in each column counter, the timing control module generates latch signals to open the latches so as to store the row merged pixel signals in the column latches of the corresponding columns; and then, the timing control module generates a reset signal to control the reset of each column counter so as to prepare for storing the pixel signals of the pixel units of the next row. The combined readout timing of the color pixel array is similar to that of the black-and-white pixel array, and will not be described again here.
In a specific embodiment, the color filter is in Bayer format, and the readout sequence for performing 2×2 merged readout of pixel signals on a Bayer array of 4 rows and 8 columns is specifically shown in fig. 8-10. Fig. 8 shows a Bayer array of 4 rows and 8 columns, whose arrangement pattern of color filters is one cycle in two rows. When the pixel signals are combined, the time sequence control module controls the row selection module to gate the first row of pixel units, and the pixel signals of the first row of pixel units are stored in the column counters of corresponding columns after passing through the column comparators and the column counters similar to a black-and-white pixel array; then, a third row of pixel units with the same optical filter arrangement rule as the first row of pixel units is selected, and pixel signals of the third row of pixel units are stored in each column counter by the same method, wherein when the third row of pixel signals are stored in each column counter, the pixel signals of the first row of pixel units are also stored in each column counter, namely, the third row of pixel signals are counted in the column counter of the corresponding column on the basis of the first row of pixel signals, so that row merging pixel signals of the first row of pixel units and the third row of pixel units are stored in each column counter; then, the timing control module sends a latch signal to each column latch, so that each column latch stores the row combination pixel signal of the corresponding column; after the row merging pixel signals of the corresponding columns are stored in each column latch, the time sequence control module generates a reset signal to reset each column counter.
When the pixel signals of the color images are combined, the readout circuit provided by the embodiment of the disclosure can gate two rows of pixel units at intervals to perform row combination of the pixel signals of the same channel in each column counter, pixel signals of the pixel units of the plurality of rows do not need to be cached, and the area for storing the pixel signals in the digital circuit can be reduced, so that the chip area is reduced.
For each row of the combined pixel signals stored in the column latches, the address decoder gates the column latches corresponding to the column address according to the received column address; reading all row combined pixel signals in each column latch into a digital circuit according to the sequence of the gated column latches; in the digital circuit, column combination of two column-row combined pixel signals may be performed.
In color application, the sequence of reading out the row-merging pixel units is shown in fig. 9, after the address decoder reads out the first column-row-merging pixel signals, the first column-row-merging pixel signals are stored in a digital circuit, then the address decoder reads out the third column-row-merging pixel signals, and then the first column-row-merging pixel signals and the third column-row-merging pixel signals are directly subjected to row-column merging in the digital circuit, so that 2x2 merging of the color pixel array and the channel pixel signals can be realized, and a 2x2 merging reading-out sequence diagram of the 4-row 8-column Bayer array is shown in fig. 10.
When the row-merging pixel signals of the same channel pixel signal are read out, the address decoder can control the gating interval column, so that the row-merging pixel signals read out by the address decoder and the row-merging pixel signals read out by the address decoder are the same channel signals, and 2x2 pixel merging of the color image can be realized by storing one row-merging pixel signal in the digital circuit without additionally storing one row-merging pixel signal, thereby reducing the chip area for storing the pixel signals.
In some other embodiments, if the color filter array uses a plurality of rows and columns as a period, the timing control module may also control the row selection module to gate the rows and columns at the same interval as the filter arrangement rule for color combination.
The embodiment of the disclosure further provides an image sensor, which includes a mode selection module adapted to select a readout mode of a readout circuit, where the readout mode includes a merge mode, and where the image sensor includes the readout circuit according to any one of the embodiments, and where the readout circuit includes an address decoder.
In some embodiments, the image sensor further comprises: and the digital circuit is used for receiving the row merging pixel signals read out by the address decoders in the merging mode and carrying out column merging on a plurality of columns of the row merging pixel signals in the digital circuit. In some embodiments, the order in which the address decoder reads out the row-combined pixel signals is related to receiving a column address provided by the digital circuit. In some specific embodiments, the row-combined pixel signals for column-combining may be two adjacent columns of pixel signals in the row-combined pixel signals. In some other embodiments, the row-combined pixel signals for column-combining may be two columns of pixel signals spaced apart in the row-combined pixel signals.
In some embodiments, the readout mode includes a merge mode and a non-merge mode. In the merging mode, when pixel signals of a row of pixel units are stored in each column counter, the time sequence control module does not generate latch signals and reset signals; when row merging pixel signals of two rows of pixel units exist in each column counter, the time sequence control module generates the latch signals and the reset signals to control the latch of the column latch and the reset of the column counter. In the non-merging mode, for example, when the pixel signals of one row of pixel units are stored in each column counter in the non-merging mode, the timing control module generates a latch signal to control the corresponding column latch to store the pixel signals of one row of pixel units, and then the timing control module generates a reset signal to reset each column counter to prepare for storing the pixel signals of the next row of pixel units.
In some embodiments, the mode selection module includes a register in the timing control module. The register marks the merging mode and the non-merging mode, and the time sequence control module enters different modes through the marks of the register. In the readout circuit described in the above embodiment, the timing control module is in the merge mode.
While the foregoing embodiments have disclosed the technical content and features of the present disclosure, the description thereof is more specific and detailed, but the description of the above embodiments is illustrative rather than limiting, and under the inventive concept of the present disclosure, those skilled in the art can make various changes and modifications to the disclosed concept, but all fall within the scope of the present disclosure, which is defined by the claims.
Claims (20)
1. A readout circuit, comprising:
a pixel array including a plurality of rows and columns of pixel units;
the column counter is suitable for acquiring corresponding pixel signals of a plurality of rows of pixel units on a specific column in the pixel array, and combining the corresponding pixel signals of the plurality of rows of pixel units on the specific column to acquire a row combined pixel signal corresponding to the corresponding pixel signals of the plurality of rows of pixel units on the specific column;
the time sequence control module is suitable for generating a reset signal so as to control the reset of the column counter after the column counter obtains the row merging pixel signals;
and the column latch is suitable for latching the row merging pixel signals obtained by the column counter on the corresponding column, and latches after the column counter obtains the row merging pixel signals and before the column counter resets.
2. The readout circuit of claim 1, wherein the rows of pixel cells on a particular column are two rows of pixel cells adjacent to the particular column.
3. The readout circuit of claim 1, wherein the rows of pixel cells on a particular column are two rows of pixel cells spaced apart on a particular column.
4. The readout circuit of claim 1, wherein the timing control module is further adapted to generate a latch signal to control the opening of the column latches.
5. The readout circuit of claim 1, further comprising: an address decoder adapted to read out the row-combined pixel signals in the column latches.
6. An image sensor, comprising:
a pixel array including a plurality of rows and columns of pixel units;
the column counter is suitable for acquiring corresponding pixel signals of a plurality of rows of pixel units on a specific column in the pixel array, and combining the corresponding pixel signals of the plurality of rows of pixel units on the specific column to acquire a row combined pixel signal corresponding to the corresponding pixel signals of the plurality of rows of pixel units on the specific column;
a timing control module adapted to generate a reset signal to control the reset of the column counter after the column counter acquires the row-combined pixel signal;
an address decoder adapted to read out the row-combined pixel signals; and
a digital circuit adapted to receive the row-combined pixel signals read out by the address decoder and combine a plurality of columns of the row-combined pixel signals by the digital circuit;
and the column latch is suitable for latching the row merging pixel signals obtained by the column counter on the corresponding column, and latches after the column counter obtains the row merging pixel signals and before the column counter resets.
7. The image sensor of claim 6 wherein the order in which the address decoder reads out the row-combined pixel signals is related to receiving a column address provided by the digital circuit.
8. The image sensor of claim 6, wherein the plurality of rows of pixel cells on a particular column are two adjacent rows of pixel cells on a particular column; the columns of the row-combined pixel signals are two adjacent columns of pixel signals in the row-combined pixel signals.
9. The image sensor of claim 6, wherein the plurality of rows of pixel cells on a particular column are two rows of pixel cells spaced apart on a particular column; the columns of the row-combined pixel signals are two columns of pixel signals spaced in the row-combined pixel signal.
10. The image sensor of claim 6 wherein the column counter is reset after acquiring row-combined pixel signals for rows of pixel cells on the particular column.
11. The image sensor of claim 6, wherein the timing control module is further adapted to generate a latch signal to control the opening of the column latches.
12. An image sensor, comprising:
the sensing circuit of any of claims 1-5, the sensing circuit comprising an address decoder; and
and the digital circuit is suitable for receiving the row merging pixel signals read out by the address decoder and carrying out column merging on a plurality of columns of the row merging pixel signals through the digital circuit.
13. The image sensor of claim 12 wherein the order in which the address decoder reads out the row-combined pixel signals is related to receiving a column address provided by the digital circuit.
14. The image sensor of claim 12, wherein the plurality of columns of row-wise combined pixel signals are two adjacent columns of pixel signals in the row-wise combined pixel signal.
15. The image sensor of claim 12, wherein the plurality of columns of row-wise combined pixel signals are two columns of pixel signals spaced apart in the row-wise combined pixel signal.
16. An image sensor, comprising:
a mode selection module adapted to select a read-out mode, the read-out mode comprising a merge mode in which the image sensor comprises the read-out circuit of any of claims 1-5, the read-out circuit comprising an address decoder.
17. The image sensor as in claim 16, further comprising: and the digital circuit is suitable for receiving the row merging pixel signals read out by the address decoder in the merging mode and carrying out column merging on a plurality of columns of the row merging pixel signals through the digital circuit.
18. The image sensor of claim 16 wherein the order in which the address decoder reads out the row-combined pixel signals is related to receiving a column address provided by a digital circuit.
19. The image sensor of claim 17, wherein the plurality of columns of row-wise combined pixel signals are two adjacent columns of pixel signals in the row-wise combined pixel signal.
20. The image sensor of claim 17, wherein the plurality of columns of row-wise combined pixel signals are two columns of pixel signals spaced apart in the row-wise combined pixel signal.
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| CN202111000521.3A CN113612948B (en) | 2021-08-27 | 2021-08-27 | Readout circuit and image sensor |
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| CN202111000521.3A CN113612948B (en) | 2021-08-27 | 2021-08-27 | Readout circuit and image sensor |
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| CN113612948B true CN113612948B (en) | 2024-03-05 |
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