CN1681290A - Method and circuit for performing correlated double sub-sampling (CDSS) of pixels in an active pixel sensor (APS) array - Google Patents

Abstract

Provided is a method and circuit for performing pixel CDSS by an APS array. A pixel outputs an image signal voltage after outputting a reset voltage. A sub-sampling method and apparatus includes the steps of: sub-sampling a plurality of pixels (L2), storing L2 analog reset charges outputted from the L2 pixels into a first set of N2 capacitor and compositing the L2 analog reset charges; storing L2 analog image signal charges outputted from the L2 pixels in the first set of N2 capacitor and compositing the L2 analog image signal charges; and subtracting voltage VR indicated by the composited L2 reset charge from voltage VS indicated by a composited image signal charge and generating a differential voltage VS-VR.

Description

Pixel in the sensor array is carried out the Method and circuits of correlated double sub sampling

Technical field

The present invention relates to imageing sensor, be particularly related to a kind of can be to CMOS active pixel sensor (APS, Active Pixel Sensor) a plurality of pixels that Dynamic Selection goes out in array N * M pixel region are carried out correlated double sub sampling (Correlated Double Sub-Sampling (CDSS), carry out sub sampling and then carry out correlated double sampling (CDS, Correlated Double Sampling)) method and circuit.

Background technology

Since 20th century the mid-80s, general image pick device (imageing sensor) is a charge-coupled device (CCD).Along with the development of semi-conductor industry, the CCD performance has obtained rapid raising, finally develops into current minitype high-performance video camera.Yet in fact charge coupled device ccd is main image pick-up device, and the core of digital camera, the shortcoming of ccd sensor are that it has consumed than higher energy, and do not support high speed operation.In light of this situation, the large-scale cmos image sensor (CIS) that several million pixels (Mps) high definition is provided is greatly developed.Except its performance allows very a large amount of pixels to be carried out layout and to carry out the data scanning at a high speed with high density, cmos image sensor (CIS) consumes seldom energy (approximately be the energy that consumed of existing CCD chip 1/5), and this is the remarkable advantage that is better than current employed standard CC D.Another advantage is that cmos sensor has lower manufacturing cost: can provide with very low cost even the cmos sensor of large-size.Utilization and MOSFET or the identical treatment step of CMOS transistor, or on identical with it chip, just can produce cmos image sensor, thus can on same chip, form signal processing circuit, reduce interconnection wiring thus.In addition, the driving voltage that cmos sensor need be littler than CCD, and, can advantageously dwindle its size owing to peripheral circuit can be installed on the chip.Thus, the expection cmos sensor will become image sensing device (replacer of CCD solid-state image pickup apparatus) crucial in the digital imaging system of following widespread adoption.

Ccd sensor and cmos sensor exist greatest differences in the view data scan method.For instance, resolution for 3,000,000 pixels, with with transmit the identical mode of bucket from a people to another person, ccd sensor scans 3,000,000 (simulation) electric charges continuously, and only just amplifies (is the signal of telecommunication with charge conversion) usually after having scanned last pixel element.On the contrary, cmos sensor, CMOS active pixel sensor (APS) array (referring to the APS array among Fig. 1) for example all provides an amplifier (amplifier means transistor or electric charge become other transducers of the signal of telecommunication) here, at each pixel.Thus, it can be carried out signal and amplifies on each pixel basis, thereby reduces the transmission operation, thus it with still less energy consumption come scan-data more apace.

Correlated double sampling (CDS)

Electric charge in the cmos image sensor is the capacitor with single (or multistage) voltage follower (voltage follower) (amplifier transistor) to electric pressure converter basically, and condenser voltage is preset (" resetting ") switch to " known " original levels place.In the simplest video system, when the beginning that each pixel is read, close this switch, and this makes condenser voltage and output level reset.After pixel charge packet (charge packet) was transferred to capacitor, its voltage changed, and output signal remarked pixel value.Parts such as switch for example, because its limited residual electricity conductance (conductivity), it can reach capacitor precharge one unknown numerical value, and this has increased the error of output signal.The probabilistic method of the above-mentioned precharge of compensation---correlated double sampling (CDS) is arranged luckily.In the method, at each pixel output signal is carried out double sampling---just after capacitor is carried out precharge and after adding the pixel charge packet.The difference of above-mentioned two numerical value has been got rid of the noise component(s) of being introduced by switch (electric charge).

Correlated double sampling, or CDS are a kind of methods that is used to improve the signal to noise ratio (S/N) of integrated image sensor.By from photoinduction (light-induced) signal of reality, deducting " deceiving " or " reference " or " resetting " output (electric charge) level of pixel, can from the output of transducer (APS array), remove stationary diagram noise (FPN, fixed pattern noise) and multiple transient noise effectively.

Fig. 2 is that the conventional correlated double sampling of expression (CDS) circuit (for example, is formed on CDS﹠amp among Fig. 1; In the ADS square) structure chart, this circuit is applicable to that 4 CDS sampled pixel values to same colored pixels in APS array 4 * 4 pixel regions of being stored are similar on average.Utilize line driver (for example referring to Fig. 1) to select two row, selected two row that go out comprise four and will be sampled by CDS and then will be by average together pixel.

In optical sensor (APS) array, utilize photodiode (PD) to collect optical charge usually, and it can be stored on the capacitor C in each pixel element.From this electric capacity, read optical charge, as the voltage (V=Q/C) of this electric capacity.Utilize the CDS process, signal voltage Vs=Qs/C compared with " deceiving ", " sky ", " reference " or " resetting " level voltage Vr=Qr/C, level voltage Vr be when all electric charges with C all are directed to fixed potential and (for example in advance) obtain.Thus, all obtain final output voltage V=Vs-Vr=(Qs-Qr)/C at each pixel.Can carry out the CDS process at " on the chip (on-chip) " by on the chip piece identical, making circuit, or carry out the CDS process by " breaking away from chip (off-chip) CDS " with CMOS active pixel sensor (APS) array (with reference to the APS array among the figure 1).Usually CDS process need memory (for example, a charge storage capacitor), an and subtracter of pixel needs that will carry out the CDS sampling at each row.

In the circuit of Fig. 2, provide four capacitors (50a, 51a, 50b, 51b) to be used to store four numerical value, and provide switch 2,21a and 21b so that four electric charges being stored are carried out " image averaging processing " from four pixels.Provide each capacitor 50a, 51a, 50b, 51b to store an electric charge (Qs-Qr), so that the final output voltage V (V=Vs-Vr) of the simulated image data of a pixel of output expression.Two pixel values that provide each switch 21a and 21b to merge and divide (on average) together to be stored (pixel order from the different rows of same row obtains).For example, when off switch 21a, and when all having stored a sampled pixel value (from row 1) among the capacitor 50a of each identical size and the 51a, the electric charge on two capacitors merges, equilibrium, and between two capacitor 50a and 51a, be evenly distributed (division).So, so to averaging from the sampled pixel value on the different rows of same row.Provide switch 2 to merge together and divide (on average) and come from sampled pixel value (or average sample pixel value) on two different lines (for example row " 1 " and " 3 ").For example, when off switch 2,21a and 21b, and when each has the average together sampled pixel value (from the pixel in the row " 1 " and " 3 ") of capacitor 50a, 51a, the 50b of identical size and 51b storage, the electric charge that is stored in all four capacitors (50a, 51a, 50b and 51b) merges, equilibrium, and between four capacitors, be evenly distributed (division).So, so the sampled pixel value from four pixels (same color) of two different rows and two different lines is averaged.If open switch 21a and 21b when switch 2 cuts out, then the circuit of Fig. 2 will be only averages together to (from delegation and two different lines) two pixel values that are stored among capacitor 50a and the 50b.

Via amplifier 54 (for example 54a and 54b),, each final average CDS sampled pixel value sequentially is transferred to analog-digital converter (ADC) (not shown) then via column select switch (for example transistor) 20 with via common output line 30.

Fig. 2 comprises two identical circuit (" a " and " b "), each circuit is connected via the vertical selection wire (" CL1 " or " CL3 ") of sampling maintained switch 42 (42a or 42b) by separately, be used for the pixel on one of two row (for example, row " 1 " or row " 3 ") is carried out the CDS sampling.Utilization sampling maintained switch 42, will sample keeps electric capacity 44 can interruptedly be connected to vertical selection wire, and sampling keeps electric capacity 44 to be used for keeping from resetting or signal charge that the pixel of APS array is exported.Keep electric capacity 44 to connect reference voltage source 46 (for example 46a and 46b) and sampling.Simulation (electric charge) subtracter keeps electric capacity 44 (44a or 44b), amplifier (for example non-inverting buffer) 48 (48a or 48b) and CDS electric capacity 50 (50a or 50b) to form by sampling.The output node (end of CDS electric capacity 50) of subtracter is connected with the input of output amplifier 54.Can in CDS electric capacity 50, duplicate the electric charge that (copy) keeps by closing clamp switch 52 in sampling maintenance electric capacity 44, because the voltage output corresponding to the non-inverting buffer (amplifier) 48 that is kept electric capacity 44 stored charge quantity by sampling can make equivalent voltage (and equal charge) be stored in the CDS electric capacity 50.By opening clamp switch 52, can make CDS electric capacity 50 have quick condition (voltage/electric charge that its storage keeps electric capacity 44 to duplicate from sampling) afterwards.

Thus, in the future self-supporting fixation element, keep electric capacity 44 to receive by sampling at first and first electric charge (for example " signal " charge Q s) that keeps duplicates and is stored in the CDS electric capacity 50, and then can keep electric capacity 44 to receive and keep second electric charge (charge Q r for example " resets ") by sampling from same pixel.

Therefore, in operation, at first with signal voltage VS (via vertical selection wire CL1 for example, from a pixel) be applied to the input node of electric capacity 44 (sampling keep) of subtracter, and owing to closed clamp switch 52 (at the ON state), signal voltage VS from this pixel keeps electric capacity 44 to charge to sampling, and also CDS electric capacity 50 is charged.Then, opening clamp switch 52 (transferring OFF to) afterwards, output reset potential (voltage) VR (via vertical selection wire CL1 for example, from same pixel), thereby resetting voltage VR is inputed to the input of analog subtracter, and keep electric capacity 44 to keep by sampling.As a result, produce difference signal (VS-VR) at the output (at an end of CDS electric capacity 50) of analog subtracter corresponding to the difference of signal voltage VS and resetting voltage VR.Thus, might obtain the analog pixel data of the CDS sampling of a pixel, wherein remove the fixed pattern noise component that is superimposed upon on signal voltage VS and the resetting voltage VR.When off switch 20, can via common output line 30, again via amplifier 54, by switch 20, export the analog pixel data of this CDS sampling.

Provide each capacitor 50a, 51a, 50b and 51b to store an electric charge (for example, Qs or Qr), so that the final output voltage V (V=Vs-Vr) of the simulated image data of a pixel of output expression.

It is said that " difference signal (VS-VR) " is " being kept by CDS electric capacity 50 ", so four complete difference signals (VS-VR) of four CDS sampled pixel of each CDS electric capacity (50a, 51a, 50b, 51b) storage.Yet, in fact be difficult in (and when change is by non-return buffer (amplifier) 48 voltages of being exported) in the electric charge that change keeps in sampling keeps electric capacity 44, the electric charge of complete difference signal (VS-VR) can be accurately represented in maintenance in a CDS electric capacity 50 (for example one of 50a, 51a, 50b, 51b) separately.In fact, CDS electric capacity 50 (for example 50a, 51a, 50b, 51b) can only store with from an electric charge of given pixel (first electric charge that receives from this pixel for example, in charge Q r or " signal " electric charge (Qs) one for example " resets ") voltage that is associated, rather than the complete difference signal (VS-VR) that is associated with Qs-Qr.

Thus, even keeping electric capacity 44 (44a by two samplings, one of 44b) receive and keep before " resetting " charge Q r of four pixels, at first image " signal " the charge Q s (rather than " resetting " charge Q r) of each in these four pixels is stored in CDS electric capacity 50a, 51a, 50b, among one of 51b, and then merge and at CDS electric capacity 50a, 51a, 50b, divide these four (floating) " signal " charge Q s between the 51b and (be stored in CDS electric capacity 50a, 51a, 50b, among the 51b), export two " resetting " electric charges (being stored in two samplings keeps in the electric capacity 44) that also will only receive from (arbitrary subtracter) result of amplifier 54 (for example 54a or 54b) based on two pixel-by-pixel basis from four pixels.Thus, the result of subtracter output (from amplifier 54) is can sequentially obtain so that the mathematics " mean value " of the pixel value (VS-VR) that four process CDS that export from the circuit of Fig. 2 sample with " no ".In this case, only there are two " resetting " charge/voltage that received to carry out " on average " with four " signal " charge/voltage of being stored.

Thus, the certain operations of the circuit of Fig. 2 can be given four pixels (average together) with the error distribution that is produced by still image noise component(s) (for example in one or two pixel in four pixels), rather than fully deletes this error from the average pixel value that is speculated as four pixels of expression.

The image that utilizes pel array to catch in the digital camera is carried out the ability of sub sampling, reducing under the useful situation of resolution is useful, for example, in moving image (video) trap mode, reduce bit rate, perhaps make it possible to display image on the display that reduces resolution.The processing time that the sub sampling that carries out in numeric field (after analog-to-digital conversion) needs jumbo memory usually and consumes additional electrical energy.

Circuit among Fig. 2, and the closely-related known circuit that pixel sub is sampled is carried out in other analog domain " on average " operations that are used for by Fig. 2, only be only applicable to by four pixels of each color in 4 * 4 pixel regions are carried out " on average " together, and in the Baeyer graphic array (Bayer-pattern array) through the pixel execution sub sampling of CDS sampling.

Summary of the invention

Exemplary embodiment of the present invention provides a kind of imageing sensor, it comprises a plurality of pixels of arranging with row and column, and each row pixel is connected at least two reseting data capacitors of at least two reset charge of storage and at least two view data capacitors storing at least two image charges convertiblely.

This imageing sensor is carried out to the N row that are arranged in CMOS active pixel sensor (APS) array and N the N on capable ²Individual pixel is carried out the method for sub sampling, and each pixel all is suitable for exporting resetting voltage and image signal voltage, and this method may further comprise the steps: the resetting voltage of storage first pixel is as first electric charge in first capacitor; The resetting voltage of storage second pixel is as second electric charge in second capacitor; And first and second electric charges are merged into average reset charge.

The method of pixel being carried out sub sampling comprises: will be from the APS array L ²The L that individual pixel-by-pixel basis is received ²Individual analog pixel reseting data charge storage is to first group of N ²In the individual capacitor; Will be from the APS array L ²The L that individual pixel-by-pixel basis is received ²Individual analog pixel image signal data charge storage is to second group of N ²In the individual capacitor.The scope of L can be to N from 1.To being stored in first group of N ²L in the individual capacitor ²Individual analog pixel reseting data electric charge is carried out first average operation.And, to being stored in second group of N ²L in the individual capacitor ²Individual analog pixel image signal data electric charge is carried out second average operation.

Imageing sensor comprises the average and comparing unit (ACU) that is connected with each row pixel.The ACU co-operation to be carrying out average operation in analog domain, and is used for deducting (still in analog domain) average reset charge (from identical a plurality of pixels) from average signal electric charge (from a plurality of pixels), so that produce differential voltage.Imageing sensor also will comprise analog-digital converter (ADC), be used for differential voltage is carried out the conversion of analog to digital.

Another embodiment of the present invention provides a kind of and carries out sub sampling (the sub sampling ratio is 1: L being arranged in pel array in a plurality of row and a plurality of row ²) method, each pixel all is suitable for exporting resetting voltage and image signal voltage, this method may further comprise the steps: merge together from a plurality of (L ²) a plurality of (L of pixel output ²) the analog reset data charge is (for example, to being stored in first group of L in the holding capacitor ²Individual reset charge merges); And merge together from a plurality of (L ²) a plurality of (L of pixel output ²) the analog picture signal data charge is (for example, to being stored in second group of L in the holding capacitor ²Individual picture signal electric charge merges).Utilize (average) the reseting data electric charge of merging and the image signal data electric charge (rather than resetting and image charge) of merging (for example to carry out correlated double sampling (CDS) operation from single pixel, correlation technique is known), thereby obtain differential voltage (VS-VR), this differential voltage (VS-VR) expression is to the L of same color ²The accurate mathematics " mean value " that individual pixel averages.

By to by following relation (equation) represented, the observation of the mathematics " mean value " of four CDS sampled pixel values of a kind of color of expression (electric charge that quantity is determined by Qs-Qr) in 4 * 4 pixel regions in the Baeyer graphic array (suppose in the subtracter all capacitors all have equal capacity C and when linking to each other, all be recharged) with same Vref, susceptible of proof is by the accuracy of performed " on average " (and sub sampling) function of exemplary embodiment of the present, and described relation (equation) is:

$Q_{\mathrm{AVG}}=\frac{1}{4}((Q_{S11}-Q_{R11})+(Q_{S13}-Q_{R13})+(Q_{S31}-Q_{R31})+(Q_{S33}-Q_{R33}))$

And, because the distribution and additive inverse (the Distributive and Additive Inverse) characteristic of addition:

$Q_{\mathrm{AVG}}=\frac{1}{4}(Q_{S11}+{\mathrm{<figure-callout\; id="13"\; label="Q\; S"\; filenames="A20051007415800341.png"\; state="\{\{state\}\}">Q</figure-callout>}}_S+Q_{S31}+Q_{S33})-\frac{1}{4}(Q_{R11}+{\mathrm{<figure-callout\; id="13"\; label="Q\; R"\; filenames="A20051007415800341.png"\; state="\{\{state\}\}">Q</figure-callout>}}_R+Q_{R31}+Q_{R33})$

From above-mentioned mathematical relationship, draw, by merging Q from four " signal " electric charges of four pixels _S11+ Q _S13+ Q _S31+ Q _S33In (simulation) deduct the merging (Q of four pixels of four " resetting " electric charges _R11+ Q _R13+ Q _R13+ Q _R33), can obtain and will together it be averaged accurate " on average " numerical value of four CDS sampled pixel values of (sub sampling) processing.By four have equal capacitance (for example, between capacitor C) (for example, the electric charge after distribute merging equally), just can be enough four " divided by " merging (for example, before " resetting " electric charge that " deducting " merges) of four " signal " electric charges.Similarly, afterwards by having the equal capacitance (electric charge after for example, (for example, equally) distribution merges between capacitor C) at four, just can be enough four " divided by " merging of four " resetting " electric charges (for example, from " signal " electric charge that merges " deducting " before).Thus,, can obtain " on average " numerical value of four CDS sampled pixel: " resetting " electric charges of four associations is merged and divide (on average, sub sampling), so that obtain average reset charge Q by carrying out following steps _RAVG" signal " electric charge of four associations is closed and divides (average, sub sampling), so that obtain the average signal charge Q _SAVGPass through from the average signal charge Q afterwards _SAVGIn deduct average reset charge Q _RAVGCarry out a correlated double sampling operation (subtraction).Here, this conventional method is called correlated double sub sampling (CDSS), because the result of this method is the accurate sub-sampled pixel values of the mathematical mean of four CDS sampled pixel of expression.Substitute as in correlation technique, carrying out the CDS subtraction four times, only need " average " (sub sampling) " resetted " and " signal " electric charge, carry out one time the CDS subtraction.Therefore, before final CDS subtraction, can accurately carry out sub sampling.

In exemplary embodiment of the present invention, can be in following three phases (take the integer of 2 powers certainly: for example with sub sampling rate B, 4,9,16,25 ...) carry out correlated double sub sampling CDSS, wherein B equals four: in the phase I, in column direction, two pairs of resetting voltages (electric charge) are averaged, and also on column direction, two pairs of signal voltages (electric charge) are averaged; In second stage, on line direction, obtain final (on average) resetting voltage, and on line direction, also obtain final (on average) image (signal) voltage by two pairs of average images (signal) voltage is averaged by two pairs of average resetting voltages are averaged; In the phase III, simulation deducts final (on average) resetting voltage (for example, by utilizing single analog subtracter) from final (on average) image (signal) voltage.Here in the exemplary embodiment, " on average " of electric charge comprises and (for example merging in the bigger more effective electric capacity being stored in four electric charges in the capacitor C, 4C), and (for example be included in right quantity, similar number) same capacitance (for example, divide by the electric charge that is combined between C).

Another exemplary embodiment of the present invention (for example provides a kind of imageing sensor, CIS), it comprises the pel array that is arranged in several rows and some row, each pixel in every capable pixel all is operably connected to averaging unit, wherein each averaging unit comprises: first and second holding capacitors are used to store and come from first pixel and from the analog reset data of second pixel; And third and fourth holding capacitor, be used to store and come from first pixel and from the analog picture signal data of second pixel.

Description of drawings

By exemplary embodiment being specifically described with reference to its accompanying drawing, make those skilled in the art can understand feature of the present invention, wherein represent components identical with identical Reference numeral:

Fig. 1 is the calcspar that the cmos image sensor (CIS) of the correlation technique that includes source pixel (APS) array is described;

Fig. 2 is in the explanation correlation technique, be applicable to that four pixels to same color be similar to the sample calcspar of (CDS) circuit of average correlated double;

Fig. 3 illustrates the calcspar of cmos image sensor (CIS) according to an exemplary embodiment of the present invention, the average and comparison circuit that it includes active picture sensor (APS) array and is used to carry out correlated double sub sampling (CDSS);

Fig. 4 is the circuit diagram of the exemplary configurations of each pixel of explanation in CMOS active pixel sensor (APS) array of the CIS unit of Fig. 3;

Fig. 5 is the Baeyer graphical distribution of the interior color sensor pixel of CMOS active pixel sensor (APS) array of key diagram 3 and the structure chart of output thereof;

Fig. 6 be explanation in the cmos image sensor (CIS) of Fig. 3, be positioned at be used to carry out correlated double sub sampling (CDSS) several on average and structure charts of the interconnection of the switches between the comparing unit (ACU);

The circuit diagrams of the average and comparing units (ACU) that Fig. 7 is in the cmos image sensor (CIS) that is described in detail in Fig. 3, two interconnect convertiblely;

Fig. 8 A is the explanation employed switching signal waveform and sequential chart of selecting (SEL) signal waveform of going in the cmos image sensor (CIS) of Fig. 3, during carrying out the correlated double sub sampling;

Fig. 8 B is the employed ramp voltage of analog-digital conversion (ramping voltage) waveform sum counter latch control signal waveform is carried out in explanation abreast to several outputs of average in the cmos image sensor (CIS) that comes from Fig. 3 and comparing unit (ACU) a sequential chart;

Fig. 9 is employed counter of analog-digital conversion and latch cicuit are carried out in explanation abreast to several several outputs that on average reach comparing unit (ACU) in the cmos image sensor (CIS) that comes from Fig. 3 a structure chart;

Figure 10 be explanation be positioned at be used to carry out correlated double sub sampling (CDSS) several on average and structure charts of the another kind of switches interconnection exemplary embodiment between the comparing unit, be used for the N in the APS array of the cmos image sensor (CIS) of Fig. 3 ²Individual pixel (with greater than 4 sub sampling rate) averages/and sub sampling handles; With

Figure 11 describes in detail according to another embodiment of the present invention, is used for the N in the APS array of the cmos image sensor (CIS) of Fig. 3 ²Individual pixel averages/circuit diagram of the average and comparing unit that sub sampling is handled.

Embodiment

Fig. 3 illustrates the structure chart of cmos image sensor (CIS) unit according to an exemplary embodiment of the present invention, the average and comparison circuit that it includes active picture sensor (APS) array and is used to carry out correlated double sub sampling (CDSS).Fig. 4 is the circuit diagram of the exemplary configurations of each pixel of explanation in CMOS active pixel sensor (APS) array of the CIS of Fig. 3.

With reference to figure 3 and Fig. 4, CMOS active pixel sensor (APS) array can be included in plurality of pixels circuit known in the correlation technique, or the image element circuit among Fig. 4 preferably, and it is applicable to sequentially exports VR (resetting) voltage and VS (picture signal) voltage.Usually each pixel in the APS array includes photoelectric transformer (transducer) (for example, the photodiode PD among Fig. 4).Row driver circuits is known circuit in the correlation technique normally, and according to exemplary embodiment of the present invention, here it is applicable to during carrying out correlated double sub sampling (CDSS), sequentially selects odd-numbered line (1,3 ...) to selecting even number line (2,4 then ...) right.Especially, one of use in several lines be provided for transmitting active row selection signal SEL, select (activation) active row.

When to being stored in charge/voltage in the electric capacity that is associated with the photodiode PD of pixel when reading, close the switch T that is controlled by signal TX _TXUsually during reset operation, open switch T _TXWith reset switch T _RXClose T together _TXThereby, also can the diffusion area (diffusion area) of the photodiode PD of pixel be resetted.Those skilled in the art can identify, and reset signal RX is used for control switch T _RX, switch T _RXWith the switch T that is controlled by signal TX _TXUse together, so that the charge/voltage that will be stored in the electric capacity that is associated with photodiode PD presets (" resetting ") to " resetting " level.

Transistor T _AMPBe " voltage follower " amplifier, the charge/voltage that is used for being stored in the electric capacity that is associated with photodiode PD changes the relevant voltage/electric current that becomes in the capacitor that enough is transferred to and is stored in average and the comparison circuit (with reference to figure 3 and Fig. 4).

When beginning to read each pixel, close switch T by reset signal RX control _RX, and this capacitance charge/voltage of closing being associated with PD resets." resetting " charge/voltage of the electric capacity that is associated with photodiode PD provides output-voltage levels VR (at off switch T at output node OUT place _SELDuring this time).When the APS array is exposed to true picture (light), the photodiode of each pixel will develop and luminous intensity (brightness) corresponding " image/signal " electric charge (voltage) that drops on this pixel (PD) with the electric capacity that is associated in array.As off switch T _TXAnd open switch T _RXThe time, will utilize amplifier T _AMPCome " amplification " actual sensitization " picture signal ", and as off switch T _SELThe time, actual sensitization " picture signal " will be used as " picture signal " voltage VS and be transferred to and be stored in the capacitor that on average reaches comparison circuit (with reference to figure 3 and Fig. 4).

Fig. 5 is the Baeyer graphical distribution of the interior color sensor pixel of CMOS active pixel sensor (APS) array of key diagram 3 and the structure chart of output thereof.Realize the Baeyer figure by the Baeyer figure color filter array (CFA) on the photodiode (PD among Fig. 4) of the APS array that is added to.Exemplary embodiment of the present invention is applicable to carries out " on average " (and correlated double sub sampling (CDSS)) together to the group of four pixels of same color, for example, is arranged on the red pixel R11 in 4 * 4 pixel regions, R13, R31, R33, for instance, highlighted pixel region in Fig. 5.Usually will be carried out the group of four pixels of CDSS sampling together and be formed with the same color pixel of identical two row, as the numeric field sub sampling of association area by coming from identical two row.Thus, will be together to red pixel R11, R13, R31, R33 carry out the CDSS sampling; And will be together (side by side) to green pixel G12, G14, G32 and G34 carry out CDSS sampling.Afterwards, will be together to green pixel G21, G23, G41 and G43 carry out the CDSS sampling, and also together to blue pixel B22, B24, B42, B44 carry out the CDSS sampling.The result that four groups of (red, green, blue, green) same color pixel are carried out the correlated double sub sampling produces four pixel values with red, blueness and green pixel corresponding accurate " on average " like this.Thus, at the performed correlated double sub sampling of the pixel region of APS array, when having proofreaied and correct stationary figure noise (FPN) and polytype transient state noise, effectively pixel region has been carried out sub sampling (in the simulation category).

Sequentially row selection signal SEL1 and the SEL3 that corresponds respectively to row 1 and 3 activated.When activating each row selection signal, all pixels in this active row at first read out its corresponding " resetting " voltage VR, read out " picture signal " voltage VS (referring to the figure among Fig. 8 A for example) of its reality then.As mentioning among Fig. 5, the output order of pixel comprises the signal (VR11, VS11 afterwards) of the pixel R11 that comes from filter red (Red-fi1tered) in the row 1, next is the signal (VR31, VS31 afterwards) that comes from the pixel R31 of filter red.Simultaneously, the output order of pixel comprises the signal (VR13, VS13 afterwards) of the pixel R13 that comes from filter red in the row 3, next is the signal (VR33, VS33 afterwards) that comes from the pixel R33 of filter red.In interchangeable embodiment, can put upside down the activation order of row 1 and row 3.And, though among Fig. 5 and not shown (but shown in Figure 6), in the row 2 pixel the time output comprise and come from the signal (VR12, VS12 afterwards) that filters green pixel G12, next be to come from the signal (VR32, VS32 afterwards) that filters green pixel G32; And pixel time output comprises and comes from the signal (VR14, VS14 afterwards) that filters green pixel G14 in the row 4, next is to come from the signal (VR34, VS34 afterwards) that filters green pixel G34.All pixel values had all carried out just exporting the pixel value in row 2 and 4 till the CDSS sampling in to row 1 and 3.

Fig. 6 is that explanation is positioned at several average structure charts that reach the switch interconnection between the comparing unit that are used to carry out correlated double sub sampling (CDSS) in the cmos image sensor (CIS) of Fig. 3.Each pixel in the row of APS array all with vertical transmission lines (by its corresponding T _SELSwitch) and an average and comparing unit (ACU) link to each other.Thus, the average and comparing unit that four shown in Fig. 6 are adjacent is corresponding to four adjacent pixels row (1,2,3,4) in the APS array.Thereby any time during read operation, ACU-1 and ACU-3 receive the analog pixel data that receive from same colored pixels place and (for example, at first receive from the pixel R11 of filter red and R13; Pixel R31 and R33 from filter red receives afterwards; Receive from filtering green pixel G21 and G23 afterwards; Receive from filtering green pixel G41 and G43 again).Thus, in order effectively received, relevant with same colored pixels analog pixel data to be carried out " on average " (in analog domain together merge), by the first average switch S avg with ACU-1 and ACU-3 each other (convertiblely) link to each other.Similarly, by the second average switch S avg with ACU-2 and ACU-4 each other (convertible ground) link to each other.In argumentation, will carry out more detailed explanation to the function of " on average " switch S avg to the detailed circuit diagram of Fig. 7 that ACU-1 and ACU-3 more specifically are shown.

Referring now to Fig. 7 and 8A, structure and method of operation average and comparing unit (ACU) in the cmos image sensor (CIS) of Fig. 3 are described.

Fig. 7 be explanation in the cmos image sensor (CIS) of Fig. 3, the detailed circuit diagram of two average and comparing units (ACU) that interconnect convertiblely.Fig. 8 A is the correlated double sub sampling is carried out in explanation in the cmos image sensor (CIS) of Fig. 3 during, be used for the switching signal waveform of ACU and the sequential chart of row selection (SEL) signal waveform.

By the corresponding T of each pixel _SELSwitch, will (Fig. 3's) on average reach each ACU in the comparison circuit (for example, ACU-1, ACU-2, ACU-3) with particular row in all pixels be connected (via vertical transmission lines) convertiblely.Thus, ACU-1---being comprised pixel R11 and R31---with each pixel in first pixel column (row 1) operationally links to each other.Equally, ACU-3---being comprised pixel R13 and R33---with all pixels in the 3rd pixel column (row 3) operationally links to each other.Usually, each pixel during each is listed as with the APS array and vertical transmission lines are (by its corresponding T _SELSwitch) and an average and comparing unit (ACU) operationally link to each other.During operation, via (level) line that links to each other with all pixels in the APS array delegation, select (SEL) control signal to activate a pixel in each row of APS array by row.If the pixel quantity on the row of APS array (integer) is W, then the quantity of ACU also will be W in average and comparison circuit.(in the interchangeable embodiment of the present invention, may connect more than W (for example, ACU 2W) is for use in W row) convertiblely.Thus as mentioned previously, during operation, comprise that all ACU by ACU-1 and ACU-3 will receive to come from simultaneously to be arranged on the analog pixel data of APS array with pixel in the delegation.

Shown in Fig. 8 A, at first activate row 1 (passing through SEL1), activate row 3 (passing through SEL3) afterwards.Thus, during operation, ACU-1 and ACU-3 catch (and storage) analog pixel data together, comprise " resetting " voltage and " picture signal " voltage of each pixel (for example, R11, R31, R13 and R33) that comes from four pixels of same color.Owing to by switch S avg ACU-1 is connected with ACU-3, so ACU-1 and ACU-3 can share from the analog pixel data of four pixels of same color (for example, R11, R31, R13 and R33) place acquisition.Particularly, ACU-1 and ACU-3 are applicable to that the pixel data to all kinds (" resetting " and " picture signal ") that obtain from four pixel places of same color merges and divides (on average, sub sampling), so that produce " on average " value of " resetting " charge/voltage VR and " on average " value of " picture signal " charge/voltage VS.Each ACU (for example ACU-1 and ACU-3) also is applicable to from " on average " value of " picture signal " charge/voltage " deducting " " reset " " on average " value of charge/voltage, so that the final analog pixel data of the accurate mathematical mean value of four pixels are expressed in output after through the CDS sampling, thereby have eliminated stationary figure noise (FPN).

Each ACU includes analog subtracter (for example, subtracter-1 and subtracter-3) and is used to receive the also amplifier AMP1 of the output of transportation simulator subtracter.Amplifier AMP1 (for example may be implemented as non-inverting buffer, Vref=0), perhaps as in the preferred embodiment of front, be implemented as the differential amplifier (differential amplifier) that depends on the reference voltage Vref that is used in combination with subsequently Parallel Simulation-digital quantizer (ADC).This set allows bias source (Vramp) to be in first voltage level during average operation, and is in second voltage level in ADC operating period, and first voltage level is different from second voltage level.The buffer capacitor (CA) and the second output amplifier AMP2 are optionally, and they are included in (shown in Fig. 7) in the preferred exemplary embodiment, so that increase gain for the resolution of ADC.The output of the analog domain subtracter in each ACU is carried out sensing by amplifier 1, and cushion by optional capacitor CA, and for analog-digital conversion, further amplify by the optional second amplifier AMP2, be output as the voltage signal (for example, VCD1 or VCD3) of the average VR-VS of expression.

Each analog domain subtracter in preferred exemplary embodiment (for example, subtracter-1) includes, and can consist essentially of, a plurality of data storage capacitor (for example, the CS11 among the ACU-1, CS31 that link to each other at a common node place each other, CR11, CR31), this node is arranged on the continuous vertical transmission lines of the pixel (pixel in the row 1 that for example, ACU-1 was applicable to) of the row that is applicable to by switch S 1 and ACU.All fill and stored in each of four data holding capacitors in each ACU from ACU (for example, ACU-1) pixel of Xiang Lianing (for example, pixel from first row of same column, or the pixel from the third line of same column) the predetermined analog pixel data charge that receives of place (for example, " reset " or " signal " data), this ACU is by by several switches (S1 for example, S2, S3, S4, SS, the order that the switch that SR) carries out connects is determined.Side by side open or close each ACU (and between the ACU, for example, Savg) respective switch in (S1 for example, S2, SS, SR, S3, S4).The ground that mates with each other, and with row selection signal as shown in the sequential chart of Fig. 8 A (for example, SEL) ordinatedly, open or close switch in each ACU (S1 for example, S2, SS, SR, S3, S4).

By master cock S1, S2, S3, S4, SS and SR, control pixel, four holding capacitors (for example, CS11, CS31, CR11, CR31) and the connection between other current paths, can fill four holding capacitors with the analog pixel data in the following order: holding capacitor CR11 storage comes from " resetting " electric charge of R11 (row 1, row 1); Holding capacitor CS11 storage comes from " signal " electric charge of pixel R11 (row 1, row 1); Holding capacitor CR31 storage comes from " resetting " electric charge of pixel R31 (row 1, row 3); Holding capacitor CS31 storage comes from " signal " electric charge of pixel R31 (row 1, row 3).

Interchangeable, during the non-CDSS pattern of ACU (for example, during standard CD S pattern), to be loaded into CR in each ACU (each ACU-1 and the AUC-3) " reset " one of data storage capacitor (for example, CR11 or CR31 from the analog pixel data that a pixel place receives; Perhaps be merged into the CR11 and the CR31 of a capacitor effectively) in, be loaded into one of CS " signal " data storage capacitor (for example, CS11 or CS31 then; Perhaps be merged into the CS11 and the CS31 of a capacitor effectively) in.Thus, will only come from whole " resetting " and " signal " analog pixel data load of one-row pixels in (and storing into) a plurality of ACU.During this method that the data storage capacitor in the ACU (CR and CS) is loaded, (for example to all pixels in the single row (for example, first row) of APS array, to pixel R11, G12, R13, G14 ...), operative norm (not sub sampled) correlated double sampling (CDS) simultaneously.Then, based on having activated which row selection wire, the ensuing operation of ACU (during non-CDSS pattern) to the single row of APS array (for example is, second row) all pixels in are (for example, to pixel G21, B22, G23, B24 ...) operative norm (not sub sampled) correlated double sampling (CDS).(for example, during standard CD S pattern) do not need switch SS during the non-CDSS pattern of ACU, and SR and Savg operate (for example, can stay open state).

During the CDSS of operation A CU (sub sampling) pattern, in case will come from four pixel R11, R31, R13, the simulation of R33 (" resetting " and " signal ") pixel data (for example is filled into a pair of ACU that is connected convertiblely, ACU-1 and ACU-3) in eight holding capacitors in, for to from four pixels (R11, R31, R13, R33) place receives, the electric charge of all four pixel datas of same type (" resetting " or " data ") carries out " on average " (merging and division) together, off switch SS sequentially, SR and Savg are (with switch S 1, S2, S3, S4 matches).

Yet, in the preferred embodiment of the CDSS of ACU operation (CDSS sub sampling pattern) method, close average switch S avg by also utilizing, (for example, even before being filled into the analog pixel data in all data storage capacitors), between the respective data storage capacitor among the ACU that connects (different lines, for example row 1 and row 3), the analog pixel data of each type (" resetting " or " signal ") are carried out " on average " (merge and divide) convertiblely.Thus, for example, when " signal " data that will come from pixel R11 are loaded into data storage capacitor CS11, data storage capacitor CR11 (with data storage capacitor CR13) is " mean value " of " resetting " data of " resetting " data of storage pixel R11 and pixel R13, rather than " resetting " value of storage pixel R11 only.

The sequential of Fig. 8 A there is shown the method for operation that is used for carrying out average switch in the process of loading four holding capacitors of each ACU---particularly average switch S avg---, and wherein high level is represented the switch of closing.Basically, (in all ACU) off switch S1, so that the analog pixel data that will come from by the predefined type (for example, " resetting ") of pixel in the determined row of capable selection wire (for example, the SEL1 of row 1) that activates are loaded in the data storage capacitor of corresponding group, CR11 for example, the CR12 (not shown), CR13, CR14 (not shown), and then open switch S 1, close average switch S avg then.(simultaneously,, in all ACU, opening or closing switch S 2, S3, S4, SS and SR) based on which is pre these specific analog pixel data of reception in four data holding capacitors among each ACU.

For example, in Fig. 8 A, as seen, locate off switch S1 when opening average switch S avg (data that are used for " resetting " are loaded into capacitor CR11 and CR13) in the time (1).Then, locate in the time (2), open switch S 1 (finishing after the pixel data that will " reset " is loaded among capacitor CR11 and the CR13), and close average switch S avg, merged and divide so that those have before just been stored into analog pixel data (electric charge) among capacitor CR11 and the CR13.Thus, each data storage capacitor of having selected (for example in by all ACU, CR11, CR12, CR13, CR14 ...) (for example receive the analog pixel data, data " reset ") afterwards, open switch S 1 (loading operation to the data holding capacitor has been finished in indication), and then be closed in average switch S avg between the ACU, so that the corresponding electric charge (" resetting " electric charge that for example, comes from pixel R11 and R13) to the same type that comes from the same colored pixels in the same pixel column averages (merge and divide) together.Thus, will be (for example from the same type received with two pixel-by-pixel basis of same color in the delegation, " reset ") analog pixel data average (merge and divide) to and be stored in each of each predetermined right data storage capacitor (for example, in CR11 and CR13).Repeat this colleague's averaging method (off switch S1 when opening switch S avg, for example in time (3), (5) and (7) are located; And when off switch Savg, open switch S 1 afterwards, for example in time (4), (6) and (8) locate), so that (for example load its excess-three to the data holding capacitor, CS11 and CS13, CR31 and CR33 afterwards, again after CS31 and CS33) in each, among the ACU that makes in convertible connection (for example, ACU-1 and ACU-3) in corresponding four pairs of data holding capacitors each all will comprise " on average " numerical value of " resetting " or " signal " data that two pixel places of same color receive from delegation.

Then, carry out the operation that the pixel data be used for the same type that receives from same row pixel (coming from the pixel on the different rows) place carries out same column average (merge and divide).By off switch SS (for example, locate in the time (9)) make and (for example be stored among each ACU a pair of CS data storage capacitor, CS11 among the ACU-1 and CS31) in the equilibrium of " signal " data charge, and off switch SR makes and (for example is stored among each ACU a pair of CR data storage capacitor, CR11 among the ACU-1 and CR31) in the equilibrium of " resetting " data charge, come simply the data that come from pixel in the different rows (same row) are carried out same column " on average " (merging and division).According to this final same column " on average " step, at the ACU that connects convertiblely (for example, ACU-1 and ACU-3) on four CS data storage capacitors (for example, CS11, CS13, CS31, CS33) each in has all kept identical average " signal " electric charge, and this average " signal " electric charge is represented from four pixel (for example, R11 of same color, R13, R31 and R33) the accurate mathematical mean of four (signal) electric charges receiving of place.And, similarly, according to this final (same column) " on average " step, at the ACU that connects convertiblely (for example, ACU-1 and ACU-3) on four CR data storage capacitors (for example, CR11, CR13, CR31, CR33) " on average " that each in has all the kept identical electric charge that " resets ", this average " resetting " electric charge is represented from four pixel (for example, R11 of same color, R13, R31 and R33) the accurate mathematical mean of four (resetting) electric charges receiving of place.

The following equation of the referential expression electric charge that the indicated time ((1) is to (9)) is located in sequential chart Fig. 8 A, more specifically explain in correlated double sub sampling pattern and (be used for pixel R11, R13, R31 and R33 carry out CDSS) in, eight data holding capacitors on the ACU of two convertible connections (for example, CR11, CR13, CR31, CR33; And CS11, CS13, CS31, performed data are loaded and " on average " operated in CS33).In these equatioies, Q is illustrated in the electric charge in the data storage capacitor shown in the subscript, and "=" symbolic representation supposes that electric charge equated when electric capacity (electric capacity of all data storage capacitors of same Type C S or CR) equated; The voltage sign of the form of subscripts, for example V _RESET11Expression and the identical implication of voltage " VR11 "; The symbol of the relevant electric capacity of the form of subscripts, for example C _CR11/CR31, the capacitor (in this example be CR11 and CR31) of expression shown in the subscript is though be interim but (so that forming additional merging capacitor) of being connected in parallel effectively:

Locate in the time (1), respectively " resetting " voltage (VR11 and VR13) of pixel R11 and R13 sampled, and it is loaded into respectively among data storage capacitor CR11 and the CR13:

R11 pixel: Q _CR11=Q _CR31=C _CR11/CR31(V _RESET11-V _Ref),

R13 pixel: Q _CR13=Q _CR33=C _CR13/CR33(V _RESET13-V _Ref)

Locate in the time (1), also to capacitor CS11, CS13, CS31 and CS33 charge, but will substitute these initial charges by suitable (picture signal) pixel data that receives from the intended pixel place after a while.

Locate in the time (2), between capacitor CR11 and CR13 (average switch S avg closes), " resetting " voltage (VR11 and VR13) to pixel R11 and R13 carries out " on average " (merging and division) respectively:

$Q_{\mathrm{CR}11}=Q_{\mathrm{CR}31}={\mathrm{<figure-callout\; id="13"\; label="Q\; CR"\; filenames="A20051007415800341.png"\; state="\{\{state\}\}">Q</figure-callout>}}_{\mathrm{CR}}=Q_{\mathrm{CR}33}=C_{\mathrm{CR}11/\mathrm{CR}31/\mathrm{<figure-callout\; id="13"\; label="CR"\; filenames="A20051007415800341.png"\; state="\{\{state\}\}">CR</figure-callout>}13/\mathrm{CR}33}(\frac{V_{\mathrm{RESET}11}+{\mathrm{<figure-callout\; id="13"\; label="V\; RESET"\; filenames="A20051007415800341.png"\; state="\{\{state\}\}">V</figure-callout>}}_{\mathrm{RESET}}}{2}-V_{\mathrm{ref}})$

Locate in the time (3), respectively " image " (signal) voltage (VS11 and VS13) of pixel R11 and R13 sampled, and it is loaded into respectively among data storage capacitor CS11 and the CS13:

R11 pixel: Q _CS11=Q _CS31=C _CS11/CS31(V _SIGNAL11-V _Ramp),

R13 pixel: Q _CS13=Q _CS33=C _CS13/CS33(V _SIGNAL13-V _Ramp)

Locate in the time (3), open switch S 3 and S4 and (be used for storing the capacitor CR11 of " resetting " voltage, CR13, CR31 and CR33 are in quick condition), and be used for storing the capacitor CR11 of " resetting " voltage, CR13, CR31 and CR33 are keeping their previous charge Q _CR11=Q _CR31=Q _CR13=Q _CR33(referring to top time (1)).

Locate in the time (4), between capacitor CS11 and CS13 (average switch S avg closes), image (signal) voltage (VS11 and VS13) to pixel R1 1 and R13 carries out " on average " (merging and division) respectively:

$Q_{\mathrm{CS}11}=Q_{\mathrm{CS}31}={\mathrm{<figure-callout\; id="13"\; label="Q\; CS"\; filenames="A20051007415800341.png"\; state="\{\{state\}\}">Q</figure-callout>}}_{\mathrm{CS}}=Q_{\mathrm{CS}33}=C_{\mathrm{CS}11/\mathrm{CS}31/\mathrm{<figure-callout\; id="13"\; label="CS"\; filenames="A20051007415800341.png"\; state="\{\{state\}\}">CS</figure-callout>}13/\mathrm{CS}33}(\frac{V_{\mathrm{SIGNAL}11}+{\mathrm{<figure-callout\; id="13"\; label="V\; SIGNAL"\; filenames="A20051007415800341.png"\; state="\{\{state\}\}">V</figure-callout>}}_{\mathrm{SIGNAL}}}{2}-V_{\mathrm{ramp}})$

Locate in the time (5), respectively " resetting " voltage (VR31 and VR33) of pixel R31 and R33 sampled, and it is loaded into respectively among data storage capacitor CR31 and the CR33:

R31 pixel: Q _CR31=C _CR31(V _RESFT31-V _Ref),

R33 pixel: Q _CR33=C _CR33(V _RESET33-V _Ref)

Locate in the time (5), because switch S S is (the capacitor CS11 and the CS13 that are used for storing " signal " voltage are in quick condition) of opening, and switch S R also is (the capacitor CR11 and the CR13 that are used for storing " resetting " voltage are in quick condition) of opening, so capacitor CS11, CS13, CR11 and CR13 keep their previous electric charges respectively.

Locate in the time (6), between capacitor CR31 and CR33 (average switch S avg closes), " resetting " voltage (VR3 1 and VR33) to pixel R31 and R33 carries out " on average " (merging and division) respectively:

$Q_{\mathrm{CR}31}=Q_{\mathrm{CR}33}=C_{\mathrm{CR}31/\mathrm{CR}33}(\frac{V_{\mathrm{RESET}31}+V_{\mathrm{RESET}33}}{2}-V_{\mathrm{ref}})$

Locate in the time (7), respectively image (signal) voltage (VS31 and VS33) of pixel R31 and R33 sampled, and it is loaded into respectively among data storage capacitor CS31 and the CS33:

R31 pixel: Q _CS31=C _CS31(V _SIGNAL31-V _Ramp),

R33 pixel: Q _CS33=C _CS33(V _SIGNAL33-V _Ramp)

Locate in the time (8), between capacitor CR31 and CR33 (average switch S avg closes), " image " (signal) voltage (VS31 and VS33) to pixel R31 and R33 carries out " on average " (merging and division) respectively:

$Q_{\mathrm{CS}31}=Q_{\mathrm{CS}33}=C_{\mathrm{CS}31/\mathrm{CS}33}(\frac{V_{\mathrm{SIGNAL}31}+V_{\mathrm{SIGNAL}33}}{2}-V_{\mathrm{ref}})$

Locate in the time (9), carry out (to four " resetting " electric charges and four " signal " electric charges) final average.(when off switch SR) will be stored in two (colleagues) among each ACU " the on average resetting " charge Q of voltage average out to that " on average resets " _RAVGAnd (when off switch SS) will be stored in " average signal " charge Q of two (colleague) " average signal " voltage average out among each ACU _SAVG:

Q _RAVG=Q _CR11=Q _CR31=Q _CR13=Q _CR33And

$Q_{\mathrm{RAVG}}=C_{\mathrm{CR}11/\mathrm{<figure-callout\; id="13"\; label="CR"\; filenames="A20051007415800341.png"\; state="\{\{state\}\}">CR</figure-callout>}13/\mathrm{<figure-callout\; id="13"\; label="CR"\; filenames="A20051007415800341.png"\; state="\{\{state\}\}">CR</figure-callout>}13/\mathrm{CR}33}(\frac{V_{\mathrm{RESET}11}+{\mathrm{<figure-callout\; id="13"\; label="V\; RESET"\; filenames="A20051007415800341.png"\; state="\{\{state\}\}">V</figure-callout>}}_{\mathrm{RESET}}+V_{\mathrm{RESET}31}+V_{\mathrm{RESET}33}}{4}-V_{\mathrm{ref}})$

Q _SAVG=Q _CS11=Q _CS31=Q _CS13=Q _CS33And

$Q_{\mathrm{SAVG}}=C_{\mathrm{CS}11/\mathrm{CS}31/\mathrm{<figure-callout\; id="13"\; label="CS"\; filenames="A20051007415800341.png"\; state="\{\{state\}\}">CS</figure-callout>}13/\mathrm{CS}33}(\frac{V_{\mathrm{SIGNAL}11}+{\mathrm{<figure-callout\; id="13"\; label="V\; SIGNAL"\; filenames="A20051007415800341.png"\; state="\{\{state\}\}">V</figure-callout>}}_{\mathrm{SIGNAL}}+V_{\mathrm{SIGNAL}31}+V_{\mathrm{SIGNAL}33}}{4}-V_{\mathrm{ref}})$

Thus, by off switch SS and SR, (for example from Q _SAVGAnd Q _RAVG) obtain final " on average " of four pixels of same color and sub sampling " voltage difference " (VS-VR).Final average after (for example, time (9) afterwards), be stored in the electric charge among the corresponding C S and CR data storage capacitor among the ACU-1 of row 1 and 3 and the ACU-3, storing identical " on average " electric charge that obtains from four pixels.Thus, can use and will export among VCD1 or the VCD3 any one, final " voltage difference " that read four CDSS sampled pixel of the same color of expression (VS-VR) (is used for analog-digital conversion).

Fig. 8 B is the employed ramp voltage waveform sum counter of analog-digital conversion latch control signal waveform is carried out in explanation concurrently to several several outputs that on average reach comparing unit (ACU) in the cmos image sensor (CIS) that comes from Fig. 3 a sequential chart.In final " on average " afterwards (for example, the time (9) shown in Fig. 8 A and the 8B afterwards), the analog domain subtracter of utilization in ACU (for example, subtracter among the ACU-1-1), " on average resetting " and " average signal " electric charge among the corresponding CS and CR data storage capacitor compares among ACU-1 and the ACU-3 to being stored in, so that obtain single (sub sampling) numerical value of four CDSS sampled pixel of APS array.To include the CS that is connected in series and the subtracter (for example, subtracter-1) of CR capacitor is connected between the input of Vramp and amplifier AMP1.Thus, represent that at the voltage of AMP1 input (VR) sum is because the polarity that is stored in the VR electric charge on the CR capacitor is connected to by (series connection) on the opposition polarity of polarity of the VS electric charge that is stored on the CS capacitor Vramp+VS+.Like this, the Vramp that is raise by clamp by (average) VS-VR at the voltage of AMP1 input.Counter enabling signal (CE) (referring to Fig. 3) can be timed to final average after (behind off switch SS and SR) begin counting.Thus, when (for example at the count initialized device, in the digital signal output circuit of Fig. 3) counting same in a flash the time, by with known (for example, predetermined) ratio, or at least with fixed ratio, voltage Vramp is inclined upwardly, when surpassing predetermined threshold voltage levels, the input (coming from the output of subtracter) of AMP1 (for example, by latching this counting, the value of VS-VR can be converted to the digital value of quantification from the analogue value in the time of Vref).The value of VS-VR is big more, and it is short more to make the input of AMP1 reach time (counting) of threshold voltage (Verf).

When the input of AMP1 reaches threshold voltage (Verf), the signal VCD of ACU (for example, the VCD1 of ACU-1) will change high value into from low value.Thus, can VCD signal (for example, VCD1, VCD2, the VCD3 of each ACU will be come from ...) as the counting latch control signal, export to latch circuit (referring to Fig. 9).

Fig. 9 is employed counter of analog-digital conversion and latch cicuit are carried out in explanation concurrently to several several outputs that on average reach comparing unit (ACU) in the cmos image sensor (CIS) that comes from Fig. 3 a structure chart.When activate counter enabling signal (CE) (for example, in the CDSS pattern, four pixels are carried out " final is average " by the ACU operation after; Or after during standard CD S pattern, only being loaded into the data of a pixel among each ACU), calculator has been exported digital counting and has been begun.Latch cicuit comprises the Puzzle lock storage (each ACU has) that several are parallel, is used for latching the counting of being exported to all latchs by counter by the corresponding represented moment of VCD signal that corresponding ACU exported.Can use the VCD signal of exporting by each ACU to be controlled to be (in latch cicuit) corresponding Puzzle lock storage that each ACU provides, with convenient VCD signal (for example, the VCD1 of ACU-1) when low value changes high value into, at this (counting) constantly, be this count value of corresponding counts latch stores that ACU provided.Therefore, when counter arrives the end of its counting, analog-digital conversion has been carried out in all (independently) outputs that come from subtracter among a plurality of ACU concurrently.The content of a plurality of latchs in the latch cicuit (for each ACU memory counter numerical value) can be exported to digital signal processor (DSP), so that (sub sampling or the not sub sampled) pixel data that comes from ACU is carried out further refining or storage or transmission as digital pixel data.

Figure 10 is that explanation is positioned at several average structure charts that reach the another kind of switch interconnection exemplary embodiment between the comparing unit that are used to carry out correlated double sub sampling (CDSS), is used for the N in the APS array of Fig. 3 cmos image sensor (CIS) ²Individual pixel (for example, with greater than 4 sub sampling rate) averages/and sub sampling handles.Similar among average and comparison circuit (referring to Fig. 3) among Figure 10 and Fig. 6, except the switches interconnection between a plurality of average and comparing units (NACU) among Figure 10 is more flexible, wherein can connect simultaneously on the different lines more than (for example, N) ACU of two.Many situations that ACU is linked to each other in Fig. 6, the property of interconnections support of this enhancing is to from average " merge and distribute " more than the electric charge of the pixels of two row (for example, reset and signal).Thus, by N NACU (rather than 2 ACU) linked together, each NACU all includes N CR data storage capacitor and N CS data storage capacitor (rather than 2 CR data storage capacitors and 2 CS data storage capacitors), can carry out downward sub sampling to the Baeyer graphical pixel zone in 2N * 2N scope, up to the data of the three kinds of colors (RGB) that obtain " on average " pixel of expression.Thus, interconnection system support among Figure 10 is carried out correlated double sub sampling (CDSS) to the 2N * 2N pixel region of cmos image sensor among Fig. 3 (CIS), wherein N can be in the scope of (being 2 under the situation of Fig. 6 and 7 circuit for example) from 1 (not sub sampled) to any integer.

Figure 11 is the circuit diagram that describes the average and comparing unit (NACU) that strengthens according to another embodiment of the present invention in detail, and this NACU is used for the nearly N to same color in the 2N * 2N pixel region in the APS array of Fig. 3 cmos image sensor (CIS) ²Individual pixel is carried out CDSS, and average/sub sampling is handled.ACU shown in NACU shown in Figure 11 and Fig. 7 is similar, except analog to digital subtracter among the NACU of Figure 11 (for example comprises 2N analog pixel data storage capacitor, 2N=6,8,10), rather than only have 4 analog pixel data storage capacitors (and additional switch, for example, SSN).Additional data storage capacitor (and controlling their loading and average extra switch) is supported the N to the same color in N different lines in the 2N * 2N pixel region that is arranged in the APS array and N the different rows ²Individual pixel is carried out the CDSS pattern average/sub sampling.Utilization comes from (resetting) voltage (VR) of the pixel of the row that link to each other with NACU, from CRN to CR1, and CR (resetting) data storage capacitor in the subtracter (for example, N subtracter-1) of charging (loading) NACU.Utilization comes from (picture signal) voltage (VS) of the same pixel of the row that link to each other with NACU, from CSN to CS1, and CS (picture signal) data storage capacitor in the subtracter (for example, N subtracter-1) of charging (loading) NACU.

Carry out because each pixel column all needs a NACU CDSS average/sub sampling, so, for example, with in the mode shown in Figure 10, the NACU among Figure 11 will by with at least N-1 similarly other NACU interconnect convertiblely.In fact, because the NACU of Figure 11 also can be to being arranged in 1 in its row, 2,3 or still less integer L pixel (be less than N pixel, for example, L=1,2,3) carry out CDSS average/sub sampling, can every other (for example, the odd number) NACU in CIS be interconnected convertiblely with mode shown in Figure 10.Yet, can control each " on average " switch S avg independently or dynamically, so that forbid every other (for example, odd number) between the NACU in adjacent second of the NACU in first of NACU (containing L odd number NACU) and every other (for example, odd number) ACU (containing other L odd number ACU) " on average " connection appears.By that way, each piece among the NACU of L or N convertible interconnection is being carried out CDSS pattern operating period, only should (pixel in the pixel region of or 2L * 2L) averages together to coming from identical 2N * 2N.

By control switch Savg dynamically, S1, S2, S3, S4 and (SS1, SS2 ... SSN) reach (SR1, SR2 ... SRN), the NACU in the present embodiment can be used for the quantity L that the Dynamic Selection of the same color in square to being arranged in (or non-square) pixel region goes out ²(from l ²To N ²) individual pixel execution sub sampling.

As mentioned above, at least one embodiment among the present invention provides a kind of method and device that is used to carry out correlated double sub sampling (CDSS), comprise the step of " on average " (in analog domain) from " resetting " numerical value and average (in analog domain) " signal " numerical value of the reception of plurality of pixels place, be from " on average " signal numerical value, to deduct the reset step of numerical value of (in analog domain) " on average " afterwards, thereby produce CDSS sampled analog data numerical value, the accurate mathematical mean value of the pixel of the common CDS sampling of four processes of the same color of this numeric representation.Thus, at least one embodiment provides a kind of performance of plurality of pixels in CMOS active pixel sensor (APS) array directly, accurately being carried out sub sampling in analog domain among the present invention, also removes stationary figure noise (FPN) simultaneously.

By above description to exemplary embodiment of the present; be appreciated that; the detail that the present invention who is defined by the appended claims is not subjected to be set forth in above-mentioned exemplary embodiment limits; thereby under the situation as claimed the spirit and scope of the present invention, its any obvious variation all is possible.In claims, L and N represent integer, and wherein the scope of L is from 1 to N, comprises N; And " N " represents digital N; 2N represents the twice of N; The twice of " 2N " expression N.

Claims (49)

1, a kind of imageing sensor, comprise: a plurality of pixels of arranging with row and column, each row pixel links to each other with two image signal data capacitors that are used to store two reseting data capacitors of two reset charge and are used to store two image charges at least at least at least at least convertiblely.

2, the imageing sensor described in the claim 1 further comprises: average circuit is used for utilizing at least two reset charge to carry out first average operation, so that produce average reset charge.

3, the imageing sensor described in the claim 1, wherein, average circuit also is used for utilizing at least two image charges to carry out second average operation, so that produce the average image electric charge.

4, the imageing sensor described in the claim 3 wherein, is carried out first and second average operations in analog domain.

5, the imageing sensor described in the claim 3 further comprises: analog subtracter is used for deducting average reset charge from average signal charge, so that produce differential voltage.

6, the imageing sensor described in the claim 5 further comprises: analogue-to-digital converters (ADC) are used for differential voltage is carried out the conversion of analog to digital.

7, the imageing sensor described in the claim 6, wherein, average circuit and ADC are by same bias source common bias.

8, the imageing sensor described in the claim 7, wherein, bias source is in the first voltage level place during first and second average operations, and is in the second voltage level place in ADC operating period, and first voltage level is different with second voltage level.

9, the imageing sensor described in the claim 2, wherein, first average operation comprises the first step that the numerical value that resets that is arranged in mutually the pixel among the colleague is averaged, and second step that the numerical value that resets that is arranged in the pixel in the same column is averaged.

10, the imageing sensor described in the claim 2 wherein, was carried out the average first step before carrying out the second average step.

11, the imageing sensor described in the claim 2, wherein, average circuit comprises and is arranged at least two switches between the reseting data capacitor.

12, the imageing sensor described in the claim 3, wherein, average circuit further comprises and is arranged at least two switches between the view data capacitor.

13, the imageing sensor described in the claim 1, wherein, imageing sensor is the CMOS type.

14, a kind of pixel in CMOS active pixel sensor (APS) array is carried out the method for sub sampling, this method comprises: at first group of N ²In the individual capacitor, storage L from the APS array ²The L that individual pixel place receives ²Individual analog pixel reseting data electric charge.

15, the method described in the claim 14 further comprises: at second group of N ²In the individual capacitor, storage L from the APS array ²The L that individual pixel place receives ²Individual analog pixel image signal data electric charge.

16, the method described in the claim 14 further comprises: to being stored in first group of N ²L in the individual capacitor ²Individual analog pixel reseting data electric charge is carried out first average operation.

17, the method described in the claim 16 wherein, is carried out first average operation in analog domain.

18, the method described in the claim 16, wherein, first average operation comprises all L ²Individual analog pixel reseting data electric charge merges.

19, the method described in the claim 16, wherein, with all L ²Individual analog pixel reseting data electric charge merges at least two capacitors that comprise in first group of N2 capacitor and is connected in parallel with each other.

20, the method described in the claim 18 further comprises: to being stored in second group of N ²L in the individual capacitor ²Individual analog pixel image signal data electric charge is carried out second average operation.

21, the method described in the claim 19, wherein, second average operation comprises all L ²Individual analog pixel image signal data electric charge merges, and further comprises at this group N ²At least two capacitors in the individual capacitor are connected in parallel with each other.

22, the method described in the claim 21 further comprises: the subtraction in analog domain, wherein pass through first group of N ²At least one capacitor in the individual capacitor and second group of N ²At least one capacitors in series in the individual capacitor connects, and obtains differential voltage.

23, the method described in the claim 22 further comprises: to coming from the differential voltage of subtraction gained, carry out the conversion (ADC) of analog to digital.

24, the method described in the claim 23 wherein, by the circuit of being setovered by single bias source, is carried out average operation and ADC to differential voltage.

25, the method described in the claim 23, wherein, single bias source is in the low voltage level place during average operation, and is in the high-voltage level place during ADC.

26, the method described in the claim 21, wherein, L equals N, and N equals four.

27. the method described in the claim 26, wherein, four line of pixels are listed in two row and two to be listed, and first average operation comprises: obtain to come from first colleague's mean value of two reset charge of the last first pair of pixel of first row, obtain to come from second colleague's mean value of two reset charge of the last second pair of pixel of second row; And the mean value of afterwards first colleague's mean value and second being gone together averages.

28, a kind of imageing sensor comprises:

The array of the pixel of arranging with a plurality of row and a plurality of row, each pixel in each row pixel operationally links to each other with averaging unit, wherein each averaging unit comprises and is used to store first and second holding capacitors that come from first pixel and come from the analog reset data of second pixel, and is used to store third and fourth holding capacitor that comes from first pixel and come from the analog picture signal data of second pixel.

29, the imageing sensor described in the claim 28, wherein, will come from first pixel is electric charge with the analog reset storage that comes from second pixel.

30, the imageing sensor described in the claim 28 further comprises: the first average switch, be used to carry out first average operation, and this first average operation comprises that the analog reset data to being stored at least two averaging units average.

31, the imageing sensor described in the claim 30, wherein, the first average switch also is used to carry out second average operation, and this second average operation comprises that the analog picture signal to being stored at least two averaging units averages.

32, the imageing sensor described in the claim 31 wherein, is carried out first and second average operations in analog domain.

33, the imageing sensor described in the claim 28, wherein, each averaging unit further comprises: N holding capacitor is used to store the analog picture signal data that come from N pixel.

34, the imageing sensor described in the claim 28, wherein, each averaging unit further comprises: 2N holding capacitor is used to store the analog reset data that come from N pixel.

35, the imageing sensor described in the claim 28 further comprises: the analogue-to-digital converters of each row (ADC) are used for a plurality of outputs that come from averaging unit are carried out the conversion of analog to digital.

36, the imageing sensor described in the claim 35, wherein, each analogue-to-digital converters (ADC) are applicable to carry out the conversion of analog to digital concurrently from a plurality of outputs of averaging unit.

37, the imageing sensor described in the claim 28, wherein, averaging unit and ADC are by same bias voltage common bias.

38, the imageing sensor described in the claim 28, wherein, bias source is in the first voltage level place during average operation, and is in the second voltage level place in ADC operating period, and first voltage level is different with second voltage level.

39, the imageing sensor described in the claim 31, wherein, first average operation comprises that the analog reset data to being arranged in the pixel in going together mutually average.

40, the imageing sensor described in the claim 32, wherein, second average operation comprises that the analog picture signal data to being arranged in the pixel in going together mutually average.

41, the imageing sensor described in the claim 28, wherein, each averaging unit further comprises and is arranged on resetting between first and second holding capacitors-average switch, is used for the analog reset data in the pixel of same column are averaged.

42, the imageing sensor described in the claim 28, wherein, each averaging unit further comprises the picture signal that is arranged between third and fourth holding capacitor-average switch, is used for the analog picture signal data in the pixel of same column are averaged.

43, the imageing sensor described in the claim 28, wherein, imageing sensor is the CMOS type.

44, the imageing sensor described in the claim 28 further comprises: digital signal processor.

45, a kind of array to the pixel of arranging with a plurality of row and a plurality of row carries out the method for sub sampling, and each pixel all is applicable to output resetting voltage and image signal voltage, and this method may further comprise the steps:

In first group of holding capacitor, a plurality of resetting voltages that storage is exported by a plurality of pixel;

In second group of holding capacitor, a plurality of image signal voltages that storage is exported by a plurality of pixel;

The a plurality of resetting voltages that are stored in first group of holding capacitor are merged; And

The a plurality of image signal voltages that are stored in second group of holding capacitor are merged.

46, the method described in the claim 45 further comprises: will be connected in series at least one holding capacitor in first group of holding capacitor and at least one holding capacitor in second group of holding capacitor.

47, the method described in the claim 45 further comprises: the voltage by the holding capacitor that is connected in series in first and second groups of holding capacitors is detected.

48, the method described in the claim 45 further comprises: the voltage by the holding capacitor that is connected in series in first and second groups of holding capacitors is carried out digital quantization.

49, a kind of to the N row that are arranged in CMOS active pixel sensor (APS) array and N the N in capable ²Individual pixel is carried out the method for sub sampling, and each pixel is applicable to output resetting voltage and image signal voltage, and this method may further comprise the steps:

In first capacitor, the resetting voltage of first pixel is stored as first electric charge;

In second capacitor, the resetting voltage of second pixel is stored as second electric charge; With

First and second electric charges are merged into average reset charge.

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