TW200533191A - Method and circuit for performing correlated double sub-sampling (CDSS) of pixels in an active pixel sensor (APS) array - Google Patents

Abstract

A method and circuit for performing Correlated Double Sub-Sampling (CDSS) of pixels in an active pixel sensor (APS) array. Each pixel outputs a reset voltage and then an image signal voltage. The method and the apparatus subsamples a plurality (L2) of pixels by: storing L2 analog reset charges output from the L2 pixels into a first set of (N2) storage capacitors, and combining the (L2) reset charges; storing L2 analog image signal charges output from the L2 pixels into a second set of (N2) storage capacitors, and combining the (L2) image charges; and then obtaining a differential voltage (VS-VR) by subtracting (in the analog-domain) the voltage (VR) represented by the combined (L2) reset charges from the voltage (VS) represented by the combined (L2) image signal charges. When L equals one, the circuit performs conventional Correlated Double Sampling CDS upon the one pixel. When L is greater than one, the circuit performs Correlated Double Sub-Sampling (CDSS) of the L2 pixels. Dynamic selection of a subsampling ratio B (where B equals 1:L2 and L ranges from 1 up to N) is supported. Averaging units used to combine the reset and image signal charges, and analog-to-digital converters (ADCs) for converting the differential voltage to a digital pixel data, may be commonly biased by the same variable bias voltage.

Description

200533191 16323pif.doc IX. Description of the invention: [Technical field to which the invention belongs] The present invention relates to an image sensor (IMAGE SENSOR), and in particular to a device capable of performing an active daylight sensor (APS) array. Method and circuit for correlated double subsampling (SUB-SAMPLING) and then correlated double sampling (CORRELATED DOUBLE SAMPLING) (CDS) of dynamically selected number of daylight in the NxM daylight region (PIXEL REGION). [Previous Technology] Since the mid-1980s, CHARGE COUPLED DEVICE (CCD) has become the most common image pickup device (image sensor). With the support of SEMICONDUCTOR INDUSTRY, the capabilities of the charge-dissipating device C C D have been rapidly improved, resulting in a modern compact camera with high performance (CAMERA). However, the charge-coupled device CCD is actually the main image capture device and the core of digital cameras. The inconvenience of the charge-coupled device CCD sensor is that it consumes considerable energy and cannot continuously operate at high speeds. In view of this situation, a large complementary metal-oxide-semiconductor image sensor (CIS) (CIS) capable of providing high resolution of several million MEGAPIXELs has been developed. In addition to 旎 two-density configuration with a very large amount of daylight and high-speed scanning data, this complementary metal-oxide-semiconductor image sensor (CIS) consumes

CCD a), which is more significant than the standard charge-coupled device cCD used today. Note the advantages of 200533191 16323pif.doc. Another benefit is that the complementary metal-oxide-semiconductor image sensor (C ^) reduces manufacturing costs: even a relatively large-sized complementary metal-oxide-semiconductor image sensor (CIS) can be provided at a relatively low cost. Complementary metal-oxide-semiconductor image sensors (CIS) can be manufactured using the same process as the metal-oxide-semiconductor field-effect transistor (MOSFET) or complementary metal-oxide-semiconductor transistor (CM0S TRANSISTOR), or manufactured on the same On the chip, the signal processing circuit (SIGNAL PROCESSING CIRCUIT) can be formed on the same chip, thereby reducing internal wiring. In addition, the complementary metal-oxide-semiconductor image sensor (CIS) can be easily reduced in size because it can be installed in the peripheral CIRCUIT ^ B, ^ (〇N.CHIP; therefore, the complementary metal-oxide-semiconductor image sensor) (CIS)

It is possible to 'become the main image sensing device (〗 MAGE SENSING DEVICE) (alternative to the charge-coupled device CCD solid-state (SOLID-STATE) image capture device) in the widespread application of future digital imaging systems. expected. There is a big difference in the image data scanning method between the charge coupled device CCD and the complementary metal oxide semiconductor CMOS sensor Lu. For example, with a resolution of 3 million daylight, the CCD of the charge-coupled device scans the three million (ANALOG) charges continuously in the same way that the same person transfers the bucket one by one; and usually only scans Mumiao will not produce amplification until the last pixel element (converts the charge into an electronic signal). On the other hand, to provide a main animation element that contains an amplifier (AMPLIFIER) for each day element (here, an amplifier refers to a transistor or other converter that converts charge into an electronic signal). (APS) array (refer to the active daylight sensor (eight? §) array of FIG. 1), such as a complementary metal-oxide-semiconductor CMOS sensor. Therefore, it can perform signal amplification on a day-to-day basis, reduce conversion operations, and thus perform faster data scanning with minimal energy consumption. The related double fetch (CDS, charge-to-voltage (CHARGE-TO-VOLTAGE) converter of complementary metal-oxide semiconductor image sensor), (CONVERTER) is basically a single (or multi-stage (MULTISTAGE)) voltage follower

_ (VOLTAGE FOLLOWER) (AMPLIFYING TRANSISTOR) capacitor (CAPACITOR), and this capacitor voltage preset (PRESET) ("Reset, (" RESET ,,)) into a "known, , SWITCH of the initial level (INITTIAL LEVEL). In the simplest video system (VIDEO SYSTEM), this switch is closed at the beginning of reading each pixel, which will reset the capacitor voltage and output level. After transmitting this PIXEL CHARGE PACKET to the capacitor, the voltage of the capacitor changes and its output signal represents the pixel value. Components such as switches •, due to their limited residual inductance (RESIDUAL CONDUCTIVITY), can pre-charge this capacitor to an unknown value, which will add an error to the output signal. Fortunately, there is a way to compensate for this precharging uncertainty: correlated double sampling (CDS). In this method, the output signal of each day element is sampled twice: immediately after the capacitor is pre-charged and after the pixel charge packet is added. The difference between these two values will remove the noise component (charge) caused by the switching. 9 200533191 16323pif.doc Correlated Double Sampling, or CDS, is a method used to improve the signal-to-noise ratio (SIGNAL TO NOISE RATTI0) (S / N) of an integrated image sensor (INTEGRATING IMAGE SENSOR). By subtracting the "dark" ("DARK"), or "reference" ("REFERENCE"), or "reset" ("RESET") from the actual light-induced signal Output (charge) level, which can effectively output static fixed pattern noise (STATN FIXED PATTERN NOISE) (FPN) and several types of timing noise (TEMPORAL NOISE) self-sensor (APS array • array) Figure 2 shows a block diagram of a conventional correlated double sampling (CDS) circuit (eg, formed in the block of the correlated double sampling (CDS) and active day sensor (APS) of Figure 1) block, which is modified to about The average of pixel values sampled by four double active samples (CDS) of the same color pixels in the 4 A4 array (APS) array of four stored active day sensors. The two rows of four pixels that are sampled and then averaged together are selected by a row of drivers (shown in Figure 1). # In an optical sensor (OPTICAL SENSOR) (active day sensor)

(APS) array, the photocharge (ph〇TOCHARGE) is usually collected by a photodiode (PD), and can be stored in the capacitor (CAPACITANCE) located in each element (PIXEL ELEMENT) C on. Read the photo charge from the capacitor as the voltage of the capacitor (V = Q / C). Use the Correlated Double Sampling (CDS) program to compare the signal voltage (SIGNAL VOLT AGE), Vs, Qs / C, and when all the charge of the capacitor C has been led to a fixed potential (FIXED POTENTIAL) (as mentioned in the above 10 2005 Unique 1) "Dark", "Empty" ("empty"), "Reference", or "Reset" level voltage (LEVEL VOLTAGE) Vr = Qr / C. The final output of each pixel can be obtained Voltage V = Vs-Vr (Qs-Qr) / C. Can be used on the same chip as the main animation element sensor (APS) array circuit "on the chip, (" 〇N CHIP ") implementation Correlated Double Sampling (CDS) procedures, or the "Off-CHIP CDS" ("OFF-CHIP CDS") method, is used to perform Correlated Double Sampling (CDS) procedures. In the Correlated Double Sampling (CDS) procedure, each column of the day element to be sampled by the correlated double sampling usually requires a memory (such as a CHARGE-STORAGE CAPACITOR) and a subtractor (SUBTRACTOR). In the circuit of FIG. 2, four capacitors (50a, 51a, 50b, 5lb) are provided to store four values from four pixels, and switches (SWITCH) 2, 21a, and 21b are provided to perform the four stored charges " "IMAGE AVERAGING PROCESSING". Each capacitor 50a, 51a, 50b, 51b is used to store the charge (QS-Qr), which is used to output an analog image data (ANALOG IMAGE DATA) which represents a pixel. The final output voltage (FINAL OUTPUT VOLTAGE) V (V2 Vs-Vr). Switches 21a and 21b are each used to combine the two stored daylight values (obtained continuously from daylight elements in different columns of the same row) and Divide them together (average). For example: When switch 21a is closed and each capacitor 50a and 51a of the same size stores the sampled day value (from column 1), the charges on the two capacitors will be combined, etc. And are equally distributed (divided by division) between the two capacitors 50a and 51a. Therefore, the sampled pixel values from different rows in the same column will therefore be averaged. Switch 2 is used 20053, ^ 31 (50a, 51a, 50b, and 51b) Equal, and will be equally divided (divided by) into the four capacitors. In this way, the sample will be sampled from two different columns (for example: column "i," and column "3") (Or the average of the day value of the samples) combined and divided together by division; average ^ For example: when switches 2, 21a and 21b are closed, and when the same size of 50 &, 51a, 50b, and 51b, etc. Capacitors store the averaged values of the sampled pixels (days in column "1" and column "3") in all four capacitors

The diurnal values of the four diurnal elements (of the same color) in two different rows and two different columns are thus averaged. If the switches 2a and 21b are both open when the switch 2 is closed, the circuit of FIG. 2 will only store two diurnal values (from the same row and two different columns) on the capacitors 50a and 50b on average. Final level of day-to-day values sampled for each correlated double sampling (CDS)

Both, then pass the amplifier (AMPLIFIER) 54 (such as 54a and 54b) 'then through the column selection switch (COLUMN SELECTION SWITCH) 20 (such as · transistor)' and then through the common output line (COMMON OUTPUT LINE) 30, An analog to digital (ANALOG-TO-DIGITAL) (ADC) converter (not shown).

Figure 2 includes two identical circuits ("a" and "b"), each of which is connected to each other and is used to select one of the two columns (for example: column "1" or column "3") through individual vertical selection VERTICAL SELECTION LINE ("CL1" or "CL3") is sampled through a pixel of a sample-and-hold switch (SAMPLE-HOLDING SWITCH) 42 for correlated double sampling (CDS). Sample-and-hold capacitor for holding or resetting the signal charge (SIGNAL CHARGE) of the pixel output in the active daylight sensor (APS) array 12 20053¾¾ 16323pif.doc (SAMPLE-HOLDING CAPACITANCE) 44, sample-and-hold switch 42 interrupts the connection with the vertical selection line. A reference voltage source (REFERENCE VOLTAGE SOURCE) 46 (for example, 4 and 46b) is connected in series with the sample-and-hold capacitor 44. The analog (charge) subtractor consists of a sample-and-hold capacitor 44 (44a or 44b), an amplifier (eg, non-inverting buffer (NON_INVERTING BUFFER)) 48 (48a or 48b), and a correlated double sampling (CDS) capacitor 50 (50a or 50b). An output point of the subtractor (one end of a correlated double sampling (CDS) capacitor 50) is connected to an input terminal of an output amplifier (OUTPUT AMPLIFIER) 54. Because the voltage output of the non-inverting buffer (amplifier) 48, which is the same as the amount of charge stored in the sample and hold capacitor 44, can induce an equal voltage (to be stored in the relevant double sampling (CDS) capacitor 50) And equal charge), so the charge held on the sample-and-hold capacitor 44 can be copied (copied) to the correlated double-sampling (CDS) capacitor 50 through the closed circuit of the clamp switch 52. The correlated double sampling (CDS) valley 50 can be changed to a floating state (FL0ATING STATE) (which stores the voltage / charge copied from the sample and hold capacitor 44) by opening the latch switch 52. In this way, the first charge (FIRSt CHargE) (eg, "signal" charge Qs) from a given daylight element that is first received and held by the sample-holding valley 44 can be copied to and stored in the relevant double sample (CDS) capacitor 50, so a second charge (for example, "reset" charge Qr) from the same day element can be received and held by the sample-and-hold capacitor 44 later. 13 200533191 16323pif.doc In this way, 'In operation, the signal voltage VS (from a pixel, via a selection line, such as CL1) is first supplied to the input of the subtractor (sampling and holding capacitor 44), Since the clamp switch 52 is closed (in the ON state), the signal voltage VS from the day element charges the sample-and-hold capacitor 44 and also the related double-sampling (CDS) capacitor 50. Next, after the position switch 52 is opened (switched to OFF), and the reset potential (voltage) VR (from the same day element, via a vertical selection line, such as cL ^, so that the reset voltage VR is input to the analog The input of the subtractor is held by the sample-and-hold capacitor 44. As a result, the output of the analog subtractor (located at the end of the correlated double-sampling (CDS) capacitor 50) produces a voltage between the signal voltage VS and the reset voltage VR. VS-VR. So it is possible to get analog pixel data (ANALOG PIXEL DATA) sampled by one pixel correlated double sampling (CDS), which overlaps the signal voltage VS and reset voltage VR Noise components on the fixed pattern will be removed. The analog diurnal data sampled by this correlated double sampling (CDS) can be output by the common output line 30 through the amplifier 54 and then the switch 20 when the switch 20 is closed. Each capacitor 50a, 51a, 50b, 51b is used to store a charge (for example, Qs or Qr), and is used to output the final output voltage v (V = Vs of ANALOG IMAGE DATA) representing a pixel. -Vr). I said " The "Variance Signal (VS-VR)" is held by the "Correlated Double Sampling (CDS) Capacitor 50" and therefore each Correlated Double Sampling (CDS) capacitor (50a, 51a, 50b, 51b) stores four correlated double samples ( CDS) The four complete differential signals (VS-VR) of the day element sampled. 200533191 16323pif.doc However, when the charge held in the sample-hold capacitor 44 is changed (and thus changed by the non-inverting buffer (amplifier) ) At 48)), it may be difficult to maintain a charge that accurately represents the complete differential signal (VS-VR) in a correlated double sampling (CDS) capacitor 50 alone. In fact, it is not so relevant The double sampling (CDS) capacitor 50 (for example: 50a, 51a ', 50b, 51b) stores a complete differential signal (VS々R) related to Qs-Qr. It is better to say that the correlated double sampling (CDS) capacitor 50 may only store one The voltage associated with a charge from a given day element (eg: the first charge received from this day element; for example ... either the "reset" charge (Qr) or the "signal," the charge (qs) One of them). In this way, even if the two sample-and-hold capacitors 44 (44a 4 servants) one of them receives and maintains the "reset of this four pixels, before the charge Qr, the image of each of these four days," the signal, the charge Qs (not the "reset, the charge Qr) First stored in one of the correlated double sampling (CDS) capacitors 50a, 51a, 50b, 51b, and then four (floating signal, charge Qs (stored in the correlated double sampling (CDS) capacitors 50a, 5la , 50b, 51b) among the correlation # double sampling (CDS) capacitors 50a, 51a, 50b, 51b are combined and divided by division, as seen by the amplifier 54 (eg: 54a or, this A final output (one of the two subtractors) will only receive the reset charge (stored in the two sample-and-hold capacitors) received from one of the four diurnal elements. So the final output of the subtractor (As in the amplifier 54 =) 'Will not be mathematically averaged by the day-to-day values (VS_VR) sampled by the four double sampling (CDS) of the circuit output of FIG. 2 in sequence. In such an example, there are two "resets" received, and the charge / voltage will be "averaged" along with the four "signal" charges / voltages stored in 2005. The pattern == two rather than from the assumption is For "=

Uncovered = bit ^ machine towel by-pixel array touch capture image to perform secondary image capture. Some occasions where it would be beneficial to reduce the resolution will be very beneficial. It is possible to enable the display on a display with a reduced resolution. Image display. = Field (after ship line position conversion) To perform sub-sampling it often requires Otani 1 memory and a lot of processing time, which will consume additional power. With the analog-digital "average," operation of Figure 2, the circuit of Figure 2 used to perform day-time subsampling, and other known circuits closely related to @ 2, have only been modified to be in the Bell diagram type (BAYER_pATTERN In the array, sub-sampling of pixels sampled by correlated double sampling (CDS) is performed by "averaging" four pixels of each color in a 4x4 celestial region together. SUMMARY OF THE INVENTION An object of the present invention is to provide an image sensor including a plurality of day pixels arranged in rows and columns, and each column of pixels can be switched with at least two reset data capacitors (RESET DATA CAPACITOR). ) For storing at least two reset charges; and including at least two image data capacitors (IMAGE DATA CAPACITOR) for storing at least two image charges (IMAGE CHARGE). This image sensor implements a main animation sensor. (APS) The sub-sampling method of N2 day elements arranged in N columns 16 200533191 16323pif.doc and N rows, every _ book element is changed to: output a reset voltage (RESET VOLTAGE) and-image signal voltage (IMAGE SIGNAL VOLTAGE), this method includes the following steps: storing the reset voltage of the first pixel as the first charge in the first capacitor, storing the reset voltage of the second pixel as the second capacitor in the second capacitor, And the first and second charges are merged into an average reset voltage (AVERAGED RESET CHARGE). The method of sub-sampling pixels includes resetting the data charge of the L2 analog pixels received from the L2 pixels in the active day sensor P (APS), and storing them in the first group of ^ capacitors. The charge of the L2 analog pixel image data of the L2 dioxin in the animated pixel sensor (Aps) is stored in the second group of capacitors. L can range from 1 to N. The first averaging job is performed on the l2 analogue daylight reset data charge stored in the first set of N2 capacitors. Similarly, the second average operation on the data charge of the L2 analog day signal data stored in the second group of N2 capacitors will also be performed. Image sensor includes an average and ratio connected to each column of each day element • AVERAGING AND COMPARING UNIT (ACU) 〇 These average and comparison units (ACU) work together to perform averaging in the analog domain And subtract the average reset charge (from the majority of pixels) from the average signal charge (from the same majority of pixels) to generate a differential voltage (DIFFERENTIAL VOLTAGE). The image sensor will also include an analog to digital converter (ADC) to perform the analog to digital conversion of the differential voltage. 20053 take

Each pixel is modified to output the same (at 1: L2 sampling ratio) reset voltage and a video signal voltage. This method includes the following steps: reset the data charge from the majority (L2) analog output from the majority Merging (for example: merging the L2 button charges stored in the first storage capacitor) and merging the electric charges of the majority (L2) analog image signal data output from the plurality (L) pixels (for example: merging the data stored in the second storage capacitor) _The L2 image signal charge in the storage capacitor is combined). The operation of correlated double sampling (CDS) (such as the conventional technique) is to use the merge (average) of the data charges of each reset and the merge (average) of the data charges of each image signal (instead of the reset and image from the diurnal prime) Charge) to obtain the precise mathematical "average" of the average L2 celestial element representing the same color. The difference voltage (VS-VR) is done by observing a color in a 4x4 pixel area representing a Bell pattern array. The daily prime value (the charge amount is set as a mathematical "average") for the four-correlation double sampling to verify the accuracy of the "average, (and sub-sampling) function performed by the embodiment of the present invention, and the following relationship (equation) To represent:

And use the addition (ADDITION) of the distribution (DISTRIBUTIVE) and the addition of the inverse element (ADDITIVE INVERSE) characteristics to represent: 1 1

Following this mathematical relationship, the four correlations to be averaged (subsampled) together 18 200533191 16323pif.doc

The exact "average, value" of the pixel values sampled by double sampling can be obtained by combining the combination of four "weights = Qru + Qri3 + Qr3i + D of the charge element from the four days and the charge combination Qsi 1 + Qsi3 + + Qs33 (Analog) '-again. By dividing the combined electric charges (for example ...) equally among the four capacitors of the phase ^ capacitance σ column such as ... C), the four "signals," the group two of charges divided by four (for example, "in" Subtracted by subtraction, this combined "reset, before the charge." Similarly, by distributing the combined charge (for example: equally) between the four capacitors of the phase capacitor (for example: C), and Divide the four "reset," the group of charge 0 by four (for example: before "minus, this combined" signal, before the charge). In this way, you can perform the following steps to obtain the "average, value" of the pixels sampled by the four-correlation double sampling: merge and divide (average, sub-sampling) the four-correlation "reset," charge to obtain An average reset charge qravg, merge, and divide (average, sub-sampling) the four related "signals," the charges to obtain the eleventh average flood charge qsavg, and then subtract from the average signal charge Qsavg De-average reset charge qravg to perform the correlated double sampling action (subtraction). Since the result of this method is an accurate sub-sampled day prime value, where the sampled pixel value represents the mathematics of the pixels sampled by four correlated double sampling Averaging, so this common method is referred to here as correlated double subsampling (CDSS). Instead of performing four-correlated double sampling subtraction, as in the conventional art, only the "average" (subsampling), "Reset," and "signal" perform a correlated double sampling subtraction. In this way, accurate sub-fetching can be performed before the last correlated double sampling subtraction In an embodiment of the present invention, the 'correlated double subsampling CDSS has a subsampling ratio B (SUBSAMPLING RATI0) (—integer (INTEGER) 19 200533191 l63 ^ pif to the power of two: for example, 4, 9, 16, 25, … Etc.), where B is equal to four, and can be performed by the following three steps. In the first step, the two pairs of reset voltages (charges) are averaged in the direction of the column, and the signal voltages (charges) of the rain pair are in the column. The directions are averaged. In the second step, the two averaged reset voltages are averaged in the row direction to obtain the final (average) reset voltage, and the two averaged images (in the row direction) The signal (voltage) is averaged to obtain the final (average) image (signal) voltage. In the third step, the final (average) average reset voltage is subtracted from the final (average) image (signal) voltage. Analog subtraction (for example: using a single analog subtractor). In this embodiment, the "average of the charge" includes combining the charges stored by the four-capacity capacitors into one larger effective capacitor (EFFECTIVE CAPACITOR) (for example: 4C ), Including merging The charge is distributed between a suitable number (eg, the same number) of equal valleys (eg, C). A further embodiment of the present invention is to provide an image sensor (such as a complementary metal-oxide-semiconductor image sensor CIS), which includes a daylight array arranged in a plurality of rows and a plurality of columns. Each day element in a column is connected to an average unit (AVERAGING UNIT) in operation, where each average unit π includes a first and a second storage capacitor (stOrage CAPACITOR), where this first The first and second storage capacitors are used to store analog reset data (anal0g RESETDATA) from the first and second storage elements, and the third and fourth storage capacitors, wherein the third and fourth storage capacitors It is used to store analog image signal data from the first dioxin and the second dioxin. In order to make the above and other objects, features, and advantages of the present invention more obvious, the following describes in detail the preferred embodiments and the accompanying drawings. [Embodiment] FIG. 3 is a block diagram of a complementary metal-oxide-semiconductor CMOS image sensor (CIS) according to an embodiment of the present invention. The complementary metal-oxide-semiconductor CMOS image sensor CIS includes a main animation element. An array of sensors (Aps), and an averaging and comparison circuit for performing correlated double subsampling (CDSS). FIG. 4 is a circuit diagram of an exemplary structure of a daylight element (STRUCTURE) in the main animation element sensor (APS) array of FIG. 3. Referring to FIG. 3 and FIG. 4, the main animation element sensor (APS) array is composed of a number of conventional day circuit elements, or preferably, the book element circuit of FIG. 4 is modified to sequentially output a VR (Reset) voltage and a VS (video signal) voltage. Each day element in the main video element sensor (APS) array usually contains a photoelectric converter (PHOTO-ELECTRIC TRANSDUCER) (for example: photodiode PD in Figure 4). Row driver circuits are well known in the art of learning, and here the embodiment of φ according to the present invention is modified to sequentially select the row number (NUMBERED ROWS) in the case of correlated double subsampling (CDSS) They are odd (ODD) pairs of (1, 3, ...) and even (EVEN) pairs of (2, 4, ...). In particular, one of the majority lines used to transmit an active row select signal (SEL) is used to select (enable) this active row. When the charge / voltage stored in the capacitor related to the pixel photodiode PD is read, the switch Tn controlled by the routing signal TX is closed. 21 5-position switch ττχ is normally open during reset operation. Ττχ is closed at the same time as the reset switch TRX, so that the pixel's photodiode PD diffusion area (DIFFUSION AREA) is also reset. The reset signal RX used to control the switch trx is easily recognized by those skilled in the art. The switch TRX is next to the switch ττχ controlled by the signal TX, which is used to store the information related to the photodiode PD. The charge / voltage in the capacitor is reset to a "reset" level. The transistor TAMP is a "voltage follower, an amplifier, which is used to change the charge / voltage stored in the capacitor related to the photodiode PD to a corresponding voltage / current. This voltage / current is sufficient It is passed to and stored in the capacitor of the averaging and comparison circuit (refer to Figure 3 and Figure 4). The switch Trx controlled by the reset signal RX will be closed at the beginning of each day reading, and this will end with Reset of capacitor charge / voltage related to photodiode PD. "Reset of capacitor related to photodiode PD, charge / voltage provides output voltage level (〇υτρυτ VOLTAGE LEVEL) VR at the output point out When the switch tsel is closed). When the active daylight sensor APS array is exposed to a real image (light), the ^ diodes in the array and the capacitance associated with each pixel will produce a "Image / signal, charge (voltage) with the same intensity (brightness) on). When the switch ττχ is closed and Trx is open, the actual light sensing" image flood "will be" magnified "by the amplifier τΑΜΡ and switched on When Tsel is closed, it will be transferred to the capacitor in the averaging and comparison circuit (refer to Fig. 3 and Fig. 4) as the image signal and the voltage will be stored in this capacitor. Fig. 5 shows the active element in Fig. 3 The sensor array (Aps array), the color in the 200522, the sensor's Belle pattern arrangement (COLOR SENSING PIXEL) and its output block diagram. We can use the Belle pattern color filter array (COLOR HLTER ARRAY) (CFA) is superimposed on each photodiode of the main animated pixel sensor array to implement a Bell diagram (such as the photodiode PD of FIG. 4). The embodiment of the present invention is modified to change the same color to four The day prime combination together "average, (to And related double subsampling (CDSS)), for example: red day pixels Rn, R13, R3, and R33 are arranged in a 4x4 pixel area; for example, the particularly bright pixel area in FIG. 5. Correlated Double Subsampling (CDSS) —The four-pixel combination from which the sample is taken is usually composed of the same color celestial elements from the same two rows and the same two columns, as in the digital domain of conventional techniques. In this way, the red daylights Rll, R13, R31, R33 will be sampled by the correlated double subsampling (CDSS), and (simultaneously) the green daylights G12, G14, G32, and G34 will be sampled by the correlated double subsampling (CDSS). Sampled. Then, the green pixels G21, G23, G41, and G43 will be sampled by the correlated double subsampling (CDSS), and the blue pixels B22, B24, B42, and B44 will be sampled by the correlated double subsampling (CDSS). The results of correlated double subsampling (CDSS) such as the four combinations (red, green, blue, green) of the same color daylight are the four accurate "averages" of the corresponding red, green, blue, and green daylight. '' Pixel value. In this way, performing a correlated double subsampling on a main animation pixel sensor APS array will effectively subsample the pixel area (in the analog domain), while also modifying the static fixed pattern Noise (FPN) and several types of timing noise. Individual row selection signals (R0w SELECTION SIGNAL) SEL1, SEL3 corresponding to row 1 and row 3 will be sequentially activated. When each row selection signal 23 200533191 16323pif When the .doc number is activated, all daylight elements in the active row (ACVTIVE ROW) first read its "reset" voltage VR, and then read its true "image signal," voltage VS. (Refer to the timing diagram of Figure 8A) As shown in Figure 5, the output order of each day element in the column \ will include the reduction from red ^ # t (RED-FILTERED PIXEL) R 11 (VR11 first, then VS ⑴) ^ Signal, and then output 5 tigers from the red filtered pixel R31 (VR31 then ▽ §31). However, the output order in column 3 will include the output from the red filtered metal R13 (VR13 then VS13), and then from = Color ^ wave β Qian R33 (VR33 then VS33) output signal. In the alternative embodiment of ^, the order of starting line 1 and line 3 can be reversed. The same (though not shown in Figure 5, but (Shown in Figure 6), the simultaneous output of each day element in column 2 will include the signal output from the green filtered day element G12 (VR12 then VS12), and then output from the green filtered day element G32 (VR32 then ^ s32) And the simultaneous output of each day element in column 4 will include the signal output from the green filtered day element G14 (VR14 then VS14), and then the signal output from the green filtered pixel G34 (VR34 then VS34). Line • The values of each day element in 2 and 4 are not output until the value of line ^ and element 3 in line 3 are compared. Until the sampling of the double subsampling (CDSS). Once, Figure 6 shows the complementary metal oxide semiconductor ^^ 08 image sensor (CIS) of FIG. 3, which is used to perform the majority of the correlated double subsampling (CDSS). A block diagram of the internal connections of each average 苎 comparison sheet = (ACU). In the -column of the active = prime sensor APS array, every _day prime is connected to a vertical transmission line (via its individual TSEL switch) Connected, and (period) connected. In this way, the four shown in Figure 6 are adjacent; 24 20053¾¾ i6323pif.doc

The unit (ACU) corresponds to the adjacent column in the Aps array of the active daylight sensor (Bus 2, 3, 4). In this way, any reading in the = '-average-cum-comparison unit (ΑαΜ) and the third average-cum-comparison unit ^ (ACU-3) will receive analog book materials received from the same color day element (For example: first filter pixels R11 and R13 from red = pixels and R33, and then from green wave diurnal and, == and then filter pixels G41 and G43 from green). In this way, in order to effectively `` average '' the received analogue daylight data related to the same color daylight (combined in the analog field), the first average and comparison unit (ΑαΜ) and the third average time The comparison units (ACU_3) are connected via a first average switch (switchable to each other). Similarly, the second average and comparison unit (acu_2) and the fourth average and comparison unit (ACU_4) are connected to each other (switchably) through a second average switch. "Averaging, the function of the switch Savg will be explained in more detail in the discussion of the circuit diagram of Fig. 7 which shows the first average and comparison unit (ACU-1) and the third average and comparison unit (ACU-3) in more detail. In the complementary metal-oxide-semiconductor image sensor (CIS) of FIG. 3, the structure and working method of the average and specific driver units (ACUs) will be described with reference to FIGS. 7 and 8a. FIG. 7 illustrates the complement of FIG. 3 Detailed circuit diagram of the 'two switchable internally connected averaging and comparison units (ACU) in the metal oxide semiconductor CMOS image sensor (cis). Figure 8A shows the complementary metal oxide semiconductor cmos image sensor (Figure 3) cis), timing diagrams of the waveforms of each switch and the waveform of the row select (rwwELEL) signal used during the execution of the correlated double subsampling (CDSS). 25 200533191 16323pif.doc (Figure 3) Averaging and comparison circuit ( Each average and comparison unit (ACU) in AVERAGING & COMPARING CIRCUIT (for example: first average and comparison unit (ACU-1), second average and comparison unit (ACU-2), third average and comparison unit (ACU-3)) can be switched by each switch All pixels in a particular row are connected (via a vertical transmission line). Therefore, the first averaging and comparison unit (ACU-1) is operationally connected to each pixel in the first column (column 1) of the pixel, Including pixels R11, R31, etc. Similarly, the third average and comparison unit (ACU_3) is operationally connected to each day element in the third column (column 3) of day elements' including pixels R13 and R33 Etc. Generally, each pixel in each column of the main animated pixel sensor APS array is operationally connected to a vertical transmission line (through its individual TSEL switch) and is also connected to an averaging and comparison unit (ACU) During operation, one pixel in each column of the APS array of active daylight sensors is selected by a row of select control signal (r0w_SELect control signal) 'in a row with the main animation element sensor aps array All pixels connected by (horizontal) lines are started. If W is the number of pixels (integer) in a row of the main animation _ prime sensor APS array, then w will also be averaged and averaged in the comparison circuit Compare the number of units. (In an alternative embodiment of the invention, A number of average and comparison units ACU (for example, 2W) can be switched to connect to serve the w column. In this way, as described above, 'ACU, all average and comparison units ACU, including the first average and The comparison unit ACU-1 and the third averaging and comparison unit ACIj-3 will simultaneously receive analog pixel data from each day element arranged in the same row of the active day element sensor APS array. 26 20053, as shown in Figure 8A As mentioned, line 1 is activated first (by SEL1), and then line 3 is activated (by SEL3). In this way, during operation, the first average and comparison unit ACU-1 and the third average and comparison unit ACl > 3 will simultaneously extract from each of the four colors of the same color (such as Rll, r31, R13, R33). Take (and store) analog data including "reset" voltage and "image signal," voltage. Because the first average and comparison unit ACU-1 and the third average comparison unit ACU-3, by switching Savg Connected, so you can • Divide each other from the analog pixel data obtained from the four pixels of the same color (such as R11, R31, R13, R3). In particular, the first level and the next generation ... and the third average Cum comparison unit 'merges and divides (average, sub-sampling) each of these types obtained from the same color tetracycline ("reset" and "image signal,") to produce a "reset" charge / Average, value, and "image signal, charge / voltage VS", "average, value" of each voltage / VR. Each average and comparison unit aCU (such as the first average and comparison unit ACU-1 and the third average and Comparison unit aCU-3) has been modified into The "average" value of the "image signal" charge / voltage, "minus Φ to reset" the "average" value of the charge / voltage is used to output a final analog daylight data, where this final analog daylight The data represents the accurate mathematical average of this four-day prime sampled by the correlated double sampling CDS to remove static fixed pattern noise (FPN). Each average and comparison unit AOJ includes an analog subtractor (ANALOG SUBTRACTOR) (eg A subtractor q, and a subtractor-2), and an amplifier AMP1 for receiving and transmitting the output of such a ratio subtractor. The amplifier AMP1 can be implemented as a non-inverting buffer (ie 27 200533191 16323pif.doc

Vref 20), or, as shown in the preferred embodiment, a differential amplifier (DIFFERENTIAL AMPLIFIER) connected to a reference voltage Vref and used in parallel with an analog-to-digital conversion (ADC) connected in parallel. This arrangement allows the bias source (BIAS SOURCE) (Vramp) to be at the first voltage level during the average operation period and to be at the first voltage level during the analog-to-digital conversion operation period. The first voltage level is different from the second voltage level. Voltage level. The buffer capacitor (BUFFER CAPACITOR) (CA) and the second output amplifier APM2 are both freely selectable and are included in this preferred embodiment (shown in Figure 7) to increase the analog-to-digital conversion (ADC) Resolution Gain (GAIN). The output of the analog field subtractor in each average and comparison unit ACU (such as the first average and comparison unit ACU-1 and the third average and comparison unit ACU-3) is sensed by the amplifier i and is freely accessible by a The selected valley is buffered by CA and further amplified for analog-to-digital conversion and then amplified by a freely selectable second amplifier AMP2 to output a voltage signal representing the average VS-VR (eg: VCD1 戋 VCD3 ). In the preferred embodiment, Jie Lu includes each analog field subtractor (for example: subtracter 1), and may essentially include a plurality of data storage capacitors (DATA STCAPAGE CAPACIT0RX) connected to a common point. CS1, CS3, CR1, and CR31 in an average and comparison unit ACU-1), where this common point is located on the vertical transmission line connected to each pixel, where each pixel is located in the average and comparison unit Acu servo through the switch S1 (For example, the pixels in column 丨 are fed by the first average and comparison unit AOM). The four data stores in each average and comparison unit acu 28 20053 ^ 191 16323pif.doc The storage capacitor is determined in accordance with the switching connection order of all the majority of switches (such as Si, S2, S3,, ss, SR) , Fill and store the predetermined analog pixels received from one of the primaries (for example: a pixel from the first row of the same column, or a pixel from the third row of the same column) Data charge (ANALOG PIXEL DATA CHARGEX, for example: "Reset," or "Signal" data), where these pixels are connected to the average and comparison unit ACU (for example: the first average and comparison unit. At each average and comparison Unit ACU (and in each average and comparison unit Acu, zero f is 1, for example: Savg) the corresponding switches (for example: S2, ss, SR, S4) are open or closed at the same time. In each average and Each switch (for example: sl, S2, ss, SR, S3 ^ 4ymu) is open or closed with the line selection signal (for example: SEL), as shown in the timing diagram in Figure 8A. S4, SS and SR switches to control each day element and four storage capacitors (Such as: csu, CS31, CRn, CR3i) and other current paths, so that these four storage capacitors are bound to # fill the analog daylight data in the following order: The storage capacitor CRU stores the data from daylight R11 (No. 1 column, row!) "Reset, the charge, storage capacitor CS11 stores the signal from day element RU (column! Column, line!), And the charge, storage capacitor CR31 stores the signal from day element R31 (first Column, row 3), the "reset" charge, and the storage capacitor CS31 stores the "signal" charge from day element R31 (column! Row, row 3). The alternative is-in each average and comparison unit (Acu) Uncorrelated double subsampling mode M_-cdssmode) (for example: during a standard correlation 29 200533191 16323pif.doc double sampling CDS mode) 'in every-average and comparison unit (ac cut in (every-th-average and comparison unit) (ΑαΜ) and the second averaging and comparison unit (ACU-2)), CR "reset, one of the data storage capacitors (for example: CRn or CR31 ·, or CR11 and CR31 effectively merge into a capacitor) and then CS" Signal, one of the data storage capacitors (eg : CS11 or CS31 'or CS11 and CS31 effectively merge into a capacitor) will be loaded with the analog diurnal received from-diurnal. So-this, the majority of the average and comparative unit (ACU) will be full (and Storage) The entire "reset ,, and" signals from the pixels and the middle row, analog day-to-day data. During the method of loading the data storage capacitors (CR and cs) in the average and comparison unit (ACU) , Can day and day in a single row (such as the first row) of an active day sensor array (APS) array (such as R11, = 12, R13, G14, ...)? The standard (non-sub-sampling) correlated double sampling was performed on the next line, and the selection line was activated according to that line, and the average and comparison of the second and second (wide) connection τ work (in non-correlated double sub-sampling_N -CDSS) mode) can be a single row (for example, on the day element by wa 仃) on the active day element sense (Aps) array (^, B22, G23, B24, etc.). The implementation of standard (non-subsampling) correlated double two (CDS). During the uncorrelated dual mode of each average and comparison unit (acu) (for example, in the standard correlated double sampling (⑽) mode, SR and Savg The switch does not need to be operated (for example, it can maintain an open circuit state). The relevant double subsampling (_person sampling) of the flat / denier comparison single 70 (Acu) work ^ period 'When each average and comparison unit (ACUX example: the first 30 200533191 16323pif.doc Eight storage capacitors in the switchable pair of one average and comparison unit (acim) and third average and comparison unit (ACl ^ 3)) are filled with R11, R31, R13, R33, etc. For the four-day analog ("Reset" and signal 1), the SS, SR, and Savg switches (with Sb, S3, S4, etc.) Related to the same) can be closed circuit in order to transfer all the four charges of the same type of four-day data ("reset" or "signal") received from the four pixels (R, U, R31, R13, R33) — From "Average," (combined and divided by division). However, the car's best implementation of the "Related Double Subsampling Working Method (A Correlated Double Subsampling (CDSS) Subsampling Mode) in an Average and Comparison Unit (ACU)" In the example, each type of analog daylight data ("Reset," or "Signal,") is transparent and closed by the σ average switch SaVg. Corresponding data storage capacitors (different columns: for example: first and third columns) are "averaged," (combined and divided by J, even though all data storage capacitors have been filled with analog day-to-day data (2 = 刖). In this way, for example, when the data storage capacitor CS11 receives the “signal from the pixel R11,” the data storage capacitor and the data storage capacitor CR13) will store the “double second of the day R11”. The "reset" of the raw materials and daytime R13 ,, and the value of the “Reset,” of the day R11. Subtract a switch, especially the average switch Savg, during the process of carrying four storage capacitors in each average and comparison table = CU), perform an average of two In the timing diagram of FIG. 8A, here, the high level indicates the switch of =. Essentially 'close the switch S1 (in all the average and early tg (ACU)) to make the corresponding data storage capacitor bank, for example: 2 〇〇mm fn, CR12 (not shown), CR13, CR14 (not shown the full-day-predetermined pattern of day-to-day analog data, where this pixel is located in the row determined by the row selection line activated Medium (for example, the row-selection line SEL1 for the row-), S1_ will be turned off, and the average switch Savg will be closed. (However, S3, S4, SS, and SR switches in all averaging and comparison units (acu) are open or closed. According to each average, which of the four data storage capacitors in the comparison unit (ACU) is reserved To receive that kind of analog data).踗 Η Case 2 Λ Katu M 'at time 0), when the average switch ㈣ is closed (for resetting, the data is loaded into CR11 and 晬 35f wide state). Then' at time ⑺ At the switch S1 is opened (the capacitors such as CR13 and the like are completely filled with "Reset, CR 2 2 1 of the day element data-closed circuit" is used to store the analog pixel 卜 3 capacitor 之前 not long ago. (Charge) Merged and used spear and 疋, in the analog pixel data (for example: `` Reset ,, data '' has been selected by m average and comparison unit (acu) each selected data storage capacitor »歹 | 〇: CRU, CR12, CR13, CR14,) open after receiving: 1 at: T road (indicating that the loading of these data storage capacitors is completed), the average opening between the door control and comparison unit (ACU) _ Savg was "paired with the same color and the same charge in the same row of each day element.) An example of the electric charge comes from the" reset "of pixels ri 1 and day element ri 3 (combined and divided by division). At the same time, the same type of analog pixel data (eg) received from the same line, such as the day element, is averaged (combined and divided by division) and Stored in each of the 32 20053M91 predetermined data storage capacitor pairs (eg, CR11 and CR13). This is generally the same line averaging methodology (the switch si is closed when the switch Savg is open). For example: at time (3), (5) , And; where switch S1 is open when the circuit is opened and closed, for example, at time (4), (6), and (8)) will be repeated to load each of the remaining three pairs of data storage capacitors A pair (for example: CS11 and CS13, then CR31 and CR33, and then CS31 and CS33), so that each average and comparison unit (ACu) (eg, the first average and comparison unit (ACIM) and the third average) Each of the four pairs of corresponding data storage capacitors in the comparison unit (ACU-3) is a `` reset, '' or `` reset, '' or a The "average" value of the tribute. Next, the same column averaging work (merging and dividing by) of the same type of daylight data received from the same column (SA) V [E_C0LUMN ^ each pixel (each daylight from different rows) will be performed. From Different rows (same columns) of the same column of the original data "average, (combined and divided by division) work, & in a very simple way to execute by the county: make off ss _ (for example in time (9 )) To equalize the "signals" stored in each CS lean storage capacitor pair (for example, CS11 and CS31 in the -average and comparison unit (AOM)) located in each average and comparison unit (acu), The data charge; and the switch SR is closed to equalize the data stored in each average and comparison unit (acu) and store the valley pair (eg, CR31 in the first average and comparison unit (acu)) "Reset" the data charge. On the same column at the end, two = steps, are located in the average and comparison unit U of each switchable connection (for example, the first average and comparison unit (ACU-1) and the third average Cum 33 200533191 16323pif.doc comparison unit (ACU-3)) four cs: body storage capacitor 3. CS31, ⑽) each maintain a uniform "signal" charge, which represents the four-charge ⑽ signal received from the same color tetracycline (for example: R1, R13, R31, and R33) The exact math is similar and similar. On the last (same column) "averaging" step, the average and comparison unit (ACU) located in each switchable connection (for example: the first average Lu comparison unit (ACU-1) and the first The three average and comparison units (acu_3)); each of the CR lean storage capacitors (for example: CRU, CR13, CR3i, cr maintains the same "average," reset, charge, its generation Accurate mathematical average of the four (reset) charges of tetrachromatic elements of the same color (for example: RU, Ri3, R3iiR3_. The average of two switchable connections in the correlated double subsampling mode and the eight data stores in the ACU Data loading between capacitors (CRU, CR13, CD, CR33 and CS11, CS13, CS3, CS33) and "average," work (used to perform the relevant double, time, etc. on R11, Rl3, New Zealand and R33) Sampling) to explain the following equations of tea test, in which Each charge at the time (⑴ to ⑼) shown in the timing diagram of Fig. 8A is shown. In these equations, Q represents the charge in the subscripted data storage capacitor 'and the number represents the equalization of the charge. It is assumed that each The capacitance (all the same types of data storage capacitors, CS or CR) are equal; the voltage indication in the subscript format (for example: Vresetu) indicates the same voltage as the "VRU"; the capacitor indication in the subscript format, such as CcR " / cR3i indicates that these sub-capacitors (the examples here are CRU and CR31) have been effectively connected in parallel (for forming—additional combined capacitors) regardless of whether they are temporary or not. 34 2〇5m? I At the time, the “reset” of the day element Rl 1 and R13, the voltage (Vri 1 and VR13) are individually sampled and individually loaded into the data storage capacitors cr ^ and CR13:

Rllpixel: Qcrii = Qcrbi-Ccr11 / cr3i (Vreseth-Vref) ^ Rl3pixel: QcR13-QCR33-Ccr13 / CR33 (Vr eseti3-Vref) At time (1), CS11, CS13, CS31, and CS33 capacitors are also used Recharge, but these initial charges are then replaced by the appropriate (image signal) pixel data received from the predetermined celestial element. At time (2), the R11 and R13 diurnal are individually reset. The voltage (VR11 and VR13) between the CR11 and CR13 capacitors (average switch Savg closed circuit) is "averaged" (combined and divided by except):

Qcrii = QCR3i = Qcrb = Qcrss = Ccrii / cr3i / cri3 / cr33 (· Υ_τιι + Vreseth _ vref,

k 2 J At time (3), the respective “images” of the two pixels Rll and R13, and the (signal) voltage (VS11 and VS13) are sampled and loaded into the data storage capacitors CS11 and CS13, respectively:

At time (3), both S3 and S4 switches are open (the capacitors CR11, CR13, CR31, and CR33 are stored in a reset state for storing the reset), and are used to store the reset, Voltage capacitors CRU, CR13, CR31, and CR33 all maintain their previous charge

Qcrii = QCR3i = QCRi corpse qCR33 (please refer to the time above). At time (4), the individual “images” of the two pixels of R11 and Ri3, (signal) 35 20053 voltages (VS11 and VS13) are all “averaged” between the two capacitors of CS11 and CS13 (average switch Savg closed circuit). "(Combined and divided by division):

Qcsil = QcS31 = Qcsi3 = QcS33 = CcSl 1 / CS31 / CS13 / CS33 + VSIGNAL13 v,, 2-V ramp

J At time (5), the respective “resets” of R31 and R33 diurnal, the voltage (VR31 and VR33) are sampled and loaded into the data storage capacitors CR31 and CR33, respectively: • R31 pixel: QCr3i = CCr3i (Vreset3i-Vref) R33 pixel: QcR33-CcR33 (VrESET33-Vref) at day guard (5) 'Because the switch SS is open (the capacitors CS11 and CS13 for voltage storage are floating), And open ^ ^ is also open (to store "reset, voltage capacitors CR11 and CR13 are floating state), CS11, CS13, CR11, and CR13 capacitors individually maintain their previous charge. In time (6 ), R31 and R33 diurnal are individually reset, and the voltages • (VR31 and VR33) are both “averaged” between CR31 and CR33 two capacitors (average switch Savg closed circuit), (combined and divided Divide): QCR3, = QCR33 = CCR31 / CR33 ^ ^ ^ At time (7), the individual image (signal) voltages (VS31 and VS33) of the two pixels R31 and R33 are sampled and loaded into the data storage capacitor CS31 Among CS33: 36 2005VJll lo323pif.doc R31 pkel: QCS31 = CCS31 (VSIGAL31 — Vramp) R33 pixel: QCS33 = CCS33 (VSIGAL33 — Vramp) At time (8), the individual “images” of the two pixels of R31 and R33, (the signal voltage (VS31 and VS33) are in the CR31 and CR33 capacitors (Average switch Savg closed circuit) is "averaged" (combined and divided by division): QCS31 = QCS33 = CCS31 / CS33 ί ^^ 1 ± ^ Coffee 3. Vref 'v 2 j At time (9), execute the last Average (four “reset,” and four “signal” charges). The two (same row) “AVERAGED RESET” voltages stored in each average and comparison unit (ACU) are both Is averaged (when the switch SR is closed) into an "average reset, charge qravg; and two (same row)" averaged signal "(average signal) stored in each average and comparison unit (ACU) The voltages are averaged into an "average signal" charge QSAVG (when the switch SS is closed):

QrAVG ^ QcRI 1 = QcR3 1 = QcR13 = QcR33 and

Qravg = CcRll / CR31 / CR13 / CR33

VrESET 11+ VrESET13 + VrESET31 + VrESET33 4 -Vref

QsAVG = QcS 11 = QcS3 1 = QcS 1 3 = QcS33 and

QsAVG = CcSll / CS31 / CS13 / CS33

VsiGNALll + VsiGNAL13 + VsiGNAL31 + VsiGNAL33 Λ r, --J --- V ref 4 In this way, it can be obtained by the closed circuit of the two switches SS and SR (example 37 200533191 16323pif.doc eg. From QSAVG and QRAVG) The last "average" of the same color tetracycline and the "voltage difference between subsampling," (VS_VR). After the last average, such as after time (9)) are stored in the first and third columns The charges in the corresponding CS and CR 中 storage capacitors in the first comparison unit ACW and the third average and comparison unit Na3 store the same "average," charge obtained from the four pixels. In this way, one of the VCD1 and vcd3 outputs can be used for reading (for analog to digital conversion) generation.

The table shows the final "voltage difference" (VS-VR) sampled by the four-correlation double subsampling of the same color. Figure 8B shows a ramp voltage (RAMPING VOLTAGE) and a ten-degree latch control. 5 Tiger (COUNTER) -LATCHING CONTROL SIGNAL) Timing chart, where the ramp voltage and this counter latch control signal waveform are used to simultaneously execute most of the complementary metal-oxide-semiconductor CMOS image sensor (CIS) from Figure 3. The analog-to-digital conversion of most outputs of the average and comparison unit (ACU). After the final average (for example, after the time (9) mentioned in Figures 8A and 8B), it is stored in (the first column and the first column Three-column) "AVERAGED RESET" and "Averaged Reset" in the corresponding CS and CR data storage capacitors in the first average and comparison unit ACU-1 and the third average and comparison unit ACU-3 ”(AVERAGED SIGNAL) charges are all made using the analog domain subtractor (ANALOG DOMAIN SUBTRACTOR) in the average and comparison unit ACU (such as the first subtracter (SUBTRACTOR-1) of the first average and comparison unit ACU-1). Compare to get this initiative A single (subsampled) value of the daytime element 38 200533191 16323pif.doc sampled by the four-correlation double subsampling (CDSS) of an element sensor (APS) array. A subtractor consisting of two capacitors in series, CS and CR (eg, the first A subtractor (SUBTRACTOR · 1)) is connected between Vramp and the input of the amplifier AMP1. Therefore, the voltage at the input terminal of the amplifier Αρι represents the sum of Vramp + VS + (_ VR), which is because of the polarity of the VR charge stored in the capacitor CR, The polarity of the charge stored in the cs capacitor is connected in anti-phase (in series). In this way, the voltage at the input of the amplifier Ampi is the Vramp latched by the (average) VS_Vr. The counter enable signal (c〇 UNTEr enable

SIGNAL) (CE) (refer to Figure 3) can be scheduled to determine that counting starts after the last average (after both SS and SR switches are closed). Therefore, by increasing the voltage Vramp with a known (predetermined) slope or at least with a fixed slope, and simultaneously starting the counting of this counter (for example, in the digital signal and output circuit of Figure 3), the VS-VR's The magnitude is converted from an analog value to a quantized digital value. When the input of the amplifier AMP1 (from the output of the subtractor) crosses a predetermined threshold voltage level (THRESHOLVOLTAGE LEVEL) (for example: Vref) , The size of the VS-VR is converted from an analog value to a quantized digital value by locking the count. The larger the size of VS-VR, the shorter the time (count) required for the amplifier AMP1 to reach the threshold voltage (vref). When the input of the amplifier AMP1 reaches the threshold voltage (Vref), the value of the signal VCD of the average and comparison unit ACU (for example, · VCD1 of the first average and comparison unit ACU-1) will change from low to high. Therefore, the signal VCD (for example: VCD, VCD2, VCD3, ...) from each average and comparison unit ACU can be output to the latch circuit (LATCH CIRCUIT) (refer to Figure 39 20053¾ 9) as a count latch control Signal (c〇UNT-LATCH SIGNAL) 〇 FIG. 9 shows a block diagram of the counter and latching circuit (COUNTER LATCHING CIRCUIT), in which the counter and the latching circuit are used to simultaneously execute the complementary metal-oxide-semiconductor CMOS from FIG. 3 In the image sensor (CIS), the analog to digital conversion of the majority output (VCD) of the plurality of average and comparison units (ACU). When the counter enable signal (COUMTER ENABLE SIGNAL) (CE) is activated, this counter starts to output a digital counter (e.g., a four-day prime in the average and comparison unit (ACU) in the related double subsampling CDSS mode). "After the final averaging, or after only one day of prime data is loaded into each averaging 1 comparison unit (ACU) during the standard correlated double sampling CDS mode). The latch circuit includes a number of parallel count locks Coontatch (each AOJ includes-one), showing: these count latches at the time points of __ inputted by the respective average and comparison units (acu) On the count output lock, η device. The CD output from each average and comparison unit (acu) can be provided to each individual count latch (located in the latch circuit towel), ^^; (cAdC: from low to threshold value, this is provided to ^, so when the counter reaches its count store this count value. Because most average and comparison = stand) Most latches in the material path (stored for every 2 〇〇53mi The contents of an average and comparison unit (ACU) counter value) can be output To a digital signal processor (DIGITAL SIGNAL) for further changes or storage or sending (sub-sampled or non-sub-sampled) pixel data from this average and comparison unit (ACU).

FIG. 10 is a diagram illustrating a complementary metal-oxide-semiconductor CMOS scene in FIG. 3 according to still another embodiment, and the main animated pixel sensor (Aps) of which the image sensor is (CIS) is used to perform correlated double subsampling (CDSS) , Whose average / time sampling reaches N2 celestial factors (with a ratio of greater than 4: undersampling ratio) between a plurality of average and comparison units (acu) to switch between the money graph. Except that the internal connection of each switch between the average and comparative unit (NACU) in Figure 1G is more flexible, the average and comparison circuit in Figure 10 is similar to the report in Figure 6, in this figure, it can be connected at the same time. Greater than two (for example: N) average and comparison units (acu) in different rows. The added internal connection supports the σKia of the charge (reset and signal) of each day element, and divides and gives the average action. Among them, these pixels come from at least: column: Γ as shown in the average and comparison table in Figure 6. OJ) 's connection pair. Therefore, the N-number of average and comparison units (NACU)

Two tf :)) are connected at the beginning, each of which contains N CR αα = 3 ^. F material storage capacitors (replaces only 2 2N subcapacitors 11 and 2 Csf material storage capacitors), showing an "average," 佥 ♦-type daylight region, which can be sub-sampled to the meter connection system ^ J㈤-4 color post Therefore, in the complementary metal oxide semiconductor CM0S image sensor in 1 in Figure 10 (CIS), N can be a double subsampling (_), which is any integer (for example, 2, 1, See Figure 6 and 200533191 16323pif.doc for an example in Figure 7.) Figure 11 shows a detailed circuit diagram of an enhanced average sound comparison unit (NACU) according to yet another embodiment of the present invention, which is used to complement Figure 3 In the main animated pixel sensor (Aps) of the metal oxide semiconductor CMOS image sensor (ClS), -2Nx2N daytime pixels of the same color in the region, perform the relevant double subsampling CDSS average / subsampling up to the number of furnace pixels The enhanced average and comparison unit (NACU) described in Figure u is very similar to the average and comparison unit (ACU) described in Figure 7, except that the enhanced average and comparison unit described in Figure η

• The analogue field subtractor in (NACU) includes 2N analog pixel data storage capacitors (eg 2N-2, 6, 8, 10) instead of four analog daylight data storage valleys (and additional switches such as SSN ) Outside. This additional data storage trough (and additional switches to control its loading and averaging) is supported in the active daylight sensor APS array-2N X 2N area, arranged in the same color in different columns and different rows Correlative double subsampling of average daily subsampling in CDSS mode. CR # (reset) data storage capacitor in the subtractor of the enhanced average and comparison unit (NACU) (eg, N subtractor-1 (NSUBTRACTOR-1)) from the enhanced average and comparison unit (NACU) The (reset) voltage (VR) of each pixel of the connected column is charged (loaded) from CRN to CR1. CS (reset) data storage capacitor in the subtractor (eg, N subtracter-1) of the enhanced average and comparison unit (NACU), with the same elements from the columns connected to the enhanced average and comparison unit (NACU) The daytime (video signal) voltage (VS) is charged (loaded) from CSN to CS1. Because the enhanced average and comparison unit (NACU) of each pixel of each pixel is required to perform the average / subsampling of the correlated double subsampling CDSS, the enhanced average and comparison unit (NACU) of Figure 42 20053MM, 11 will be shown in Figure 1 The method described in 〇, similar to other at least N-1, the improved average and comparison are switchably internally connected. In fact, due to the enhanced average and comparison unit (NACU) of graph u, it is also possible to calculate 2, 3 or any smaller integer L (less than n pixels, such as L = 1, 2, 3) Correlation double subsampling average / subsampling is performed, so all other enhanced averaging and comparison units (NACU) in complementary metal oxide semiconductor CMOS image sensors (CIS) (e.g., odd numbers ), Can be switchably internally connected in the manner described in FIG. However, each "average," the switch Savg can be controlled independently or dynamically in order to prohibit all other (eg, odd number) enhanced average and comparison units (NACU) (containing L odd number of improved average and comparison Each of the enhanced average and comparison units (NACU) in the first block of the unit (NACU) and all other (eg, odd number) average and comparison units (^ ACU) (accommodates the other l odd number of average and comparison units ( (ACU) "Evenly connected between the enhanced average and comparison units (NACU) in the second square. In this method, only from the same 2N X 2N or (2L · X 2L) daylight region The pixels of each block can be averaged together during the correlated double-sampling CDSS mode of each block between the L or N switchable internally connected enhanced average and comparison unit (NACU). By dynamically controlling Savg, SI , S2, S3, S4, and (SSI, SS2, ..., SSN) and (SRI, SR2, ..., SRN) and other switches, the enhanced average and comparison unit (NACU) of this embodiment can be used to Configure the same color in a square (or non-square) daylight region-a dynamic selection number Measure L2 (as low as 丨 2 and as high as N2) pixels, and perform sub-sampling. 43 20053m 雔 Repeat sub-sampling; at least consistent embodiments provide a method and device for performing correlated and heavy-human sampling (CDSS) , Which includes: "in the flat analog domain) these 彳 < the" reset "values received by most of the day elements and in the" flat analog domain "these slaves? The "signal" value received by several pixels is formed into a step, followed by the "average, reset value" is subtracted from the "average," signal value to generate-related double silk Sampling (CDSS-SAMPLm)), where the correlation is double-sampling

The analogy sampled represents the exact mathematical mean of the celestial samples sampled by this traditional four-correlation double sampling of the same age. In this way, this embodiment of the present invention provides the ability to directly and accurately subsample most of the daylight elements in the active daylight sensory (APS) array while removing static M noise (FPN) in the analog field. . Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make some changes and decorations without departing from the spirit of the present invention. Therefore, The protection scope of the present invention shall be determined by the scope of the attached patent application. [Brief description of the diagram] Fig. 1 is a block diagram of a complementary metal oxide semiconductor CMOS image sensor (CIS), which is not a conventional technique. The complementary metal oxide semiconductor CMOS image sensor includes a main animation element. Sensor (APS) array. FIG. 2 is a block diagram of a related art double-sampling (CDS) circuit, in which the double-sampling (CDS) circuit is modified to an average of four days of the same color. FIG. 3 is a block diagram of a CMOS image sensor (CIS) 44 200533191 16323pif.doc according to an embodiment of the present invention. The CMOS image sensor (CIS) includes an active daylight sensor. Elementary sensor array, and an averaging and comparison circuit for performing correlated double subsampling (CDSS). 1 FIG. 4 is a circuit diagram of an exemplary structure of each day element in the main animation element sensor (APS) array of the complementary metal-oxide semiconductor CMOS image sensor CIS of FIG. 3. Fig. 5 is a block diagram showing the arrangement of the bell pattern of the color sensor pixels (COLOR SENSING PIXEL) in the main animation element sensor (Aps) array of Fig. 3 and the block diagram of each output thereof. FIG. 6 shows a plurality of AVERAGING & COMPUTING UNITs (ACU) in the complementary metal-oxide-semiconductor CMOS image sensor (cis) of FIG. 3 for performing correlated double subsampling (CDSS). ) Switch between internal connections. Figure 7 is a detailed circuit diagram of the 'A switchable internally connected averaging and comparison unit (ACU)' in the complementary metal-oxide semiconductor CMOS image sensor (CIS) of Figure 3. FIG. 8A shows a timing diagram of the waveforms of the switching Λ and row selection signals used in performing the correlated double subsampling (CDSS) in the complementary metal-oxide semiconductor CMOS image sensing system (CIS) of FIG. 3. . Fig. 8B shows the timing diagram of a ramping voltage (RAMPING VOLTAGE) and a count of a latching control signal (COUNTER-LATCHING CONTROL ^ IGN ^ L). Among them, the ramping voltage is different from this. In order to latch the control signal waveforms, the complementary metal 45 200533191 from FIG. 3 is used to simultaneously perform analog-to-digital conversion of the majority of the average and comparison output of the 7L (ACU) in the semiconductor CMOS image sensor (CIS). FIG. 9 is a block diagram of a counter and a latch circuit (counter LATCmNG aRCUIT), wherein the counter and the latch circuit are used to simultaneously execute the CMOS image sensor (CIS) from the complementary metal oxide semiconductor of FIG. 3 'Analog-to-digital conversion of majority output (VCD) of majority average and comparison unit (ACU). FIG. 10 is a diagram illustrating a complementary double subsampling (CDSS) in the active daylight sensor (Aps) of the complementary metal-oxide semiconductor CMOS image sensor (CIS) of FIG. A block diagram of the internal connection between the average and comparison units (acu) of the N2 day sample (at a subsampling ratio greater than 4) per sample. 0 FIG. 11 is a detailed circuit diagram of an enhanced average reputation comparison unit (NACU) according to yet another embodiment of the present invention, which is used for the main animation of the complementary metal & semiconductor CMOS image sensor (CIS) of FIG. 3 In a pixel sensor (Aps), pixels of the same color in a 2Nx2N area are subjected to correlated double subsampling. The average / subsampling of CDSS reaches as many as N2 day pixels. [Description of main component symbols]

Vramp: bias source S2, S3, S4, SS, SR, Savg, 2, 20, 2la, 21b, 52, Tτχ, TRX, TAMP, TSEL: switches csil, CS13, CS3, CS33, CRU, CR13, CR3, CR33, CS1, CSN, CR and CRN: data storage capacitor CA: buffer capacitor 46 200533191 16323pif.doc AMP1, AMP2: amplifier,

Vref: Reference voltage source VCD and VCD3: Voltage signals VR11, VR12, VR13, VR14, VR31, VR32, VR33, VR34 "Reset" voltage VS11, VS12, VS13, VS14, VS31, VS32, VS33, VS34: " "Image" (signal) voltage

SEL, SEL1, SEL2, SEL3: Active line selection signals B22, B24, B42, B44: Blue pixels 30: Common output lines 50, 50a, 50b, 51a, 51b. Correlated double sampling (CDS) capacitor CE: Counter Enable signals G12, G14, G21, G23, G41, G43: Green pixels 48, 48a, 48b: Non-inverting buffers 54, 54a, 54b: Output amplifier PD: Photodiode

Rll, R13, R31, R33: Red pixels RX: Reset signals 44, 44a, 44b: Sample-and-hold capacitors 42, 42a, 42b: Sample-and-hold switches TX: Signals CL1, CL3: Vertical selection lines

Vcd, VCD1, VCD2, VCD3, VCD4: voltage signal 47

Claims (1)

20053 View ten. Scope of patent application: Zhisu, which includes a large number of rows and columns connected to store two and at least two capacitors for storage; =: electricity: and includes at least two images The video system described in the item 1 of the asset-average method, including the production of the average circuit using the at least two resets, is generated by an average reset charge. The image sensor described in the first item, wherein the second image charge is performed to generate an average image signal. The image sensor described in the third level of the Pingli domain, complex, and analogy. "Subtraction cry, JL 丨 brother" The image sensor described in the "item" also includes the charge from the flat ": === reset-class: === item = image sensor, more (ADC7) = ; Do this! Move_Analog to Digital: Switch to the digital converter and average the electric power ^ In the y❹❻image ❹❻1 described in item 6, === The analog to digital converter (view) is usually made by the same-bias ^ The 7th scope of the patent application No. 7 the bias source _ the first and second stationary period image ^ Second: _ its first Zhongyi Electric 48 20053 vertical L 縻 level is in the -th ratio; working period ^ Bit. ^ The first voltage level is different from the second voltage and the ninth one === 2 ^ The image sensor described in the above, wherein the reset values of the element are equal to :::: == The reset materials of the pixels will be arranged in the same size, μ, the average circuit 4 is specifically for the image sensor described in item 2, wherein the switch includes-is disposed in the at least The resetting the image sensor between the data capacitors as described in item 3 of Lu Shenwei, wherein, the switch between the two. Dagger—The image sensor is disposed on the at least two image signal data capacitors. The image sensor described in the first item, wherein 14% is a complementary metal-oxide-semiconductor CMOS type. Fang Ban, ·: A kind of piano 2 that samples the daylight in the active daylight sensor (APS) array. · The pixel that will receive L2 pixels from the active daylight sensor (APS). The method of resetting the data charge and storing it in the N2 capacitors, sampling method, and more will include receiving from the initiative ~! KA12) The L2 day pixel image data of this l2 analog pixel is stored in a second group of N2 capacitors. 16. The method for subsampling the day element in the main animation element sensor (APS) array as described in item 14 of the scope of patent application, further comprising: the L2 analog stored in the first group of the N2 capacitors A first averaging operation is performed on the pixel reset data charge. Π. The method of subsampling a daylight in an active daylight sensor (APS) array as described in item 6 of the patent application range, wherein the first average work is performed in the analog field. 18. The method of subsampling a daylight in an active daylight sensor (APS) array as described in item 16 of the scope of patent application, wherein the first averaging work includes merging all of the L2 analog daylighting reset data charges . The method for sampling daylight in the active daylight sensor (APS) array as described in item 16 of the material benefit range, wherein all the data charges of the resetting daylight reset are included in the N2 capacitors, and at least two are connected in parallel. Capacitor. The method of sampling the daytime element in the main animation element __ and the train line described in item 18 of the patent scope includes the analogue of the daytime image clear charge on the N2 capacitors: Including merging all of the methods, its t's two-average work package includes the charge of the electric charge, and more than 22 capacitors are connected in parallel between the 22 groups. As described in the application section (21), in the silk 4 element sensor (50, 2005, c, yAPS) array towel: the method of undersampling the day element, including performing two subtraction operations in the analog field, of which a differential The voltage is obtained by connecting at least one capacitor between the -group of N2 capacitors and at least one capacitor between the second group of n2 capacitors in series. 23. The method of subsampling a daylight sensor in an active daylight sensor (APS ^ array as described in item 22 of the scope of patent application) further includes performing an analog-to-digital conversion of the differential voltage from the subtraction operation ( ADC) 24. The method for sub-sampling pixels in the main animation pixel sensor (APS) array as described in item 23 of the scope of patent application, wherein the average operation of the differential voltage and analog-to-digital conversion ADc are This is performed using a circuit that is pressed by a single bias. 25. The method of subsampling a daylight in an active daylight sensor (A ^) array as described in item 23 of the scope of the patent application, wherein the single bias source is at a low voltage level during the average operation period. And during the analog-to-digital conversion ADC is at-high voltage level. 26. The method for sub-sampling pixels in the main animation pixel sensing array (APS) array as described in item 21 of the scope of patent application, wherein L is equal to N and equal to 4. 27. The method for subsampling celestial elements in an active celestial sensing field (PS) array as described in item 26 of the scope of patent application, wherein the four pixels are arranged & an array of rows and two columns, and the The first averaging job includes: averaging one of the first two rows in the first II to obtain a reset charge for the day element, and ^ obtaining the two reset charges in the second pair of pixels in the second row. A second identical line is averaged, and then the first identical line is averaged with the second identical line average_ 51 200533191 16323pif.doc. 28 · —A kind of image sensor, comprising: a pixel array of pixels in a row of pixels, an average cell in each frame including-a first and a second frame, wherein each second storage capacitor is used for Store ^ 2, device ', where the first and day prime reset data, and day prime from a second, the third and fourth storage electric brothers, and brother four storage capacitors, where, from the first The analog pixel number of the two pixels = from this -day element and the incoming material is stored as a charge. ° " Brother-Day Su's analogue reset is poor 30. For example, the scope of the patent application No. 28 image sensor includes a first-average opening, = read sensor, the image is used to perform including the storage Performing at least a single _ ^ Haidi-average switch average-the first-the average working thousand are 7 ° earlier than the _ ratio reset data t > 30 ^ * The analogy in the unit to perform includes including storing at least two average m, above Tiger profile average-second average job. In the image sensor described in item / 1, the ^ specialist ^, among them. The average work of the two brothers is performed in the field of analogy. 'Every-Pingshen is a special second = two image sensors. Its ¥ N storage capacitor is used to store 52 200533191 16323pif.doc from the Nth day. Analog video signal data. 3-4. The image sensor as described in the 28 items of the scope of patent application, the storage unit further includes:-The 2N storage capacitor, which is used to store the I pixel N axis axis reset data. 35. The image sensor described in claim 28 of the patent scope, each of: = to digital converter (ADC) 'is used to perform analog-to-digital conversion of several outputs from the second to early 7L . From 'Gu: The image sensor described in Item 35 of the scope of patent application, from which the U: J ί: = 器 (adc) is modified to perform the analogy to digital output of 17 Λ i to digital at the same time Conversion. An analog-to-digital converter (ADC) of the same bias source is composed of 38. As in the patent application, 'The bias is derived from the average' two m =, which is during the operation of the analog-to-digital converter; ; ::: The first voltage level is different from the second voltage level. In the “Slave position”, the image sensor described in the 31st item of the perimeter is designed to average the data. The pixel weight of each pixel in the same row is 40. As in Shen Qing's patent scope & ^, the second average 1 is used as the image sensor, and the image signal data is averaged. , 1; Analog images of the same day and day. 41. The image sensor described in item 28 of the scope of patent application 'its 53 2005331 ^ single Λ also includes-arranged in the-and the second storage capacitor _, _ Flat touch on _ Cai Ge daysu by ί 2. As the image sensor described in the scope of the patent application No. 28, its σα mother 彳 are single and include a storage capacitor placed in the third and fourth halls The average image signal · average switch is used to average the analog image signal data of each day element in the same row. 43. The image sensor according to item 28 of the scope of application for a patent, wherein the image sensor is a complementary metal oxide semiconductor CMOS type. 44. The image sensor described in item 28 of the scope of patent application, further comprising a digital signal processor. 45 · —A method of subsampling a celestial array arranged in a majority row and a plurality of columns. Each celestial element is modified to output a reset voltage and an image signal voltage. The method includes the following steps: · Storage Reset voltages from a plurality of daylight output in a first set of storage capacitors; Storing a plurality of image signal voltages output from a plurality of pixels in a second set of storage capacitors; merging a plurality of reset voltages stored in the first set of storage capacitors; and merging the storages stored in the second set of storage capacitors Most of the video signal voltages. 46. The method of sub-sampling a celestial array arranged in a plurality of rows and a plurality of columns as described in item 45 of the scope of patent application, further including a cascade method 54 200mm 47. The method of sampling pixels in a plurality of rows and in a series as described in item 45 of the scope of patent application, and further includes detecting across two or more of the first and second sets of storage. Voltage across a container in which m is connected in series. 48. The method of subsampling a pixel array arranged in a plurality of rows and a plurality of columns as described in item 45 of the scope of the patent application, further comprising digitally quantifying the span between the first and second sets of storages. Voltage across a storage capacitor in series between capacitors. 49 · A method of sub-sampling N2 day elements arranged in n rows and N columns of an active day element sensor (APS) array, each day element is modified to output a reset voltage and an image signal voltage, The method includes the following steps: storing a reset voltage of a first pixel as a first charge in a first capacitor; storing a reset voltage of a second pixel as a second in a second capacitor Charge; and combining the first and second charges into an average reset charge. 55