JP2532374B2 - Solid-state imaging device - Google Patents

Description

Description: FIELD OF THE INVENTION The present invention relates to a MOS solid-state image sensor suitable for realizing high sensitivity, low smear, and high resolution.

(Background of the Invention) Conventionally, a MOS has been used as a typical type of a two-dimensional solid-state image sensor.
Type solid-state image pickup devices are known (M. Aoki et.al: ISSC Digest of Technical Papers, p26, Feb. 13, 1980). The element has a circuit configuration as shown in FIG. In FIG. 6, reference numeral 1 denotes a photodiode arranged two-dimensionally for photoelectric conversion,
Reference numeral 2 is a vertical scanning circuit for selecting each row, 3 is a vertical gate line for guiding a selection signal from the vertical scanning circuit to each vertical switch, 4 is a vertical switch for opening and closing by a selection signal from the vertical scanning circuit, and 5 is a row switch for each row. Horizontal scanning circuit for selection,
Reference numeral 6 is a horizontal switch that opens and closes in response to a selection signal from the horizontal scanning circuit, 7 is an amplifier circuit outside the element, and 8 is a vertical signal line. The above circuit performs the following operations. First, during the horizontal blanking period, the voltage of the vertical gate line 3 in the row selected by the vertical scanning circuit 2 increases, the vertical switch 4 opens (turns on), and the signal charge is transferred from the photodiode 1 to the vertical signal line 8. Sent. After that, in the horizontal scanning period, the horizontal scanning circuit 5 operates and the horizontal switch 6 sequentially opens and closes, and the signal charges are sequentially amplified and output by the amplifier 7 outside the element.

The MOS type solid-state image pickup device described above has a simple structure of the light receiving portion including the photodiode 1 and the vertical switch 4 as compared with the CCD type solid-state image pickup device which is one of other typical two-dimensional solid-state image pickup devices. A high light utilization rate and a high yield can be obtained. However, the noise is large and the signal-to-noise ratio (hereinafter referred to as S / N ratio) is low.

On the other hand, in all solid-state imaging devices, when a bright subject is photographed, a vertical smear phenomenon in which white and white tails appear on the top and bottom of a reproduced image occurs, which causes image deterioration at high illuminance.

Further, in the future, a television system will be in the direction of higher definition, and as an example thereof, a system in which the number of scanning lines is 1125 and the aspect ratio of the screen is 3: 4 is drawing attention. A system using the above method needs to use a television camera having a signal bandwidth of 0 to 30 MHz (Kumada: Television Society, 1982 National Convention SP1-1, p.373). The solid-state imaging device used in the above-mentioned camera is required to have a scanning speed of 60 MHz or more, and in the conventional MOS type device or CCD type device, the experimental result shows that
It is difficult to realize with current technology.

(Object of the Invention) The present invention realizes a signal reading method capable of high-speed scanning while reducing noise and smear while maintaining a high signal utilization rate and a high yield of a MOS type solid-state imaging device.
The object is to obtain a solid-state image sensor having high resolution.

(Outline of the Invention) According to a study by the inventors, one of the main noise sources of a MOS type solid-state image sensor is kT generated by thermal noise of a horizontal switch.
It is C noise. The noise is generated when the reset potential of the vertical signal line fluctuates due to thermal noise of the horizontal switch when the horizontal switch opens and closes. The kTC noise is of the same kind as the reset noise generated at the output of the CCD solid-state image sensor. In the CCD device, in order to reduce the above noise, the correlated double sampling method (MHWHITE et a
l: Journal of Solid State Circuit,
vol.SC-9, No.1, p1-12, Feb.1974) is widely used. According to the present invention, a circuit for performing the above-mentioned correlated double sampling method is provided for each vertical signal line of a MOS type solid-state image pickup device to suppress kTC noise generated by thermal noise of a horizontal switch. Therefore, the present invention, on the same semiconductor substrate,
A photoelectric conversion element arranged two-dimensionally, a vertical scanning circuit and a horizontal scanning circuit for selecting the photoelectric conversion element,
In a solid-state imaging device including a vertical switch that opens and closes according to a selection signal of the vertical scanning circuit and has one end connected to the photoelectric conversion element, and a vertical signal line that connects one end of the vertical switch, the vertical signal line for each vertical signal line. First, the vertical signal line is reset by providing a reset switch for resetting the signal line and providing a means for detecting a difference between the empty vertical signal potential after reset and the vertical signal line potential when there is a signal. Then, only the kTC noise is output, then the signal charge is sent from the photodiode to the vertical signal line, the signal on which the kTC noise is superimposed is output, and the true signal is output by taking the difference between the above two. .

By the way, the vertical smear of the MOS type solid-state image pickup device occurs because extra charges are generated in the vertical signal line due to light leakage during one horizontal scanning period and are mixed into the signal charges. In the above-described device according to the present invention, since the signal charge is sent from the photodiode to the vertical signal line after resetting the vertical signal line, the time for smear signal mixing is 1 /
It can be reduced to 20 to 1/60 and therefore smear can be reduced.

On the other hand, as a very effective means of reducing vertical smear, Ozawa et al.
3-15, pp67, there is a smear differential method.
Another gist of the present invention is to provide a circuit for performing the smear differential method for each vertical signal line. Therefore, first, only the vertical smear is output, then the signal charge on which the vertical smear is superimposed is read out, and the signal charge is output by taking the difference between these two. Further, in order to perform high-speed scanning, in the device of the present invention, an amplifying means including an amplifier for amplifying a plurality of signal charges photoelectrically converted for each column in parallel, and respective outputs from the amplifying means for each column. The voltage is compared with a common staircase-like reference voltage, for each output of the amplifying means for each column, a staircase-like reference having a common end with a capacitor whose one end is connected to the output of the amplifying means for each output Comparing means having a switch connected to the voltage application terminal and having the other end connected to the other end of the capacitor, and a binary value representing the number of steps of a given common staircase wave synchronized with the change of the reference voltage. The digital data holding means provided for each of the comparing means selectively holds the data when the comparison result of each of the comparing means changes, and obtains a digital signal corresponding to each output voltage from the converted data. Be The digital signals of each column are scanned in series. According to this configuration, since the horizontal scanning is a digital system, the speed can be easily increased, which is suitable for high speed scanning. In addition, the staircase reference voltage required for A / D conversion and binary data representing the number of steps of the staircase can be made common to each column, and the output voltage holding means, the comparing means, and the digital value holding are held in each row. Since only the means is required, the amount of hardware required for A / D conversion can be reduced and high integration can be achieved. Further, since the reference voltage of the signal voltage matches the reference voltage of the common reference voltage, it is possible to eliminate the error of A / D conversion that occurs due to the variation of the DC output voltage of the amplification means provided for each column, and A / D conversion with high accuracy can be realized.

In order to realize the device of the present invention described above, an amplifier circuit for detecting and amplifying the potential of each vertical signal line is indispensable.
However, the gain of the amplifier provided on each vertical signal line is not uniform due to variations in the semiconductor manufacturing process. As a result, vertical stripe noise called fixed pattern noise occurs, and it becomes difficult to obtain high S / N. In order to suppress the fixed pattern noise, the device of the present invention uses A / D
It is intended to correct the variation in the output voltage of the amplification means for each column, which is caused by the variation in the voltage gain of each amplifier upon conversion.

Embodiments of the Invention Next, embodiments of the present invention will be described with reference to the drawings. First
FIG. 1 is a circuit configuration diagram showing an embodiment of a solid-state image sensor according to the present invention, and FIG. 2 shows a portion corresponding to 21, 22 of the circuit block for one column surrounded by the broken line in FIG. FIG. 3 is a diagram showing a detailed circuit, FIG. 3 is a timing diagram of drive pulses applied to corresponding terminals in FIG. 2, and FIG. 4 is a circuit block for one column surrounded by a broken line in FIG. 23 is a diagram showing a detailed circuit of a portion corresponding to 23, and FIG. 5 is a diagram showing timings of drive pulses applied to respective corresponding terminals in FIG. In order to simplify the explanation, FIG. 1 shows 3 × 4.
2 and 4 show only a circuit for one column surrounded by a broken line in FIGS. 2 and 4, and the output signal to the outside of the element is 3 bits and the correction signal is 2 bits. The case is shown.

In FIG. 1, 1 is a two-dimensionally arranged photodiode, 2 is a vertical scanning circuit for selecting each row, 3 is a vertical gate line, 4 is a vertical switch, 5 is a horizontal scanning circuit for selecting each column, and 8 is A vertical signal line, 21 is an amplifying means including a one-dimensionally arranged first-stage amplifier and a double sampling circuit for suppressing kTC noise, and 22 is also commonly used as a smear differential circuit for similarly smearing and suppressing smear. Comparator for A / D conversion and a reference voltage correction circuit for gain correction, which has an input section, and 23 is an output buffer for holding and outputting the result of A / D conversion, which is also arranged one-dimensionally And a gain correction signal holding circuit for holding gain correction information. In FIG. 2, the inside of the broken line shows the detailed circuit of the portion corresponding to 21 and 22 of the circuit block for one column surrounded by the broken line in FIG. 1, 31 to 34 and 45 are from 21 and 35 from above. 43, 46 to 50
Corresponds to 22 above, and terminals S1 to S5 and terminals outside the broken line
REEP, REF1, REF2, and R are 21-dimensionally arranged as described above.
In order to apply the driving pulse to 22 and 22, voltage application terminals are provided outside the array, A is connected to the vertical signal line 8, and B, C and D are detailed views of the above-mentioned 23 of FIG. E,
It is connected to F and G respectively. Reference numeral 31 in FIG. 2 is a reset switch for resetting the vertical signal line potential, 32
Is an initial stage amplifier for detecting and amplifying the potential fluctuation of the vertical signal line 8. A double sampling circuit that suppresses kTC noise is configured by 33, 34, and 45, and 33 is an amplifier,
3 is a switch for self-biasing the amplifier 33 in the high gain region, 45 is a switch 34 closed (off)
Sometimes it is the capacity for transmitting signals. Also, 37, 38,
48, 39, 40, 41 and the input section 35, 36, 46 which is also used as a smear differential circuit for suppressing smear, Nakatani et al .: Same as described in 1985 National Conference of IEICE 444 Of the sample-hold type MOS comparator is constructed, and 46 is a capacitance for transmitting a signal based on the reference voltage V _REFP of the reference voltage applied to the terminal REFP when the switch 36 is closed, and 35 is a signal by the capacitance 46. Buffer amplifier to prevent voltage attenuation during transmission, 36 is input to buffer amplifier 35
A switch for transmitting the reference voltage applied to the terminal REFP for A / D conversion, 47 is a capacitor for holding a signal, 37 is an amplifier, 38 is a switch for self-biasing the amplifier 37 in a high gain region, Reference numeral 48 is a capacitance for absorbing the adverse effect of the feedthrough charge of the switch 38, 39 is an amplifier, and 40 is a switch for self-biasing the amplifier 39 in the high gain region. In the comparative example of the above-mentioned document, the input part is composed of two switches for switching the signal voltage and the reference voltage, whereas in the comparative example of the present invention, the input and the switch 36 having one end connected to the reference voltage applying terminal REFP and the signal. It is composed of a capacitor 46 for transmitting a voltage. 42, 43, 49, 50 constitute a 2-bit reference voltage correction circuit for correcting the magnitude of one step of the reference voltage in accordance with the variation in each column of the amplifiers 32 and 33 in each column, Reference numerals 47, 42 and 43 are switches that are opened and closed by a signal from the gain correction signal holding circuit shown in FIG. 4, and 49 and 50 are capacitors that transmit the gain correction reference voltage applied to the terminals REF1 and REF2. S1 to S5 are drive pulse application terminals for switches 31, 34, 36, 42, 38 and 40, RE
FP is a staircase reference voltage application terminal for A / D conversion, RFE
Reference numerals 1 and REF2 are step-like gain correction reference voltage application terminals for correcting the gain variation of each column of the amplifiers 32 and 33, and R is a DC reset voltage application terminal of the vertical signal line. In addition, 101, 103, 105, 108, and 109 are switches 3 provided in each column from terminals S1 to S5 provided outside the array, respectively.
Wiring for transmitting drive pulse to 1, 34, 36, 42, 38, 40, 1
04 is a wiring for transmitting a staircase reference voltage from the terminal REFP provided outside the array to the input terminal of the switch 36 provided in each column, and 106 and 107 are terminals REF1 and RE provided outside the array.
Wiring for transmitting a staircase-shaped gain correction reference voltage from F2 to the input terminals of the switches 42 and 43 provided in each column, and 102 is a switch 31 provided in each column from a terminal R provided outside the array.
Is a wiring for transmitting the reset voltage to the input terminal of the. The gains of the amplifiers 32, 33, 35, 37, 39, 41 are respectively G ₁ ,
Let G ₂ , G ₃ , G ₄ , G ₅ , and G ₆ . In the drive pulse timing chart of FIG. 3, (b) to (f) are from the terminal S1 of FIG. 2, respectively.
Driving pulses applied to S5 are as follows: (h) to (j) are driving voltages applied to the terminals REFP, REF1 and REF2 in FIG. 2, and (g) is the vertical gate line 3 of the selected row in FIG. And (a) shows the horizontal blanking period. In the horizontal blanking period, the smear signal is read out first. The potential of S1 to S5 becomes high, and the switches 31, 34, 36,
38 and 40 open. At this time, the pseudo signal stored in the vertical signal line 8 such as smear is swept out of the element through the switch 31, and the vertical signal line 8 is reset to the voltage V _v applied to the terminal R. Further, the input terminal of the amplifier 35 is reset to the reference voltage V _REFP of the reference voltage (FIG. 3, t = t ₁ ). Next, the switch 31 is closed, and the vertical signal line potential is V _n due to kTC noise.
Only fluctuates (Fig. 3, t = t ₂ ). After that, when the switch 34 is closed after a certain time delay, the displacement variation of the output end of the amplifier 32 after this time is transmitted to the input terminal of the amplifier 33 through the capacitance 45 by capacitive coupling, and the amplifier 33 The potential fluctuation of the vertical signal line after this time is G ₁ ×
It appears after being multiplied by G ₂ (Fig. 3, t = t ₃ ). After this, when the switch 36 is closed after a lapse of time T _sl, the potential fluctuation at the output terminal of the amplifier 33 after this time causes the reference voltage V of the reference voltage applied to the terminal REFP by the capacitive coupling via the capacitor 46. _It is transmitted to the input terminal of the amplifier 35 with _REFP as a base point, and is multiplied by G _{3 and} appears at the output terminal of the amplifier 35. On the other hand, the vertical signal line displacement variation after time t ₃ is only the potential variation due to the generation of smear charges. Therefore, when the switch 36 is closed, the potential variation ΔV ₂ at the output end of the amplifier 33 is expressed by the equation (1).

ΔV ₂ = G ₁ G ₂ V _sm T _s1 (1) where V _sm is the vertical signal line potential fluctuation due to smear charge per unit time. That is, it is possible to obtain only the smear signal in which kTC noise is not mixed, and the double sampling is achieved (FIG. 3, t = t ₄ ).

Then, the signal charges are read out in the same manner. That is, the switch 31 is opened and closed again to reset the vertical signal line, and after the switch 34 is closed, the potential of a certain vertical gate line (FIGS. 1 and 3) becomes high, and the vertical gate line (FIGS. 1 and 1) becomes higher than the photodiode (FIGS. 1 and 1). Signal charges are sent to the vertical signal line 8. Switch 34 closes and time T _s2 passes before switch 38
Is closed, the amplifier 37 is activated, and the amplifier after this time
The potential fluctuation at the output terminal of 35 is multiplied by G ₄ and appears at the output terminal of the amplifier 37. Thereafter, after a certain delay, the switch 40 is closed and the amplifier 39 is activated.

The displacement variation ΔV ₂ ′ at the output terminal of the amplifier 33 at the time when the switch 38 is closed is as follows, similar to the equation (1).

ΔV ₂ ′ = G ₁ G ₂ (V _sm T _s2 + V _s ) (2) Here, V _s represents vertical signal line potential fluctuation due to signal charge. That is, a signal in which smear charge is added to signal charge in which kTC noise is not mixed is obtained. As a result, the potential fluctuation at the output end of the amplifier 33 after the switch 36 is closed at the time t4 is due to the capacitive coupling via the capacitor 46, and the terminal RE.
The reference voltage V _REFP of the reference voltage applied to FP is transmitted to the input terminal of the amplifier 35 as a base point, and G ₃ is output to the output terminal of the amplifier 35.
The output voltage of the amplifier 35 fluctuates by the amount shown in the equation (3) from the reference output when the reference voltage V _REFP is applied to the input terminal because it is multiplied.

ΔV ₃ = G ₁ G ₂ G ₃ {V _sm (T _s2 −T _s1 ) + V _s ) (3) Here, if T _s1 = T _s2 , the potential fluctuation ΔV ₃ at the output end of the amplifier 35 is given by the equation (4). become that way.

ΔV ₃ = G ₁ G ₂ G ₃ V _s (4) That is, the true signal component in which neither kTC noise nor smear signal is mixed can be amplified, and smear differential is achieved (Fig. 3). , T = t _s ).

Then, in the horizontal scanning period, A / D conversion is executed. Further, since the switch 38 does not open after this time, if the parasitic capacitance associated with the input terminal of the amplifier 37 is smaller than the capacitance 47, the voltage difference between both terminals of the capacitance 47 will be the other end of the capacitance 47. It becomes constant regardless of the voltage of the 35 output terminals. That is, the true signal voltage is held in the capacitor 47 without changing the voltage difference between the two terminals of the capacitor 47. First, the amplifiers 32 and 33 are deactivated. This is each amplifier
This is achieved by setting the power supply of 32 and 33 to a low level.
After that, when the voltage applied to the S3 terminal becomes high level and the switch 36 is opened, the input terminal of the amplifier 35 becomes the reference reference voltage V _REFP applied to the terminal REFP, and the output terminal voltage of the amplifier 35 also returns to the reference voltage ( FIG. 3, t = t ₆ ). At this time, the potential of the output end of the amplifier 35 is at the time when the signal reading is completed (see FIG. 3,
t = compared to t _5), changes by _{-G 1 G 2 G 3 V s} . As a result,
The output of the output terminal of the amplifier 41 changes by −G ₁ G ₂ G ₃ G ₄ G ₅ G ₆ V _s . Thereafter, when Yuku increased by [Delta] V _REFP reference voltage applied to the REFP terminal in a stepwise wave from the V _REFP, the output potential variation [Delta] V ₆ of the amplifier 41 is (5).

ΔV ₆ = G ₃ G ₄ G ₅ G ₆ (nΔV _REFP −G ₁ G ₂ V _s ) (5) where n is 0 when the voltage applied to the REF1 pin is V _REFP.
Is an integer that increases by 1 for each step of the staircase wave. Therefore, if the value of G ₃ G ₄ G ₅ G ₆ is sufficiently high, the output of the amplifier 41 changes from the high level to the low level when the step number n of the staircase is the following equation (6).

At this time, the level of the output of the amplifier 41 is detected, and the value of n is held in the output buffer to complete the A / D conversion.
Hereinafter, the operation for holding and outputting the A / D conversion result will be described in detail with reference to FIGS. 4 and 5.

In FIG. 4, the portion enclosed by the broken line in FIG.
A detailed circuit of a portion corresponding to 23 of the circuit blocks for columns is shown, and terminals D1 to D3 and terminals TG1 and TG2 outside the broken line are shown.
PC1, PC2 and terminals V _ss and V _cc are arranged one-dimensionally 21,
A voltage application terminal provided outside the array for applying a drive pulse to 22. Three pairs of 51, 52, 5 in the broken line in the figure
An output buffer configured to hold and output a 3-bit digital signal is constituted by 3, 54, and 55. When the output voltage of the amplifier 41 changes from a high level to a low level, 51 is connected to the terminals D1 to D3 in synchronization with the staircase wave. A switch for selecting a value corresponding to the true signal voltage held in FIG. 2 from the digital value representing the number of steps of the applied staircase and holding it at the capacitance node X, 52 is a voltage of the node X A switch that opens and closes depending on the level, 53 is a gate for transferring the level of the voltage held at the node X to the memory capacity 54, 54 is a buffer memory capacity for temporarily holding a digital signal, and 55 is a selection of the horizontal scanning circuit 5. Opens / closes according to a signal and the information in the memory capacity 54
It is a switch for reading to 56. Also, two pairs of 59,
A 2-bit gain correction signal holding circuit for holding the gain correction information is constituted by 60, 59 is a switch for reading the gain correction information into the node Y and opening / closing the switch 42 or 43 in FIG. 2, and 60 is A switch for resetting the voltage of the node Y. Further, 57 provided outside the array is a sense amplifier for discriminating between 1 and 0 of the digital signal held in the memory capacity 54 read out on the signal line 56, and 58 is for resetting the signal line 56. It is a precharge switch. D1 to D3 are terminals REFP and REF in Fig. 2.
1, a digital value representing the number of steps of the staircase applied to REF2 (high voltage state represents 1, low voltage state represents 0), the minimum bit value at terminal D1, the next bit value at terminal D2, The maximum bit value is applied to terminal D3. TG1, TG2, PC
1, PC2, respectively gates 53, switch 59, a precharge switch 58, the driving pulse applying terminal of the reset switch 60, the V _cc high DC voltage application terminal, V _ss is a low DC voltage application terminal. 111 is a wire for transmitting a digital value representing the number of steps of the staircase wave from the terminals D1 to D3 provided outside the array to the switch 51 provided in each column, and 113, 114 and 116 are terminals TG1 provided outside the array, respectively. , TG2, PC2 wiring to transmit the drive pulse to the switches 53, 59, 60 provided in each column,
112 is a wire for transmitting a high DC voltage from a terminal V _cc provided outside the array to an input terminal of the switch 52 provided in each column, 113
Is a wiring for transmitting a low DC voltage from the terminal V _ss provided outside the array to the input terminal of the switch 60 provided in each column.

In FIG. 5, (a) is a timing diagram of drive pulses in one horizontal scanning period of the circuit shown in FIG. 4, and (b) is a timing of drive pulses in the vertical blanking period of the circuit shown in FIG. It is a figure. (A) In the figure, (b) to (d) indicate the drive voltage applied to the terminals D1 to D3 in FIG. 4, respectively.
(E) and (g) show the drive pulses applied to the terminals TG1 and PC1, (f) and (g) show the two-phase scan pulses φ ₁ and φ ₂ of the horizontal scan circuit, and (a) show the horizontal pulse. Indicates the ranking period. The driving pulse applied to the terminal PC1 is equal to the scanning pulse φ ₂ of the horizontal scanning circuit. (B) In the figure (a)
And (d) show the drive pulse applied to the terminals PC2 and TG2 in FIG. 4, respectively, and (b) and (c) show the drive voltage applied to the terminals R and REFP in FIG. When the A / D conversion operation starts in the horizontal scanning period, the switch 36 is opened as described above, the input terminal of the amplifier 35 becomes the reference reference voltage V _REP applied to REFP, and the output of the amplifier 41 becomes the high voltage. become. As a result, the node X is reset to the low voltage indicating 0 applied to the terminals D1 to D3 (FIG. 5 (a) t =
t ₆ ). After that, the voltage applied to the terminal REFP changes in a staircase waveform, and the voltages at the terminals D1, D2, and D3 rise and fall in accordance with the step of the staircase wave. Note that D1 indicates the minimum bit, D2 indicates the next bit, and D3 indicates the maximum bit. When the step number n of the staircase wave becomes the expression (6), the output of the amplifier 41 changes from the high voltage to the low voltage, and the switch 51 closes. As a result, the node X holds the high and low voltages of the terminals D1, D2 and D3 at this time (FIG. 5 (a) t = t ₇ ). After this time, the voltage of REFP increases and the voltages of the terminals D1 and D2 continue to change, but the output of the amplifier 41 remains low, so the switch 51 remains closed. As a result, A /
The result of D conversion is obtained as the high and low voltage of the node X. The result of this A / D conversion is transferred to the memory capacity 54 by opening the transfer gate 53 before entering the next horizontal scanning period. That is, when a high voltage is held at the node X is the switch 52 is open, the high voltage applied to the terminal V _cc is written in the memory 54. Further, when the low voltage is held at the node X, the switch 52 is closed, so the voltage of the memory capacitor 54 remains the low voltage at the time of reset (FIG. 5 (a), t = t ₆ ). ). In the next scanning period, the information held in the memory capacity 54 is sequentially read. That is, the selection signal is sent in synchronization with the pulse φ ₁ of the horizontal scanning circuit 5, the switch 55 of a certain column is opened, the signal charge in the memory capacitor is read out to the signal line 56, and the memory capacitor 54 becomes low voltage. Will be reset. The charges read out to the signal line are detected by the sense amplifier 57 and read out of the element. After that, the switch 58 is opened in synchronization with another pulse φ ₂ of the horizontal scanning circuit and the signal line is connected to the terminal V.
It is precharged to the low voltage applied to _ss , and the next signal can be read out (t = t _{6 in} FIG. 5 (a)).

The operation for reading the optical signal is completed as described above. Next, the operation for gain correction will be described. The number of n indicating the digital value of the optical signal is given by the equation (6). Therefore, if the gains G ₁ and G ₂ vary from column to column, the vertical signal line potential fluctuation V _s due to the signal charges will result in different values of n even in columns having the same amount, and noise called vertical striped fixed pattern noise will result. Occurs. Therefore, this gain is corrected by changing the step size of the reference voltage for each column,
Suppress fixed pattern noise. Therefore, 5 shown in FIG.
Gain correction signal holding circuit consisting of 9 and 60 and 4 shown in FIG.
A reference voltage correction circuit composed of 2, 43, 49 and 50 is provided. The operation of gain correction will be described below with reference to the drive pulse timing shown in FIG.

In the vertical blanking period, an operation is performed to detect the gain variation in each column and hold the gain correction information as the voltage level of the node Y. That is, first, a high voltage is applied to the PC2 terminal, the switch 60 opens, and the node Y becomes V
The voltage becomes low as _ss (t = t _{9 in} FIG. 5 (b)). Then, an operation similar to that shown in FIG. 3 occurs. However, instead of increasing the voltage of the vertical gate line 3 selected at this time and reading the signal charge to the vertical signal line 8, the voltage of the R terminal is smeared during the time when the switch 31 is opened for signal reading. The vertical signal line 8 is changed by changing ΔR in comparison with the read voltage V _v.
, A pseudo signal voltage common to each column is generated (t = t _{10 in} FIG. 5 (b)). The fluctuation of the R terminal is amplified by the amplifier and A / D converted in the same manner as the optical signal. In this A / D conversion, the reference voltage applied to the REEP pin at the beginning of conversion is
V _REFP + NΔV _REFP Here, N indicates the maximum number of steps for A / D conversion, and 2 ^P for A / D conversion of P bits.
(FIG. 5 (b) t = t ₁₁ ). After that V _REFP is ΔV _REFP
It gradually increases in a staircase pattern, and A / D conversion is performed to obtain the value of m shown in equation (7).

That is, the difference between the amplified signal G ₁ G ₂ ΔR of ΔR and the maximum change value NΔV _REFP of the reference voltage is divided by the voltage step ΔV _REFP . Now, the expression (8) is selected so that ΔR becomes m = 0.

At this time, if the gain of a certain column is larger than those of the other columns by dG ₁ and dG ₂ , the gain correction signal m of the equation (9) can be obtained.

When the A / D conversion is completed, the value of m is held as a digital value as the voltage level of the node X. This value is the terminal TG
By increasing the voltage of ₂ , the gate 59 is opened and transferred to the node Y. As a result, depending on the value of the gain correction signal m,
The switches 42 and 43 are opened or closed, and the preparation for gain correction is completed (t = t _{12 in} FIG. 5 (b)).

Now, in this state, when A / D conversion of the signal is performed, REF
Not only the voltage of P but also the voltage of REFP1 and REFP2 is ΔV at the same time
Only _REF1 and ΔV _REF2 are changed in a staircase waveform. This voltage fluctuation appears as a change in the input terminal voltage of the amplifier 37 via the capacitors 49 and 50. As a result, the output displacement variation ΔV ₆ ′ of the amplifier 41 is given by equation (10).

Where c _p is the value of capacity 47, c _i (i = 1, 2) is capacity 49,
The value of 50, a _i (i = 1, 2), takes a value from 1 to 0 depending on the digital value of m. Therefore, the value of n'obtained is given by equation (11).

If there is no gain variation, a _i = 0 (i = 1-q)
Therefore, equation (11) is the same as equation (6). On the other hand, the gain of a certain column If the relational expression (12) holds, the correct A / D conversion result can be obtained regardless of the gain variation.

On the other hand, equation (13) is established from equation (9).

Therefore, if the relationship of the equation (14) holds between the capacitance c _i for inputting each reference voltage to the input terminal of the amplifier 37, the step ΔV _{REFi of the} reference voltage, and the gain G ₂ , the gain correction can be performed.

That is, the capacitance c _i is reduced by 2 ^ip of c _p , the reference voltage ΔV _REFi is reduced by 2 ^ip of ΔV _REFP , or G _{3 is set} to 2
Equation (14) should be satisfied by either of the three times ^ip or by a combination thereof.
Note that the above gain correction can be realized only when the gain varies in the positive direction. However, for a column in which the voltage applied to the R terminal is sufficiently large and the gains G ₁ and G ₂ are minimum, It is always possible if it is made up. Further, both positive and negative variations can be corrected.

In the above embodiment, by providing the double sampling circuit for each column, kTC noise due to the reset of the vertical signal line is not mixed in the signal and the sensitivity is high, and by providing the smear differential circuit for each column, smear is reduced. Low smear without mixing in the signal. Furthermore, the output voltage of the double sampling circuit described above for each column is compared with a common staircase-shaped reference voltage, and a comparator having a switch connected to the application terminal of the reference voltage with the capacitor and the reference voltage Of binary steps representing the number of steps of a common staircase wave that is given in synchronization with the change of the data, the data when the comparison result of the comparator changes is selectively held and the digital signal corresponding to each output voltage is obtained. Since it has an output buffer and scans the obtained digital signals in series, it is suitable for high-speed scanning, and
The amount of hardware for obtaining digital signals is also small,
High integration can be achieved, and highly accurate A / D conversion can be realized. Furthermore, by providing an amplifier for each column and reducing random noise, conversely, the gain variation of the amplifier, which is a problem, is corrected digitally by correcting the step of the reference voltage at the time of A / D conversion. It is possible to correct this gain variation.

(Advantages of the Invention) As described above, the solid-state imaging device according to the present invention includes an amplifying unit including an amplifier that amplifies a plurality of signal charges photoelectrically converted in each column in parallel, and an amplifying unit for each column. Comparing the output voltage of the above with a common staircase-like reference voltage, a comparing means provided for each output of the amplifying means for each column, and a common stepwise step provided in synchronization with the change of the reference voltage. A digital signal holding means provided for each comparing means for selectively holding the data when the comparison result of each comparing means changes, and obtaining a digital signal corresponding to each output voltage from the binarized data representing the number. An input part of the comparison means, one end of which is connected to the output of the amplification means, and one end of which is connected to a common staircase reference voltage application terminal and the other end of which is connected to the other end of the capacitance. It By providing such a switch, noise can be reduced, smear can be eliminated in principle, and high-speed scanning can be performed by scanning digital values without changing the configuration of the light receiving section of the MOS type solid-state image sensor. It is possible to realize a solid-state imaging device having high S / N, low smear, and high resolution.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram showing an embodiment of a solid-state image pickup device according to the present invention, and FIG. 2 is a view surrounded by a broken line 1 in FIG.
FIG. 4 is a diagram showing a detailed circuit of a portion corresponding to columns 21 and 22 of the circuit blocks for columns, FIG. 3 is a timing diagram of drive pulses applied to corresponding terminals in FIG. 2, and FIG. FIG. 5 is a diagram showing a detailed circuit of a portion corresponding to 23 of the circuit block for one column surrounded by a broken line in FIG. 1, and FIG. 5 shows the timing of the drive pulse applied to each terminal corresponding to FIG. FIG. 6 and FIG. 6 are circuit configuration diagrams of a conventional MOS type solid-state imaging device. 1 ... Photoelectric conversion element, 2 ... vertical scanning circuit 3 ... vertical gate line, 4 ... vertical switch 5 ... horizontal scanning circuit, 8 ... vertical signal line 21 ... consisting of first stage amplifier and double sampling circuit Amplification circuit 22 ... A / D with human power part shared with smear differential circuit
Comparator and reference voltage correction circuit for conversion 23 …… Output buffer and gain correction signal holding circuit for holding and outputting A / D conversion result 31 …… Reset switch, 32 …… First stage amplifier 33 …… Double Amplifier that constitutes the sampling circuit 34 ...... Switch for setting the amplifier 33 in the high gain region 35 …… Buffer amplifier that constitutes the smear differential circuit 36 …… Switches for transmitting the reference voltage 37, 39, 41 …… Comparison 38 for setting the amplifier 37 in the high gain region 40. Switches for setting the amplifier 39 in the high gain region 42, 43 ..... Switch 45 for forming the reference voltage correction circuit. … Capacity that constitutes the double sampling circuit 46 …… Capacity for transmitting the signal to the comparator, 47 …… Capacity for holding the signal 48 …… Capacity for absorbing feedthrough 49, 50 …… Reference voltage correction circuit Structure Capacitor 51 ... A switch 52 that selects a value corresponding to the true signal voltage held in the capacitor 47 from the digital value representing the number of steps of the staircase waves applied to the terminals D1 to D3 and holds it in the capacitor node X ... … Switch, 53 …… Transfer gate 54 …… Buffer memory capacity, 55 …… Reading switch 56 …… Signal line, 57 …… Sense amplifier 58 …… Precharge switch, 59 …… Gain correction information reading switch 60 …… Gain Correction signal holding circuit reset switch S1, S2, S3, S4, S5 ...... Drive voltage application terminal REFP …… Reference voltage application terminal REF1, REF2 …… Gain correction reference voltage application terminal R …… Vertical signal line DC reset voltage Application terminals D1, D2, D3: Application terminals for digital values that represent the number of steps of the staircase in synchronization with the staircase TG1, TG2, PC1, PC2 ... Drive voltage application terminal V _ss ... DC high voltage application terminal, V _cc: DC low voltage Applied terminal

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Masaaki Nakai 1-280 Higashi Koigakubo, Kokubunji City, Central Research Laboratory, Hitachi, Ltd. (72) Inventor Haruhisa Ando 1-280 Higashi Koigakubo, Kokubunji City, Hitachi Research Center, Ltd. ( 72) Inventor Hajime Akimoto 1-280, Higashi Koigakubo, Kokubunji City Central Research Laboratory, Hitachi, Ltd. (56) Reference JP 59-151455 (JP, A) JP 56-83127 (JP, A) JP A 59-143479 (JP, A) JP-A-60-150384 (JP, A)

Claims (6)

(57) [Claims] 1. A column-by-column amplifier having an amplifier provided for each column for amplifying a plurality of photoelectrically converted signal charges in parallel, and a common output voltage from each of the column-by-column amplifiers. Comparing means provided for each output of the amplifying means for each column for comparing with the staircase-shaped reference voltage, and binarization representing the number of steps of a common staircase wave given in synchronization with the change of the reference voltage From the data, select and hold the data when the comparison result of each comparison means changes,
A digital signal holding means provided for each of the comparing means for obtaining a digital signal corresponding to each output voltage, and a scanning means for serially scanning the obtained digital signal of each column,
On the same semiconductor substrate, the comparing means has one end connected to the output of the amplifying means and one end connected to a common staircase reference voltage application terminal, and the other end of the capacitance is the other end. A solid-state image sensor, comprising: an input unit having a switch connected to the. 2. Each of the comparison means and the digital signal holding means includes a correction means for correcting a variation in output voltage from the amplification means for each column, which is caused by a variation in voltage gain of the amplification means for each column. The solid-state image pickup device according to claim 1, wherein the solid-state image pickup device according to claim 1. 3. The amplifying means is connected between an output terminal of an amplifier provided for each column and a comparing means provided for each output of the amplifying means for each column, and the amplifying means of the amplifier is connected. The differential processing means for outputting a differential output between the amplifier first output when a signal charge is input to the input terminal and the amplifier second output when the amplifier input terminal is reset. The solid-state image sensor according to claim 1. 4. The photoelectric conversion is performed by a plurality of photoelectric conversion elements formed on the semiconductor substrate, and an input terminal of an amplifier for each column of a plurality of signal charges photoelectrically converted by the photoelectric conversion elements. The solid-state imaging device according to claim 3, wherein a selection switch for controlling reading to and from is formed on the semiconductor substrate. 5. A plurality of photoelectric conversion elements for performing the photoelectric conversion are arranged and formed in a horizontal and vertical two-dimensional shape on the semiconductor substrate, and an amplifier for each row is one vertical row of the photoelectric conversion elements. The solid-state image pickup device according to any one of claims 1 to 4, wherein the solid-state image pickup device is arranged for each. 6. The amplifying means is connected between an output terminal of an amplifier provided for each column and a comparing means provided for each output of the amplifying means for each column, and the amplifying means of the amplifier is connected. A difference processing means is provided for performing difference processing between an amplifier output when a signal charge mixed with smear charge is input to the input terminal and an amplifier output when only the smear charge is input to the input terminal of the amplifier. The solid-state image sensor according to claim 5, characterized in that